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Searched refs:CLK_TOP_DISP_PWM0 (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt8188-clk.h50 #define CLK_TOP_DISP_PWM0 39 macro
Dmt8195-clk.h54 #define CLK_TOP_DISP_PWM0 42 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8188-topckgen.c1048 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
Dclk-mt8195-topckgen.c978 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8195.dtsi1149 clocks = <&topckgen CLK_TOP_DISP_PWM0>,