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Searched refs:CLK_TOP_AUD_ENGEN1_SEL (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmt8516-clk.h178 #define CLK_TOP_AUD_ENGEN1_SEL 146 macro
Dmt6765-clk.h149 #define CLK_TOP_AUD_ENGEN1_SEL 114 macro
Dmediatek,mt8365-clk.h90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
Dmt8192-clk.h55 #define CLK_TOP_AUD_ENGEN1_SEL 43 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8516.c399 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
Dclk-mt8167.c588 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
Dclk-mt8365.c461 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
Dclk-mt8192.c649 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
Dclk-mt6765.c428 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8365.dtsi828 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
Dmt8192.dtsi1014 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,