| /linux-6.12.1/include/dt-bindings/clock/ |
| D | mt7986-clk.h | 38 #define CLK_TOP_APLL2_D4 15 macro
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| D | mediatek,mt7981-clk.h | 31 #define CLK_TOP_APLL2_D4 18 macro
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| D | mt8516-clk.h | 71 #define CLK_TOP_APLL2_D4 39 macro
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| D | mediatek,mt7988-clk.h | 42 #define CLK_TOP_APLL2_D4 14 macro
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| D | mediatek,mt8365-clk.h | 60 #define CLK_TOP_APLL2_D4 50 macro
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| D | mt6779-clk.h | 89 #define CLK_TOP_APLL2_D4 79 macro
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| D | mt2712-clk.h | 81 #define CLK_TOP_APLL2_D4 50 macro
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| D | mt8183-clk.h | 114 #define CLK_TOP_APLL2_D4 78 macro
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| D | mt8186-clk.h | 122 #define CLK_TOP_APLL2_D4 103 macro
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| D | mt8192-clk.h | 119 #define CLK_TOP_APLL2_D4 107 macro
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| D | mediatek,mt8188-clk.h | 145 #define CLK_TOP_APLL2_D4 134 macro
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| D | mt8195-clk.h | 178 #define CLK_TOP_APLL2_D4 166 macro
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| /linux-6.12.1/sound/soc/mediatek/mt8192/ |
| D | mt8192-afe-clk.c | 37 [CLK_TOP_APLL2_D4] = "top_apll2_d4",
171 afe_priv->clk[CLK_TOP_APLL2_D4]); in apll2_mux_setting()
175 aud_clks[CLK_TOP_APLL2_D4], ret); in apll2_mux_setting()
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| D | mt8192-afe-clk.h | 194 CLK_TOP_APLL2_D4, enumerator
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt7986-topckgen.c | 44 FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
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| D | clk-mt7981-topckgen.c | 41 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
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| D | clk-mt7988-topckgen.c | 38 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
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| D | clk-mt8186-topckgen.c | 57 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
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| D | clk-mt8516.c | 66 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
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| D | clk-mt8167.c | 73 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
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| D | clk-mt8183.c | 77 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
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| D | clk-mt8365.c | 82 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
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| D | clk-mt2712.c | 89 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
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| D | clk-mt8188-topckgen.c | 69 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
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| D | clk-mt8195-topckgen.c | 80 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
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