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Searched refs:CLK_TOP_APLL2 (Results 1 – 19 of 19) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmt8516-clk.h69 #define CLK_TOP_APLL2 37 macro
Dmediatek,mt6795-clk.h37 #define CLK_TOP_APLL2 26 macro
Dmt8173-clk.h36 #define CLK_TOP_APLL2 26 macro
Dmediatek,mt8365-clk.h58 #define CLK_TOP_APLL2 48 macro
Dmt2712-clk.h79 #define CLK_TOP_APLL2 48 macro
Dmt8192-clk.h117 #define CLK_TOP_APLL2 105 macro
Dmediatek,mt8188-clk.h84 #define CLK_TOP_APLL2 73 macro
Dmt8195-clk.h105 #define CLK_TOP_APLL2 93 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c387 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
Dclk-mt8173-topckgen.c462 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
Dclk-mt8516.c64 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
Dclk-mt8167.c71 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
Dclk-mt8365.c80 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
Dclk-mt2712.c87 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
Dclk-mt8188-topckgen.c1133 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
Dclk-mt8195-topckgen.c1102 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
Dclk-mt8192.c63 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi889 <&topckgen CLK_TOP_APLL2>;
Dmt8192.dtsi1013 <&topckgen CLK_TOP_APLL2>,