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Searched refs:CLK_TOP_A1SYS_SEL (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmt7986-clk.h72 #define CLK_TOP_A1SYS_SEL 49 macro
Dmediatek,mt7981-clk.h115 #define CLK_TOP_A1SYS_SEL 102 macro
Dmediatek,mt7988-clk.h88 #define CLK_TOP_A1SYS_SEL 60 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt7986-topckgen.c246 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
Dclk-mt7981-topckgen.c371 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
Dclk-mt7988-topckgen.c174 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,