Searched refs:CLK_RESET_CCLK_DIVIDER (Results 1 – 4 of 4) sorted by relevance
| /linux-6.12.1/arch/arm/mach-tegra/ |
| D | sleep.S | 23 #define CLK_RESET_CCLK_DIVIDER 0x24 macro
149 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
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| D | sleep-tegra20.S | 31 #define CLK_RESET_CCLK_DIVIDER 0x24 macro
202 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
289 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
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| D | sleep-tegra30.S | 44 #define CLK_RESET_CCLK_DIVIDER 0x24 macro
376 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
679 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-tegra30.c | 123 #define CLK_RESET_CCLK_DIVIDER 0x24 macro
1134 readl(clk_base + CLK_RESET_CCLK_DIVIDER); in tegra30_cpu_clock_suspend()
1176 clk_base + CLK_RESET_CCLK_DIVIDER); in tegra30_cpu_clock_resume()
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