Searched refs:CLK_PWM (Results 1 – 21 of 21) sorted by relevance
| /linux-6.12.1/include/dt-bindings/clock/ |
| D | exynos5410.h | 49 #define CLK_PWM 279 macro
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| D | thead,th1520-clk-ap.h | 61 #define CLK_PWM 51 macro
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| D | sophgo,cv1800.h | 71 #define CLK_PWM 60 macro
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| D | exynos5250.h | 115 #define CLK_PWM 311 macro
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| D | s5pv210.h | 155 #define CLK_PWM 137 macro
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| D | exynos4.h | 174 #define CLK_PWM 336 macro
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| D | exynos5420.h | 88 #define CLK_PWM 279 macro
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| D | exynos3250.h | 208 #define CLK_PWM 202 macro
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 213 GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
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| D | clk-s5pv210.c | 571 GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
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| D | clk-exynos5250.c | 598 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
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| D | clk-exynos3250.c | 655 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
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| D | clk-exynos4.c | 754 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
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| D | clk-exynos5420.c | 1096 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
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| /linux-6.12.1/arch/arm/boot/dts/samsung/ |
| D | exynos5410.dtsi | 329 clocks = <&clock CLK_PWM>;
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| D | s5pv210.dtsi | 291 clocks = <&clocks CLK_PWM>;
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| D | exynos4.dtsi | 668 clocks = <&clock CLK_PWM>;
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| D | exynos5250.dtsi | 1178 clocks = <&clock CLK_PWM>;
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| D | exynos5420.dtsi | 1301 clocks = <&clock CLK_PWM>;
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| /linux-6.12.1/drivers/clk/sophgo/ |
| D | clk-cv1800.c | 1089 [CLK_PWM] = &clk_pwm.common.hw,
1320 [CLK_PWM] = &clk_pwm.common.hw,
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| /linux-6.12.1/drivers/clk/thead/ |
| D | clk-th1520-ap.c | 809 static CCU_GATE(CLK_PWM, pwm_clk, "pwm", perisys_apb_pclk_pd, 0x204, BIT(18), 0);
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