Searched refs:CLK_PLL2_FIN (Results 1 – 2 of 2) sorted by relevance
2571 #define CLK_PLL2_FIN 48000000 macro2727 CLK_PLL2_FIN); in rt5682_wclk_set_rate()2729 if (parent_rate != CLK_PLL2_FIN) in rt5682_wclk_set_rate()2731 clk_name, CLK_PLL2_FIN); in rt5682_wclk_set_rate()2739 CLK_PLL2_FIN, clk_pll2_out); in rt5682_wclk_set_rate()
2512 #define CLK_PLL2_FIN 48000000 macro2660 CLK_PLL2_FIN); in rt5682s_wclk_set_rate()2662 if (parent_rate != CLK_PLL2_FIN) in rt5682s_wclk_set_rate()2664 clk_name, CLK_PLL2_FIN); in rt5682s_wclk_set_rate()2672 CLK_PLL2_FIN, clk_pll2_fout); in rt5682s_wclk_set_rate()