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Searched refs:CLK_PLL (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/clk/
Dclk-loongson2.c70 #define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \ macro
116 CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
117 CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
118 CLK_PLL(LOONGSON2_DC_PLL, "pll_soc", 0x10, 16, 8, 8, 6),
119 CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x18, 16, 8, 8, 6),
120 CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x20, 16, 8, 8, 6),
137 CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 32, 10, 26, 6),
138 CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x10, 32, 10, 26, 6),
139 CLK_PLL(LOONGSON2_DC_PLL, "pll_dc", 0x20, 32, 10, 26, 6),
140 CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 32, 10, 26, 6),
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Dclk-bm1880.c174 #define CLK_PLL(_id, _name, _parent, _reg, _flags) { \ macro
206 CLK_PLL(BM1880_CLK_MPLL, "clk_mpll", bm1880_pll_parent,
208 CLK_PLL(BM1880_CLK_SPLL, "clk_spll", bm1880_pll_parent,
210 CLK_PLL(BM1880_CLK_FPLL, "clk_fpll", bm1880_pll_parent,
212 CLK_PLL(BM1880_CLK_DDRPLL, "clk_ddrpll", bm1880_pll_parent,
/linux-6.12.1/drivers/clk/renesas/
Dr7s9210-cpg-mssr.c51 CLK_PLL, enumerator
63 DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
66 DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1),
77 DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1),
78 DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1),
79 DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1),
80 DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1),
81 DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1),
177 case CLK_PLL: in rza2_cpg_clk_register()
/linux-6.12.1/drivers/clk/microchip/
Dclk-mpfs.c136 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ macro
146 CLK_PLL(CLK_MSSPLL_INTERNAL, "clk_msspll_internal", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT,