| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8167.dtsi | 146 clocks = <&mmsys CLK_MM_SMI_LARB0>,
147 <&mmsys CLK_MM_SMI_LARB0>;
|
| D | mt2712e.dtsi | 1006 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1007 <&mmsys CLK_MM_SMI_LARB0>;
|
| D | mt8183.dtsi | 907 <&mmsys CLK_MM_SMI_LARB0>,
1864 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1865 <&mmsys CLK_MM_SMI_LARB0>;
|
| D | mt8173.dtsi | 1295 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1296 <&mmsys CLK_MM_SMI_LARB0>;
|
| D | mt6795.dtsi | 940 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>;
|
| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt6765-mm.c | 46 GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20),
|
| D | clk-mt2701-mm.c | 35 GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
| D | clk-mt8167-mm.c | 39 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1),
|
| D | clk-mt6797-mm.c | 34 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
| D | clk-mt6795-mm.c | 34 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
| D | clk-mt8183-mm.c | 37 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
| D | clk-mt6779-mm.c | 37 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
| D | clk-mt8173-mm.c | 38 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
| D | clk-mt2712-mm.c | 45 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
| /linux-6.12.1/include/dt-bindings/clock/ |
| D | mt8167-clk.h | 80 #define CLK_MM_SMI_LARB0 1 macro
|
| D | mediatek,mt6795-clk.h | 220 #define CLK_MM_SMI_LARB0 1 macro
|
| D | mt6797-clk.h | 216 #define CLK_MM_SMI_LARB0 2 macro
|
| D | mt8173-clk.h | 249 #define CLK_MM_SMI_LARB0 2 macro
|
| D | mt6765-clk.h | 271 #define CLK_MM_SMI_LARB0 20 macro
|
| D | mt6779-clk.h | 342 #define CLK_MM_SMI_LARB0 2 macro
|
| D | mt2712-clk.h | 302 #define CLK_MM_SMI_LARB0 1 macro
|
| D | mt8183-clk.h | 310 #define CLK_MM_SMI_LARB0 1 macro
|
| D | mt2701-clk.h | 354 #define CLK_MM_SMI_LARB0 2 macro
|
| /linux-6.12.1/arch/arm/boot/dts/mediatek/ |
| D | mt7623n.dtsi | 65 clocks = <&mmsys CLK_MM_SMI_LARB0>,
66 <&mmsys CLK_MM_SMI_LARB0>;
|
| D | mt2701.dtsi | 534 clocks = <&mmsys CLK_MM_SMI_LARB0>,
535 <&mmsys CLK_MM_SMI_LARB0>;
|