Searched refs:CLK_MM_DISP_WDMA0 (Results 1 – 20 of 20) sorted by relevance
| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt6765-mm.c | 37 GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11),
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| D | clk-mt8186-mm.c | 38 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "top_disp", 5),
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| D | clk-mt6797-mm.c | 54 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
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| D | clk-mt6795-mm.c | 54 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
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| D | clk-mt8183-mm.c | 61 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
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| D | clk-mt8192-mm.c | 48 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
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| D | clk-mt6779-mm.c | 61 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
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| D | clk-mt8173-mm.c | 57 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
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| D | clk-mt2712-mm.c | 65 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 240 #define CLK_MM_DISP_WDMA0 21 macro
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| D | mt6797-clk.h | 236 #define CLK_MM_DISP_WDMA0 22 macro
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| D | mt8173-clk.h | 268 #define CLK_MM_DISP_WDMA0 21 macro
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| D | mt6765-clk.h | 262 #define CLK_MM_DISP_WDMA0 11 macro
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| D | mt6779-clk.h | 365 #define CLK_MM_DISP_WDMA0 25 macro
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| D | mt2712-clk.h | 322 #define CLK_MM_DISP_WDMA0 21 macro
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| D | mt8183-clk.h | 333 #define CLK_MM_DISP_WDMA0 24 macro
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| D | mt8186-clk.h | 306 #define CLK_MM_DISP_WDMA0 5 macro
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| D | mt8192-clk.h | 429 #define CLK_MM_DISP_WDMA0 5 macro
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt6795.dtsi | 787 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
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| D | mt8173.dtsi | 1129 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
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