Searched refs:CLK_MM_DISP_RDMA0 (Results 1 – 25 of 25) sorted by relevance
| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt6765-mm.c | 36 GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10),
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| D | clk-mt8186-mm.c | 36 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "top_disp", 3),
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| D | clk-mt8167-mm.c | 49 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
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| D | clk-mt6797-mm.c | 52 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
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| D | clk-mt6795-mm.c | 51 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
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| D | clk-mt8183-mm.c | 59 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
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| D | clk-mt8192-mm.c | 46 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
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| D | clk-mt6779-mm.c | 59 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
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| D | clk-mt8173-mm.c | 54 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
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| D | clk-mt2712-mm.c | 62 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | mt8167-clk.h | 90 #define CLK_MM_DISP_RDMA0 11 macro
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| D | mediatek,mt6795-clk.h | 237 #define CLK_MM_DISP_RDMA0 18 macro
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| D | mt6797-clk.h | 234 #define CLK_MM_DISP_RDMA0 20 macro
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| D | mt8173-clk.h | 265 #define CLK_MM_DISP_RDMA0 18 macro
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| D | mt6765-clk.h | 261 #define CLK_MM_DISP_RDMA0 10 macro
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| D | mt6779-clk.h | 363 #define CLK_MM_DISP_RDMA0 23 macro
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| D | mt2712-clk.h | 319 #define CLK_MM_DISP_RDMA0 18 macro
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| D | mt8183-clk.h | 331 #define CLK_MM_DISP_RDMA0 22 macro
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| D | mt8186-clk.h | 304 #define CLK_MM_DISP_RDMA0 3 macro
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| D | mt8192-clk.h | 427 #define CLK_MM_DISP_RDMA0 3 macro
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt6795.dtsi | 757 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
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| D | mt8173.dtsi | 1099 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
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| D | mt8183.dtsi | 1762 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
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| D | mt8192.dtsi | 1531 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
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| D | mt8186.dtsi | 1838 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
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