Searched refs:CLK_MCU_MP0_SEL (Results 1 – 6 of 6) sorted by relevance
| /linux-6.12.1/include/dt-bindings/clock/ |
| D | mt2712-clk.h | 289 #define CLK_MCU_MP0_SEL 0 macro
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| D | mt8183-clk.h | 421 #define CLK_MCU_MP0_SEL 0 macro
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt8183.c | 611 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
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| D | clk-mt2712.c | 782 MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8183.dtsi | 334 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
357 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
380 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
403 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
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| D | mt2712e.dtsi | 89 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
102 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
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