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Searched refs:CLK_INFRA_MUX_SPI0_SEL (Results 1 – 2 of 2) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt7988-clk.h144 #define CLK_INFRA_MUX_SPI0_SEL 3 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt7988-infracfg.c65 MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,