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Searched refs:CLKID_VCLK_DIV6 (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Daxg-clkc.h135 #define CLKID_VCLK_DIV6 125 macro
Dgxbb-clkc.h196 #define CLKID_VCLK_DIV6 188 macro
Damlogic,s4-peripherals-clkc.h61 #define CLKID_VCLK_DIV6 51 macro
Dmeson8b-clkc.h153 #define CLKID_VCLK_DIV6 146 macro
Dg12a-clkc.h162 #define CLKID_VCLK_DIV6 151 macro
/linux-6.12.1/drivers/clk/meson/
Dmeson8b.c2923 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3127 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3342 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
Dgxbb.c2916 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
3123 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
Dg12a.c4533 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4760 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
5028 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
Daxg.c2020 [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
Ds4-peripherals.c3350 [CLKID_VCLK_DIV6] = &s4_vclk_div6.hw,