Searched refs:CG_SCLK_DPM_CTRL (Results 1 – 2 of 2) sorted by relevance
478 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()481 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()484 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()487 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()584 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()587 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()590 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()593 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_power_level_enable()
182 #define CG_SCLK_DPM_CTRL 0x684 macro