Searched refs:CACHELINE_BYTES (Results 1 – 13 of 13) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/i915/gt/ |
| D | intel_ring_types.h | 19 #define CACHELINE_BYTES 64 macro
20 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
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| D | intel_ring.h | 111 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid()
139 return (head - tail - CACHELINE_BYTES) & (size - 1); in __intel_ring_space()
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| D | intel_ring.c | 170 ring->effective_size -= 2 * CACHELINE_BYTES; in intel_engine_create_ring()
317 num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); in intel_ring_cacheline_align()
331 GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); in intel_ring_cacheline_align()
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| D | intel_engine.h | 32 #define CACHELINE_BYTES 64 macro
33 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
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| D | intel_lrc.c | 807 GEM_BUG_ON(!IS_ALIGNED(size, CACHELINE_BYTES)); in lrc_setup_indirect_ctx()
810 ctx_bb_ggtt_addr | (size / CACHELINE_BYTES); in lrc_setup_indirect_ctx()
1472 while ((unsigned long)cs % CACHELINE_BYTES) in setup_indirect_ctx_bb()
1698 while ((unsigned long)batch % CACHELINE_BYTES) in gen8_init_indirectctx_bb()
1795 while ((unsigned long)batch % CACHELINE_BYTES) in gen9_init_indirectctx_bb()
1897 CACHELINE_BYTES))) { in lrc_init_wa_ctx()
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| /linux-6.12.1/drivers/gpu/drm/xe/ |
| D | xe_guc_submit_types.h | 28 #define CACHELINE_BYTES 64 macro
40 u8 unused[CACHELINE_BYTES - sizeof(u32)];
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| /linux-6.12.1/arch/powerpc/lib/ |
| D | string_32.S | 16 CACHELINE_BYTES = L1_CACHE_BYTES define
51 addi r6, r6, CACHELINE_BYTES
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| D | checksum_32.S | 120 CACHELINE_BYTES = L1_CACHE_BYTES define
180 addi r3,r3,CACHELINE_BYTES
184 addi r3,r3,CACHELINE_BYTES
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| D | copy_32.S | 61 CACHELINE_BYTES = L1_CACHE_BYTES define
124 addi r6,r6,CACHELINE_BYTES
374 addi r3,r3,CACHELINE_BYTES
378 addi r3,r3,CACHELINE_BYTES
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_dsb.c | 20 #define CACHELINE_BYTES 64 macro
451 aligned_tail = ALIGN(tail, CACHELINE_BYTES); in intel_dsb_align_tail()
527 if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) in _intel_dsb_chain()
589 if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) in _intel_dsb_commit()
720 size = ALIGN(max_cmds * 8, CACHELINE_BYTES); in intel_dsb_prepare()
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| /linux-6.12.1/drivers/gpu/drm/i915/gvt/ |
| D | scheduler.c | 623 0, CACHELINE_BYTES, 0); in prepare_shadow_wa_ctx()
644 memset(per_ctx_va, 0, CACHELINE_BYTES); in prepare_shadow_wa_ctx()
1713 CACHELINE_BYTES; in intel_vgpu_create_workload()
1732 CACHELINE_BYTES)) { in intel_vgpu_create_workload()
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| D | cmd_parser.c | 2891 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES, in scan_wa_ctx()
3009 roundup(ctx_size + CACHELINE_BYTES, in shadow_indirect_ctx()
3064 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES); in combine_wa_ctx()
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| /linux-6.12.1/drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_submission.c | 431 u8 unused[CACHELINE_BYTES - sizeof(u32)];
467 BUILD_BUG_ON(sizeof(struct sync_semaphore) != CACHELINE_BYTES); in __get_parent_scratch()
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