Searched refs:Base (Results 1 – 25 of 162) sorted by relevance
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42 specific LPC part. Base clocks are numbered from 0 to 27.45 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT46 1 BASE_USB0_CLK Base clock for USB047 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,49 3 BASE_USB1_CLK Base clock for USB152 5 BASE_SPIFI_CLK Base clock for SPIFI53 6 BASE_SPI_CLK Base clock for SPI54 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock55 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock56 9 BASE_APB1_CLK Base clock for APB peripheral block # 1[all …]
1 * Time Base Generator Clock bindings for Marvell Armada 37xx SoCs3 Marvell Armada 37xx SoCs provide Time Base Generator clocks which are
40 pair is located at the HWM Base Address + 0 and the HWM Base Address + 1. The41 HWM Base address can be obtained from Logical Device 8, registers 0x60 (MSB)42 and 0x61 (LSB). Currently we are using 0x480 for the HWM Base Address and170 Obtaining the HWM Base Address173 The following is an example of how to read the HWM Base Address located in191 OUT DX,AL ; Point to HWM Base Addr MSB193 IN AL,DX ; Get MSB of HWM Base Addr
13 IOMMU: dmar0 Register Base Address: 26be3700024 IOMMU: dmar1 Register Base Address: fed9000035 IOMMU: dmar2 Register Base Address: fed91000131 Base: 0x10022e000 Head: 20 Tail: 20145 Base: 0x10026e000 Head: 32 Tail: 32191 IOMMU: dmar0 Register Base Address: 26be37000200 IOMMU: dmar2 Register Base Address: fed91000213 IOMMU: dmar0 Register Base Address: 26be37000
35 0x80000000 0x0010 /* NAND Base DATA */36 0x80020000 0x0010 /* NAND Base ADDR */37 0x80010000 0x0010>; /* NAND Base CMD */
30 0x40000000 0x0010 /* NAND Base DATA */31 0x40020000 0x0010 /* NAND Base ADDR */32 0x40010000 0x0010>; /* NAND Base CMD */
37 0x50000000 0x0010 /* NAND Base DATA */38 0x50020000 0x0010 /* NAND Base ADDR */39 0x50010000 0x0010>; /* NAND Base CMD */
77 0xd2000000 0x0010 /* NAND Base DATA */78 0xd2020000 0x0010 /* NAND Base ADDR */79 0xd2010000 0x0010>; /* NAND Base CMD */
140 0xb0800000 0x0010 /* NAND Base DATA */141 0xb0820000 0x0010 /* NAND Base ADDR */142 0xb0810000 0x0010>; /* NAND Base CMD */
3 * Caninos Labrador Base Board13 model = "Caninos Labrador Core v2 on Labrador Base-M v1";
12 model = "LeMaker Guitar Base Board rev. B";
3 * Marvell OpenRD Base Board Description16 model = "OpenRD Base";
3 * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)12 model = "SolidRun Clearfog Base A1";
66 +--------------------------------------------------+ Base74 +-----------------------+--------------------------+ Base + span_offset79 +-----------------------+--------------------------+ Base + span_offset
596 | Offs|Base |I/O Addr |621 S1 1-3: I/O Base Address Select622 4-6: Memory Base Address Select645 Setting the I/O Base Address649 of eight possible I/O Base addresses using the following table::665 Setting the Base Memory (RAM) buffer Address670 Switches 4-6 of switch group S1 select the Base of the 16K block.829 SW1 1-6: I/O Base Address Select886 Setting the I/O Base Address890 of 32 possible I/O Base addresses using the following table::[all …]
47 0xd2000000 0x0010 /* NAND Base DATA */48 0xd2020000 0x0010 /* NAND Base ADDR */49 0xd2010000 0x0010>; /* NAND Base CMD */
89 0x4000 Inbound List Base Address Low90 0x4004 Inbound List Base Address High93 0x4050 Outbound List Base Address Low94 0x4054 Outbound List Base Address High95 0x4058 Outbound List Copy Pointer Shadow Base Address Low96 0x405C Outbound List Copy Pointer Shadow Base Address High
29 mov r1, #0x10000000 @ Base address of TC6393 chip43 ldr r1, .W100ADDR @ Base address of w100 chip + regs offset129 mov r1, #0x0c000000 @ Base address of NAND chip
84 | Arguments: | (uint64) | R1 | Base IPA of memory region to share |109 | Arguments: | (uint64) | R1 | Base IPA of memory region to unshare |135 | Arguments: | (uint64) | R1 | Base IPA of MMIO memory region |
14 hex '(S)DRAM Base Address' if SET_MEM_PARAM22 hex 'FLASH Base Address' if SET_MEM_PARAM
19 echo Base file $base unreadable!!!
38 power-isa-b; // Base40 power-isa-atb; // Alternate Time Base
4 Linux Base Driver for WangXun(R) 10 Gigabit PCI Express Adapters