Searched refs:BMC (Results 1 – 25 of 131) sorted by relevance
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| /linux-6.12.1/drivers/char/ipmi/ |
| D | Kconfig | 74 Provides a driver for a SMBus interface to a BMC, meaning that you
83 It supports normal system interface messages to a BMC on the IPMB
113 tristate "Aspeed KCS IPMI BMC driver"
118 The driver implements the BMC side of the KCS contorller, it
119 provides the access of KCS IO space for BMC side.
125 tristate "NPCM KCS IPMI BMC driver"
130 The driver implements the BMC side of the KCS contorller, it
131 provides the access of KCS IO space for BMC side.
138 tristate "IPMI character device interface for BMC KCS devices"
140 Provides a BMC-side character device implementing IPMI
[all …]
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| /linux-6.12.1/arch/arm/mach-npcm/ |
| D | Kconfig | 10 bool "Support for WPCM450 BMC (Hermon)"
16 General support for WPCM450 BMC (Hermon).
18 Winbond/Nuvoton WPCM450 BMC based on the ARM926EJ-S.
21 bool "Support for NPCM7xx BMC (Poleg)"
38 General support for NPCM7xx BMC (Poleg).
40 Nuvoton NPCM7xx BMC based on the Cortex A9.
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-driver-intel-m10-bmc | 6 MAX10 BMC chip.
14 BMC chip.
23 that is managed by the Intel MAX10 BMC. It is stored in
24 FLASH storage and is mirrored in the MAX10 BMC register
34 MAX10 BMC. This value is stored in FLASH and is mirrored
35 in the MAX10 BMC register space.
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| /linux-6.12.1/Documentation/hwmon/ |
| D | intel-m10-bmc-hwmon.rst | 8 * Intel MAX 10 BMC for Intel PAC N3000
19 support for the Intel MAX 10 Board Management Controller (BMC) chip.
20 The BMC chip is integrated in some Intel Programmable Acceleration
22 sensor data of different components on the board. The BMC firmware is
27 The BMC chip is implemented using the Intel MAX 10 CPLD. It could be
30 variants, but now it only supports the BMC for Intel PAC N3000.
38 - Intel MAX 10 BMC for Intel PAC N3000:
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| D | ftsteutates.rst | 18 The BMC Teutates is the Eleventh generation of Superior System
20 functionality of the BMC Theseus and contains several new features and
30 The 4 voltages require a board-specific multiplier, since the BMC can
42 /Services/Software_Tools/Linux_SystemMonitoring_Watchdog_GPIO/BMC-Teutates_Specification_V1.21.pdf
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| D | menf21bmc.rst | 17 The menf21bmc is a Board Management Controller (BMC) which provides an I2C
18 interface to the host to access the features implemented in the BMC.
22 The voltage sensors are connected to the ADC inputs of the BMC which is
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| D | sbrmi.rst | 9 device connected to the BMC via the APML.
17 management controller (BMC) to the CPU.
41 power sensor's I2C interface to BMC.
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| D | ibmaem.rst | 27 available on various IBM System X hardware through the BMC. All sensor banks
33 last BMC reset, and a power sensor that returns average power use over a
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| /linux-6.12.1/drivers/soc/aspeed/ |
| D | Kconfig | 14 also provides a read/write interface to a BMC ram region where the
24 allows the BMC to listen on and save the data written by
38 tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"
43 Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The
53 Say yes to support decoding of ASPEED BMC information.
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| /linux-6.12.1/Documentation/devicetree/bindings/spi/ |
| D | nuvoton,npcm-fiu.txt | 14 - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
15 "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
33 In the NPCM7XX BMC:
38 In the NPCM8XX BMC:
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| /linux-6.12.1/Documentation/ABI/stable/ |
| D | sysfs-driver-aspeed-vuart | 5 will appear on the host <-> BMC LPC bus.
13 the UART will appear on the host <-> BMC LPC bus.
21 host via the BMC LPC bus.
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| /linux-6.12.1/drivers/peci/controller/ |
| D | Kconfig | 11 AST2500 and AST2600 SoCs. It allows BMC to discover devices
15 as BMC for Intel platform.
27 and NPCM8XX SoCs. It allows BMC to discover devices connected
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| /linux-6.12.1/arch/arm/boot/dts/aspeed/ |
| D | aspeed-bmc-facebook-tiogapass.dts | 11 model = "Facebook TiogaPass BMC";
99 // SoL BMC Console
104 // BMC Console
109 // BMC KCS channel 2
115 // BMC KCS channel 3
131 "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC",
132 "CPU1_PROCHOT_LVT3_ BMC",
437 // BMC Debug Header
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| D | aspeed-bmc-facebook-elbert.dts | 9 model = "Facebook Elbert BMC";
188 * BMC's "mac3" controller is connected to BCM53134P's IMP_RGMII port
190 * Note: BMC's "mdio0" controller is connected to BCM53134P's MDIO
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| D | aspeed-bmc-tyan-s8036.dts | 9 model = "Tyan S8036 BMC";
125 /* BMC "debug" (console) UART; connected to RS-232 connector
143 * BMC.
231 /* BMC EEPROM, incl. mainboard FRU */
370 /* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
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| D | aspeed-bmc-asrock-spc621d8hm3.dts | 11 model = "ASRock SPC621D8HM3 BMC";
32 /* BMC heartbeat */
102 /* motherboard temp sensor (TMP1, near BMC) */
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| D | aspeed-bmc-portwell-neptune.dts | 9 model = "Portwell Neptune BMC";
73 // BMC Console
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| D | aspeed-bmc-tyan-s7106.dts | 9 model = "Tyan S7106 BMC";
125 /* BMC "debug" (console) UART; connected to RS-232 connector
143 * BMC.
273 /* BMC EEPROM, incl. mainboard FRU */
416 /* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
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| /linux-6.12.1/Documentation/devicetree/bindings/misc/ |
| D | aspeed-p2a-ctrl.txt | 6 In this case, the host has access to a 64KiB window into all of the BMC's
7 memory. The BMC can disable this bridge. If the bridge is enabled, the host
9 and write access depending on a register controlled by the BMC.
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | nuvoton,npcm750-clk.txt | 3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
4 generates and supplies clocks to all modules within the BMC.
8 There are six fixed clocks that are generated outside the BMC. All clocks are of
23 Poleg BMC NPCM750
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| /linux-6.12.1/Documentation/driver-api/ |
| D | ipmb.rst | 8 between the baseboard management (BMC) and chassis electronics.
17 When an IPMB is implemented in the system, the BMC serves as
18 a controller to give system software access to the IPMB. The BMC
21 sends a response back to the BMC.
30 receive IPMB messages from a BMC and send a response back.
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| /linux-6.12.1/Documentation/devicetree/bindings/edac/ |
| D | aspeed-sdram-edac.txt | 1 Aspeed BMC SoC EDAC node
3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
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| /linux-6.12.1/arch/arm/mach-hpe/ |
| D | Kconfig | 5 This enables support for HPE ARM based BMC chips.
16 BMC features at HPE. It supports ARMv7 architecture based on the Cortex
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| /linux-6.12.1/arch/arm/mach-aspeed/ |
| D | Kconfig | 3 bool "Aspeed BMC architectures"
11 Say Y here if you want to run your kernel on an ASpeed BMC SoC.
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| /linux-6.12.1/drivers/hwmon/occ/ |
| D | Kconfig | 13 can only run on a baseboard management controller (BMC) connected to
27 can only run on a baseboard management controller (BMC) connected to
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