Searched refs:BIT10 (Results 1 – 10 of 10) sorted by relevance
65 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11); in PHY_RF6052SetBandwidth8723B()71 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10); in PHY_RF6052SetBandwidth8723B()
375 ODM_BB_PATH_DIV = BIT10,
22 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
204 #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */233 #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */
27 #define BIT10 0x00000400 macro
41 #define BIT10 0x00000400 macro
29 #define BIT10 0x0400 macro
66 #define BIT10 0x00000400 macro
385 #define IRQ_RXDATA BIT102043 if (count == info->rbuf_fill_level || (reg & BIT10)) { in isr_rxdata()4184 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()4186 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4188 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4190 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4257 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()4259 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4261 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4263 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
777 #define LPFC_SLI4_INTR10 BIT10