1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_TXRX_H__
6 #define __RTW89_TXRX_H__
7
8 #include "debug.h"
9
10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
11 #define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8)
12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
13 #define DATA_RATE_MODE_NON_HT 0x0
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
16 #define DATA_RATE_MODE_HT 0x1
17 #define DATA_RATE_HT_NSS_MASK GENMASK(4, 3)
18 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
19 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)
20 #define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5)
21 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
22 #define DATA_RATE_MODE_VHT 0x2
23 #define DATA_RATE_MODE_HE 0x3
24 #define DATA_RATE_MODE_EHT 0x4
25
rtw89_get_data_rate_mode(struct rtw89_dev * rtwdev,u16 hw_rate)26 static inline u8 rtw89_get_data_rate_mode(struct rtw89_dev *rtwdev, u16 hw_rate)
27 {
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
29 return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK_V1);
30
31 return u16_get_bits(hw_rate, DATA_RATE_MODE_CTRL_MASK);
32 }
33
rtw89_get_data_not_ht_idx(struct rtw89_dev * rtwdev,u16 hw_rate)34 static inline u8 rtw89_get_data_not_ht_idx(struct rtw89_dev *rtwdev, u16 hw_rate)
35 {
36 return u16_get_bits(hw_rate, DATA_RATE_NOT_HT_IDX_MASK);
37 }
38
rtw89_get_data_ht_mcs(struct rtw89_dev * rtwdev,u16 hw_rate)39 static inline u8 rtw89_get_data_ht_mcs(struct rtw89_dev *rtwdev, u16 hw_rate)
40 {
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
42 return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK_V1);
43
44 return u16_get_bits(hw_rate, DATA_RATE_HT_IDX_MASK);
45 }
46
rtw89_get_data_mcs(struct rtw89_dev * rtwdev,u16 hw_rate)47 static inline u8 rtw89_get_data_mcs(struct rtw89_dev *rtwdev, u16 hw_rate)
48 {
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
50 return u16_get_bits(hw_rate, DATA_RATE_MCS_MASK_V1);
51
52 return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_IDX_MASK);
53 }
54
rtw89_get_data_ht_nss(struct rtw89_dev * rtwdev,u16 hw_rate)55 static inline u8 rtw89_get_data_ht_nss(struct rtw89_dev *rtwdev, u16 hw_rate)
56 {
57 return u16_get_bits(hw_rate, DATA_RATE_HT_NSS_MASK);
58 }
59
rtw89_get_data_nss(struct rtw89_dev * rtwdev,u16 hw_rate)60 static inline u8 rtw89_get_data_nss(struct rtw89_dev *rtwdev, u16 hw_rate)
61 {
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
63 return u16_get_bits(hw_rate, DATA_RATE_NSS_MASK_V1);
64
65 return u16_get_bits(hw_rate, DATA_RATE_VHT_HE_NSS_MASK);
66 }
67
68 /* TX WD BODY DWORD 0 */
69 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
70 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
74 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
75 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11)
76 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
77 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
78 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)
79 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0)
80
81 /* TX WD BODY DWORD 1 */
82 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
83 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
84 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4)
85 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
86
87 /* TX WD BODY DWORD 2 */
88 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
89 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
90 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17)
91 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0)
92
93 /* TX WD BODY DWORD 3 */
94 #define RTW89_TXWD_BODY3_BK BIT(13)
95 #define RTW89_TXWD_BODY3_AGG_EN BIT(12)
96 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0)
97
98 /* TX WD BODY DWORD 4 */
99 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
100 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16)
101
102 /* TX WD BODY DWORD 5 */
103 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
104 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16)
105 #define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8)
106 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)
107
108 /* TX WD BODY DWORD 6 (V1) */
109
110 /* TX WD BODY DWORD 7 (V1) */
111 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
112 #define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28)
113 #define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25)
114 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)
115
116 /* TX WD INFO DWORD 0 */
117 #define RTW89_TXWD_INFO0_USE_RATE BIT(30)
118 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28)
119 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25)
120 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)
121 #define RTW89_TXWD_INFO0_DATA_ER BIT(15)
122 #define RTW89_TXWD_INFO0_DATA_STBC BIT(12)
123 #define RTW89_TXWD_INFO0_DATA_LDPC BIT(11)
124 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10)
125 #define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8)
126 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4)
127
128 /* TX WD INFO DWORD 1 */
129 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
130 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
131 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)
132
133 /* TX WD INFO DWORD 2 */
134 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18)
135 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9)
136 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8)
137 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8)
138 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
139
140 /* TX WD INFO DWORD 3 */
141
142 /* TX WD INFO DWORD 4 */
143 #define RTW89_TXWD_INFO4_RTS_EN BIT(27)
144 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
145
146 /* TX WD INFO DWORD 5 */
147
148 /* TX WD BODY DWORD 0 */
149 #define BE_TXD_BODY0_EN_HWSEQ_MODE GENMASK(1, 0)
150 #define BE_TXD_BODY0_HW_SSN_SEL GENMASK(4, 2)
151 #define BE_TXD_BODY0_HWAMSDU BIT(5)
152 #define BE_TXD_BODY0_HW_SEC_IV BIT(6)
153 #define BE_TXD_BODY0_WD_PAGE BIT(7)
154 #define BE_TXD_BODY0_CHK_EN BIT(8)
155 #define BE_TXD_BODY0_WP_INT BIT(9)
156 #define BE_TXD_BODY0_STF_MODE BIT(10)
157 #define BE_TXD_BODY0_HDR_LLC_LEN GENMASK(15, 11)
158 #define BE_TXD_BODY0_CH_DMA GENMASK(19, 16)
159 #define BE_TXD_BODY0_SMH_EN BIT(20)
160 #define BE_TXD_BODY0_PKT_OFFSET BIT(21)
161 #define BE_TXD_BODY0_WDINFO_EN BIT(22)
162 #define BE_TXD_BODY0_MOREDATA BIT(23)
163 #define BE_TXD_BODY0_WP_OFFSET_V1 GENMASK(27, 24)
164 #define BE_TXD_BODY0_AZ_FTM_SEC_V1 BIT(28)
165 #define BE_TXD_BODY0_WD_SOURCE GENMASK(30, 29)
166 #define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31)
167
168 /* TX WD BODY DWORD 1 */
169 #define BE_TXD_BODY1_DMA_TXAGG_NUM GENMASK(6, 0)
170 #define BE_TXD_BODY1_REUSE_NUM GENMASK(11, 7)
171 #define BE_TXD_BODY1_SEC_TYPE GENMASK(15, 12)
172 #define BE_TXD_BODY1_SEC_KEYID GENMASK(17, 16)
173 #define BE_TXD_BODY1_SW_SEC_IV BIT(18)
174 #define BE_TXD_BODY1_REUSE_SIZE GENMASK(23, 20)
175 #define BE_TXD_BODY1_REUSE_START_OFFSET GENMASK(25, 24)
176 #define BE_TXD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
177
178 /* TX WD BODY DWORD 2 */
179 #define BE_TXD_BODY2_TXPKTSIZE GENMASK(13, 0)
180 #define BE_TXD_BODY2_AGG_EN BIT(14)
181 #define BE_TXD_BODY2_BK BIT(15)
182 #define BE_TXD_BODY2_MACID_EXTEND BIT(16)
183 #define BE_TXD_BODY2_QSEL GENMASK(22, 17)
184 #define BE_TXD_BODY2_TID_IND BIT(23)
185 #define BE_TXD_BODY2_MACID GENMASK(31, 24)
186
187 /* TX WD BODY DWORD 3 */
188 #define BE_TXD_BODY3_WIFI_SEQ GENMASK(11, 0)
189 #define BE_TXD_BODY3_MLO_FLAG BIT(12)
190 #define BE_TXD_BODY3_IS_MLD_SW_EN BIT(13)
191 #define BE_TXD_BODY3_TRY_RATE BIT(14)
192 #define BE_TXD_BODY3_RELINK_FLAG_V1 BIT(15)
193 #define BE_TXD_BODY3_BAND0_SU_TC_V1 GENMASK(21, 16)
194 #define BE_TXD_BODY3_TOTAL_TC GENMASK(27, 22)
195 #define BE_TXD_BODY3_RU_RTY BIT(28)
196 #define BE_TXD_BODY3_MU_PRI_RTY BIT(29)
197 #define BE_TXD_BODY3_MU_2ND_RTY BIT(30)
198 #define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
199
200 /* TX WD BODY DWORD 4 */
201 #define BE_TXD_BODY4_TXDESC_CHECKSUM GENMASK(15, 0)
202 #define BE_TXD_BODY4_SEC_IV_L0 GENMASK(23, 16)
203 #define BE_TXD_BODY4_SEC_IV_L1 GENMASK(31, 24)
204
205 /* TX WD BODY DWORD 5 */
206 #define BE_TXD_BODY5_SEC_IV_H2 GENMASK(7, 0)
207 #define BE_TXD_BODY5_SEC_IV_H3 GENMASK(15, 8)
208 #define BE_TXD_BODY5_SEC_IV_H4 GENMASK(23, 16)
209 #define BE_TXD_BODY5_SEC_IV_H5 GENMASK(31, 24)
210
211 /* TX WD BODY DWORD 6 */
212 #define BE_TXD_BODY6_MU_TC GENMASK(4, 0)
213 #define BE_TXD_BODY6_RU_TC GENMASK(9, 5)
214 #define BE_TXD_BODY6_PS160 BIT(10)
215 #define BE_TXD_BODY6_BMC BIT(11)
216 #define BE_TXD_BODY6_NO_ACK BIT(12)
217 #define BE_TXD_BODY6_UPD_WLAN_HDR BIT(13)
218 #define BE_TXD_BODY6_A4_HDR BIT(14)
219 #define BE_TXD_BODY6_EOSP_BIT BIT(15)
220 #define BE_TXD_BODY6_S_IDX GENMASK(23, 16)
221 #define BE_TXD_BODY6_RU_POS GENMASK(31, 24)
222
223 /* TX WD BODY DWORD 7 */
224 #define BE_TXD_BODY7_RTS_TC GENMASK(5, 0)
225 #define BE_TXD_BODY7_MSDU_NUM GENMASK(9, 6)
226 #define BE_TXD_BODY7_DATA_ER BIT(10)
227 #define BE_TXD_BODY7_DATA_BW_ER BIT(11)
228 #define BE_TXD_BODY7_DATA_DCM BIT(12)
229 #define BE_TXD_BODY7_GI_LTF GENMASK(15, 13)
230 #define BE_TXD_BODY7_DATARATE GENMASK(27, 16)
231 #define BE_TXD_BODY7_DATA_BW GENMASK(30, 28)
232 #define BE_TXD_BODY7_USERATE_SEL BIT(31)
233
234 /* TX WD INFO DWORD 0 */
235 #define BE_TXD_INFO0_MBSSID GENMASK(3, 0)
236 #define BE_TXD_INFO0_MULTIPORT_ID GENMASK(6, 4)
237 #define BE_TXD_INFO0_DISRTSFB BIT(9)
238 #define BE_TXD_INFO0_DISDATAFB BIT(10)
239 #define BE_TXD_INFO0_DATA_LDPC BIT(11)
240 #define BE_TXD_INFO0_DATA_STBC BIT(12)
241 #define BE_TXD_INFO0_DATA_TXCNT_LMT GENMASK(21, 16)
242 #define BE_TXD_INFO0_DATA_TXCNT_LMT_SEL BIT(22)
243 #define BE_TXD_INFO0_RESP_PHYSTS_CSI_EN_V1 BIT(23)
244 #define BE_TXD_INFO0_RLS_TO_CPUIO BIT(30)
245 #define BE_TXD_INFO0_ACK_CH_INFO BIT(31)
246
247 /* TX WD INFO DWORD 1 */
248 #define BE_TXD_INFO1_MAX_AGG_NUM GENMASK(7, 0)
249 #define BE_TXD_INFO1_BCN_SRCH_SEQ GENMASK(9, 8)
250 #define BE_TXD_INFO1_NAVUSEHDR BIT(10)
251 #define BE_TXD_INFO1_A_CTRL_BQR BIT(12)
252 #define BE_TXD_INFO1_A_CTRL_BSR BIT(14)
253 #define BE_TXD_INFO1_A_CTRL_CAS BIT(15)
254 #define BE_TXD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(27, 16)
255 #define BE_TXD_INFO1_SW_DEFINE GENMASK(31, 28)
256
257 /* TX WD INFO DWORD 2 */
258 #define BE_TXD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
259 #define BE_TXD_INFO2_FORCE_KEY_EN BIT(8)
260 #define BE_TXD_INFO2_LIFETIME_SEL GENMASK(15, 13)
261 #define BE_TXD_INFO2_FORCE_TXOP BIT(17)
262 #define BE_TXD_INFO2_AMPDU_DENSITY GENMASK(20, 18)
263 #define BE_TXD_INFO2_LSIG_TXOP_EN BIT(21)
264 #define BE_TXD_INFO2_OBW_CTS2SELF_DUP_TYPE GENMASK(29, 26)
265 #define BE_TXD_INFO2_SPE_RPT_V1 BIT(30)
266 #define BE_TXD_INFO2_SIFS_TX_V1 BIT(31)
267
268 /* TX WD INFO DWORD 3 */
269 #define BE_TXD_INFO3_SPE_PKT GENMASK(3, 0)
270 #define BE_TXD_INFO3_SPE_PKT_TYPE GENMASK(7, 4)
271 #define BE_TXD_INFO3_CQI_SND BIT(8)
272 #define BE_TXD_INFO3_RTT_EN BIT(9)
273 #define BE_TXD_INFO3_HT_DATA_SND_V1 BIT(10)
274 #define BE_TXD_INFO3_BT_NULL BIT(11)
275 #define BE_TXD_INFO3_TRI_FRAME BIT(12)
276 #define BE_TXD_INFO3_NULL_0 BIT(13)
277 #define BE_TXD_INFO3_NULL_1 BIT(14)
278 #define BE_TXD_INFO3_RAW BIT(15)
279 #define BE_TXD_INFO3_GROUP_BIT_IE_OFFSET GENMASK(23, 16)
280 #define BE_TXD_INFO3_SIGNALING_TA_PKT_EN BIT(25)
281 #define BE_TXD_INFO3_BCNPKT_TSF_CTRL BIT(26)
282 #define BE_TXD_INFO3_SIGNALING_TA_PKT_SC GENMASK(30, 27)
283 #define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31)
284
285 /* TX WD INFO DWORD 4 */
286 #define BE_TXD_INFO4_PUNCTURE_PATTERN GENMASK(15, 0)
287 #define BE_TXD_INFO4_PUNC_MODE GENMASK(17, 16)
288 #define BE_TXD_INFO4_SW_TX_OK_0 BIT(18)
289 #define BE_TXD_INFO4_SW_TX_OK_1 BIT(19)
290 #define BE_TXD_INFO4_SW_TX_PWR_DBM GENMASK(26, 23)
291 #define BE_TXD_INFO4_RTS_EN BIT(27)
292 #define BE_TXD_INFO4_CTS2SELF BIT(28)
293 #define BE_TXD_INFO4_CCA_RTS GENMASK(30, 29)
294 #define BE_TXD_INFO4_HW_RTS_EN BIT(31)
295
296 /* TX WD INFO DWORD 5 */
297 #define BE_TXD_INFO5_SR_RATE_V1 GENMASK(4, 0)
298 #define BE_TXD_INFO5_SR_EN_V1 BIT(5)
299 #define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16)
300
301 /* TX WD INFO DWORD 6 */
302 #define BE_TXD_INFO6_UL_APEP_LEN GENMASK(11, 0)
303 #define BE_TXD_INFO6_UL_GI_LTF GENMASK(14, 12)
304 #define BE_TXD_INFO6_UL_DOPPLER BIT(15)
305 #define BE_TXD_INFO6_UL_STBC BIT(16)
306 #define BE_TXD_INFO6_UL_LENGTH_REF GENMASK(21, 18)
307 #define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22)
308
309 /* TX WD INFO DWORD 7 */
310 #define BE_TXD_INFO7_UL_FIXED_GAIN_EN BIT(0)
311 #define BE_TXD_INFO7_UL_PRI_EXP_RSSI_DBM GENMASK(7, 1)
312 #define BE_TXD_INFO7_ELNA_IDX BIT(8)
313 #define BE_TXD_INFO7_UL_APEP_UNIT GENMASK(10, 9)
314 #define BE_TXD_INFO7_UL_TRI_PAD GENMASK(13, 11)
315 #define BE_TXD_INFO7_UL_T_PE GENMASK(15, 14)
316 #define BE_TXD_INFO7_UL_EHT_USR_PRES BIT(16)
317 #define BE_TXD_INFO7_UL_HELTF_SYMBOL_NUM GENMASK(19, 17)
318 #define BE_TXD_INFO7_ULBW GENMASK(21, 20)
319 #define BE_TXD_INFO7_ULBW_EXT GENMASK(23, 22)
320 #define BE_TXD_INFO7_USE_WD_UL GENMASK(25, 24)
321 #define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28)
322
323 /* RX WD dword0 */
324 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0)
325 #define AX_RXD_SHIFT_MASK GENMASK(15, 14)
326 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16)
327 #define AX_RXD_BB_SEL BIT(22)
328 #define AX_RXD_MAC_INFO_VLD BIT(23)
329 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24)
330 #define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28)
331 #define AX_RXD_LONG_RXD BIT(31)
332
333 /* RX WD dword1 */
334 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)
335 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4)
336 #define AX_RXD_SR_EN BIT(7)
337 #define AX_RXD_USER_ID_MASK GENMASK(15, 8)
338 #define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8)
339 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)
340 #define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25)
341 #define AX_RXD_NON_SRG_PPDU BIT(28)
342 #define AX_RXD_INTER_PPDU BIT(29)
343 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
344 #define AX_RXD_INTER_PPDU_v1 BIT(15)
345 #define AX_RXD_BW_MASK GENMASK(31, 30)
346 #define AX_RXD_BW_v1_MASK GENMASK(31, 29)
347
348 /* RX WD dword2 */
349 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
350
351 /* RX WD dword3 */
352 #define AX_RXD_A1_MATCH BIT(0)
353 #define AX_RXD_SW_DEC BIT(1)
354 #define AX_RXD_HW_DEC BIT(2)
355 #define AX_RXD_AMPDU BIT(3)
356 #define AX_RXD_AMPDU_END_PKT BIT(4)
357 #define AX_RXD_AMSDU BIT(5)
358 #define AX_RXD_AMSDU_CUT BIT(6)
359 #define AX_RXD_LAST_MSDU BIT(7)
360 #define AX_RXD_BYPASS BIT(8)
361 #define AX_RXD_CRC32_ERR BIT(9)
362 #define AX_RXD_ICV_ERR BIT(10)
363 #define AX_RXD_MAGIC_WAKE BIT(11)
364 #define AX_RXD_UNICAST_WAKE BIT(12)
365 #define AX_RXD_PATTERN_WAKE BIT(13)
366 #define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14)
367 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16)
368 #define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21)
369 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
370 #define AX_RXD_WITH_LLC BIT(25)
371 #define AX_RXD_RX_STATISTICS BIT(26)
372
373 /* RX WD dword4 */
374 #define AX_RXD_TYPE_MASK GENMASK(1, 0)
375 #define AX_RXD_MC BIT(2)
376 #define AX_RXD_BC BIT(3)
377 #define AX_RXD_MD BIT(4)
378 #define AX_RXD_MF BIT(5)
379 #define AX_RXD_PWR BIT(6)
380 #define AX_RXD_QOS BIT(7)
381 #define AX_RXD_TID_MASK GENMASK(11, 8)
382 #define AX_RXD_EOSP BIT(12)
383 #define AX_RXD_HTC BIT(13)
384 #define AX_RXD_QNULL BIT(14)
385 #define AX_RXD_SEQ_MASK GENMASK(27, 16)
386 #define AX_RXD_FRAG_MASK GENMASK(31, 28)
387
388 /* RX WD dword5 */
389 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0)
390 #define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8)
391 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16)
392 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24)
393 #define AX_RXD_ADDR_CAM_VLD BIT(28)
394 #define AX_RXD_ADDR_FWD_EN BIT(29)
395 #define AX_RXD_RX_PL_MATCH BIT(30)
396
397 /* RX WD dword6 */
398 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
399
400 /* RX WD dword7 */
401 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
402 #define AX_RXD_SMART_ANT BIT(16)
403 #define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17)
404 #define AX_RXD_HDR_CNV BIT(21)
405 #define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22)
406 #define AX_RXD_BIP_KEYID BIT(27)
407 #define AX_RXD_BIP_ENC BIT(28)
408
409 struct rtw89_rxinfo_user {
410 __le32 w0;
411 };
412
413 #define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0)
414 #define RTW89_RXINFO_USER_DATA BIT(1)
415 #define RTW89_RXINFO_USER_CTRL BIT(2)
416 #define RTW89_RXINFO_USER_MGMT BIT(3)
417 #define RTW89_RXINFO_USER_BCN BIT(4)
418 #define RTW89_RXINFO_USER_MACID GENMASK(15, 8)
419
420 struct rtw89_rxinfo {
421 __le32 w0;
422 __le32 w1;
423 struct rtw89_rxinfo_user user[];
424 } __packed;
425
426 #define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0)
427 #define RTW89_RXINFO_W0_USR_NUM_V1 GENMASK(4, 0)
428 #define RTW89_RXINFO_W0_FW_DEFINE GENMASK(15, 8)
429 #define RTW89_RXINFO_W0_PLCP_LEN_V1 GENMASK(23, 16)
430 #define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16)
431 #define RTW89_RXINFO_W0_INVALID_V1 BIT(27)
432 #define RTW89_RXINFO_W0_IS_TO_SELF BIT(28)
433 #define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29)
434 #define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)
435 #define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0)
436 #define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16)
437
438 struct rtw89_phy_sts_hdr {
439 __le32 w0;
440 __le32 w1;
441 } __packed;
442
443 #define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0)
444 #define RTW89_PHY_STS_HDR_W0_HDR_2_EN BIT(5)
445 #define RTW89_PHY_STS_HDR_W0_VALID BIT(7)
446 #define RTW89_PHY_STS_HDR_W0_LEN GENMASK(15, 8)
447 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
448 #define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0)
449 #define RTW89_PHY_STS_HDR_W1_RSSI_B GENMASK(15, 8)
450 #define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16)
451 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
452
453 struct rtw89_phy_sts_hdr_v2 {
454 __le32 w0;
455 __le32 w1;
456 } __packed;
457
458 #define RTW89_PHY_STS_HDR_V2_W0_PATH_EN GENMASK(20, 16)
459
460 struct rtw89_phy_sts_iehdr {
461 __le32 w0;
462 };
463
464 #define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0)
465 #define RTW89_PHY_STS_IEHDR_LEN GENMASK(11, 5)
466
467 /* BE RXD dword0 */
468 #define BE_RXD_RPKT_LEN_MASK GENMASK(13, 0)
469 #define BE_RXD_SHIFT_MASK GENMASK(15, 14)
470 #define BE_RXD_DRV_INFO_SZ_MASK GENMASK(19, 18)
471 #define BE_RXD_HDR_CNV_SZ_MASK GENMASK(21, 20)
472 #define BE_RXD_PHY_RPT_SZ_MASK GENMASK(23, 22)
473 #define BE_RXD_RPKT_TYPE_MASK GENMASK(29, 24)
474 #define BE_RXD_BB_SEL BIT(30)
475 #define BE_RXD_LONG_RXD BIT(31)
476
477 /* BE RXD dword1 */
478 #define BE_RXD_PKT_ID_MASK GENMASK(11, 0)
479 #define BE_RXD_FWD_TARGET_MASK GENMASK(23, 16)
480 #define BE_RXD_BCN_FW_INFO_MASK GENMASK(25, 24)
481 #define BE_RXD_FW_RLS BIT(26)
482
483 /* BE RXD dword2 */
484 #define BE_RXD_MAC_ID_MASK GENMASK(7, 0)
485 #define BE_RXD_TYPE_MASK GENMASK(11, 10)
486 #define BE_RXD_LAST_MSDU BIT(12)
487 #define BE_RXD_AMSDU_CUT BIT(13)
488 #define BE_RXD_ADDR_CAM_VLD BIT(14)
489 #define BE_RXD_REORDER BIT(15)
490 #define BE_RXD_SEQ_MASK GENMASK(27, 16)
491 #define BE_RXD_TID_MASK GENMASK(31, 28)
492
493 /* BE RXD dword3 */
494 #define BE_RXD_SEC_TYPE_MASK GENMASK(3, 0)
495 #define BE_RXD_BIP_KEYID BIT(4)
496 #define BE_RXD_BIP_ENC BIT(5)
497 #define BE_RXD_CRC32_ERR BIT(6)
498 #define BE_RXD_ICV_ERR BIT(7)
499 #define BE_RXD_HW_DEC BIT(8)
500 #define BE_RXD_SW_DEC BIT(9)
501 #define BE_RXD_A1_MATCH BIT(10)
502 #define BE_RXD_AMPDU BIT(11)
503 #define BE_RXD_AMPDU_EOF BIT(12)
504 #define BE_RXD_AMSDU BIT(13)
505 #define BE_RXD_MC BIT(14)
506 #define BE_RXD_BC BIT(15)
507 #define BE_RXD_MD BIT(16)
508 #define BE_RXD_MF BIT(17)
509 #define BE_RXD_PWR BIT(18)
510 #define BE_RXD_QOS BIT(19)
511 #define BE_RXD_EOSP BIT(20)
512 #define BE_RXD_HTC BIT(21)
513 #define BE_RXD_QNULL BIT(22)
514 #define BE_RXD_A4_FRAME BIT(23)
515 #define BE_RXD_FRAG_MASK GENMASK(27, 24)
516 #define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30)
517
518 /* BE RXD dword4 */
519 #define BE_RXD_PPDU_TYPE_MASK GENMASK(7, 0)
520 #define BE_RXD_PPDU_CNT_MASK GENMASK(10, 8)
521 #define BE_RXD_BW_MASK GENMASK(14, 12)
522 #define BE_RXD_RX_GI_LTF_MASK GENMASK(18, 16)
523 #define BE_RXD_RX_REORDER_FIELD_EN BIT(19)
524 #define BE_RXD_RX_DATARATE_MASK GENMASK(31, 20)
525
526 /* BE RXD dword5 */
527 #define BE_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
528
529 /* BE RXD dword6 */
530 #define BE_RXD_ADDR_CAM_MASK GENMASK(7, 0)
531 #define BE_RXD_SR_EN BIT(13)
532 #define BE_RXD_NON_SRG_PPDU BIT(14)
533 #define BE_RXD_INTER_PPDU BIT(15)
534 #define BE_RXD_USER_ID_MASK GENMASK(21, 16)
535 #define BE_RXD_RX_STATISTICS BIT(22)
536 #define BE_RXD_SMART_ANT BIT(23)
537 #define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24)
538
539 /* BE RXD dword7 */
540 #define BE_RXD_PATTERN_IDX_MASK GENMASK(4, 0)
541 #define BE_RXD_MAGIC_WAKE BIT(5)
542 #define BE_RXD_UNICAST_WAKE BIT(6)
543 #define BE_RXD_PATTERN_WAKE BIT(7)
544 #define BE_RXD_RX_PL_MATCH BIT(8)
545 #define BE_RXD_RX_PL_ID_MASK GENMASK(15, 12)
546 #define BE_RXD_HDR_CNV BIT(16)
547 #define BE_RXD_NAT25_HIT BIT(17)
548 #define BE_RXD_IS_DA BIT(18)
549 #define BE_RXD_CHKSUM_OFFLOAD_EN BIT(19)
550 #define BE_RXD_RXSC_ENTRY_MASK GENMASK(22, 20)
551 #define BE_RXD_RXSC_HIT BIT(23)
552 #define BE_RXD_WITH_LLC BIT(24)
553 #define BE_RXD_RX_AGG_FIELD_EN BIT(25)
554
555 /* BE RXD dword8 */
556 #define BE_RXD_MAC_ADDR_MASK GENMASK(31, 0)
557
558 /* BE RXD dword9 */
559 #define BE_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
560 #define BE_RXD_HDR_OFFSET_MASK GENMASK(20, 16)
561 #define BE_RXD_WL_HD_IV_LEN_MASK GENMASK(26, 21)
562
563 struct rtw89_phy_sts_ie00 {
564 __le32 w0;
565 __le32 w1;
566 __le32 w2;
567 __le32 w3;
568 } __packed;
569
570 #define RTW89_PHY_STS_IE00_W0_RPL GENMASK(15, 7)
571
572 struct rtw89_phy_sts_ie00_v2 {
573 __le32 w0;
574 __le32 w1;
575 __le32 w2;
576 __le32 w3;
577 __le32 w4;
578 __le32 w5;
579 __le32 w6;
580 __le32 w7;
581 } __packed;
582
583 #define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A GENMASK(8, 0)
584 #define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B GENMASK(17, 9)
585 #define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C GENMASK(26, 18)
586 #define RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D GENMASK(8, 0)
587
588 struct rtw89_phy_sts_ie01 {
589 __le32 w0;
590 __le32 w1;
591 __le32 w2;
592 __le32 w3;
593 __le32 w4;
594 __le32 w5;
595 } __packed;
596
597 #define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16)
598 #define RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD GENMASK(15, 8)
599 #define RTW89_PHY_STS_IE01_W0_RX_PATH_EN GENMASK(31, 28)
600 #define RTW89_PHY_STS_IE01_W1_FD_CFO GENMASK(19, 8)
601 #define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)
602 #define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0)
603 #define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8)
604 #define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16)
605 #define RTW89_PHY_STS_IE01_W2_LDPC BIT(28)
606 #define RTW89_PHY_STS_IE01_W2_STBC BIT(30)
607
608 struct rtw89_phy_sts_ie01_v2 {
609 __le32 w0;
610 __le32 w1;
611 __le32 w2;
612 __le32 w3;
613 __le32 w4;
614 __le32 w5;
615 __le32 w6;
616 __le32 w7;
617 __le32 w8;
618 __le32 w9;
619 } __packed;
620
621 #define RTW89_PHY_STS_IE01_V2_W5_BW_IDX GENMASK(31, 29)
622 #define RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A GENMASK(11, 4)
623 #define RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B GENMASK(23, 16)
624 #define RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C GENMASK(11, 4)
625 #define RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D GENMASK(23, 16)
626
627 enum rtw89_tx_channel {
628 RTW89_TXCH_ACH0 = 0,
629 RTW89_TXCH_ACH1 = 1,
630 RTW89_TXCH_ACH2 = 2,
631 RTW89_TXCH_ACH3 = 3,
632 RTW89_TXCH_ACH4 = 4,
633 RTW89_TXCH_ACH5 = 5,
634 RTW89_TXCH_ACH6 = 6,
635 RTW89_TXCH_ACH7 = 7,
636 RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */
637 RTW89_TXCH_CH9 = 9, /* HI Band 0 */
638 RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */
639 RTW89_TXCH_CH11 = 11, /* HI Band 1 */
640 RTW89_TXCH_CH12 = 12, /* FW CMD */
641
642 /* keep last */
643 RTW89_TXCH_NUM,
644 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
645 };
646
647 enum rtw89_rx_channel {
648 RTW89_RXCH_RXQ = 0,
649 RTW89_RXCH_RPQ = 1,
650
651 /* keep last */
652 RTW89_RXCH_NUM,
653 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1
654 };
655
656 enum rtw89_tx_qsel {
657 RTW89_TX_QSEL_BE_0 = 0x00,
658 RTW89_TX_QSEL_BK_0 = 0x01,
659 RTW89_TX_QSEL_VI_0 = 0x02,
660 RTW89_TX_QSEL_VO_0 = 0x03,
661 RTW89_TX_QSEL_BE_1 = 0x04,
662 RTW89_TX_QSEL_BK_1 = 0x05,
663 RTW89_TX_QSEL_VI_1 = 0x06,
664 RTW89_TX_QSEL_VO_1 = 0x07,
665 RTW89_TX_QSEL_BE_2 = 0x08,
666 RTW89_TX_QSEL_BK_2 = 0x09,
667 RTW89_TX_QSEL_VI_2 = 0x0a,
668 RTW89_TX_QSEL_VO_2 = 0x0b,
669 RTW89_TX_QSEL_BE_3 = 0x0c,
670 RTW89_TX_QSEL_BK_3 = 0x0d,
671 RTW89_TX_QSEL_VI_3 = 0x0e,
672 RTW89_TX_QSEL_VO_3 = 0x0f,
673 RTW89_TX_QSEL_B0_BCN = 0x10,
674 RTW89_TX_QSEL_B0_HI = 0x11,
675 RTW89_TX_QSEL_B0_MGMT = 0x12,
676 RTW89_TX_QSEL_B0_NOPS = 0x13,
677 RTW89_TX_QSEL_B0_MGMT_FAST = 0x14,
678 /* reserved */
679 /* reserved */
680 /* reserved */
681 RTW89_TX_QSEL_B1_BCN = 0x18,
682 RTW89_TX_QSEL_B1_HI = 0x19,
683 RTW89_TX_QSEL_B1_MGMT = 0x1a,
684 RTW89_TX_QSEL_B1_NOPS = 0x1b,
685 RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c,
686 /* reserved */
687 /* reserved */
688 /* reserved */
689 };
690
rtw89_core_get_qsel(struct rtw89_dev * rtwdev,u8 tid)691 static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid)
692 {
693 switch (tid) {
694 default:
695 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid);
696 fallthrough;
697 case 0:
698 case 3:
699 return RTW89_TX_QSEL_BE_0;
700 case 1:
701 case 2:
702 return RTW89_TX_QSEL_BK_0;
703 case 4:
704 case 5:
705 return RTW89_TX_QSEL_VI_0;
706 case 6:
707 case 7:
708 return RTW89_TX_QSEL_VO_0;
709 }
710 }
711
rtw89_core_get_ch_dma(struct rtw89_dev * rtwdev,u8 qsel)712 static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)
713 {
714 switch (qsel) {
715 default:
716 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel);
717 fallthrough;
718 case RTW89_TX_QSEL_BE_0:
719 return RTW89_TXCH_ACH0;
720 case RTW89_TX_QSEL_BK_0:
721 return RTW89_TXCH_ACH1;
722 case RTW89_TX_QSEL_VI_0:
723 return RTW89_TXCH_ACH2;
724 case RTW89_TX_QSEL_VO_0:
725 return RTW89_TXCH_ACH3;
726 case RTW89_TX_QSEL_B0_MGMT:
727 return RTW89_TXCH_CH8;
728 case RTW89_TX_QSEL_B0_HI:
729 return RTW89_TXCH_CH9;
730 case RTW89_TX_QSEL_B1_MGMT:
731 return RTW89_TXCH_CH10;
732 case RTW89_TX_QSEL_B1_HI:
733 return RTW89_TXCH_CH11;
734 }
735 }
736
rtw89_core_get_tid_indicate(struct rtw89_dev * rtwdev,u8 tid)737 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid)
738 {
739 switch (tid) {
740 case 3:
741 case 2:
742 case 5:
743 case 7:
744 return 1;
745 default:
746 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid);
747 fallthrough;
748 case 0:
749 case 1:
750 case 4:
751 case 6:
752 return 0;
753 }
754 }
755
756 #endif
757