Searched refs:BASEADDR_V7M_SCB (Results 1 – 13 of 13) sorted by relevance
| /linux-6.12.1/arch/arm/mm/ |
| D | pmsa-v7.c | 105 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RNR); in rgnr_write()
113 u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(15, 0); in dracr_write()
115 writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + PMSAv7_RASR); in dracr_write()
121 u32 racr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(31, 16); in drsr_write()
123 writel_relaxed(v | racr, BASEADDR_V7M_SCB + PMSAv7_RASR); in drsr_write()
129 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RBAR); in drbar_write()
134 return readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RBAR); in drbar_read()
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| D | pmsa-v8.c | 53 return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RLAR); in prlar_read()
58 return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RBAR); in prbar_read()
63 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR); in prsel_write()
68 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR); in prbar_write()
73 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR); in prlar_write()
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| D | proc-v7m.S | 77 movw r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
78 movt r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
89 movw r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
90 movt r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
112 ldr r0, =BASEADDR_V7M_SCB
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| D | proc-macros.S | 76 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
77 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
94 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
95 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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| D | cache-v7m.S | 26 movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg
27 movt \rt, #:upper16:BASEADDR_V7M_SCB + \reg
32 movw\c \tmp, #:lower16:BASEADDR_V7M_SCB + \op
33 movt\c \tmp, #:upper16:BASEADDR_V7M_SCB + \op
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| /linux-6.12.1/arch/arm/include/asm/ |
| D | cputype.h | 159 return readl(BASEADDR_V7M_SCB + offset); in read_cpuid_ext()
203 return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); in read_cpuid_id()
208 return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR); in read_cpuid_cachetype()
213 return readl(BASEADDR_V7M_SCB + MPU_TYPE); in read_cpuid_mputype()
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| D | cachetype.h | 92 writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR); in set_csselr()
97 return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); in read_ccsidr()
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| D | v7m.h | 8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00) macro
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| /linux-6.12.1/arch/arm/kernel/ |
| D | v7m.c | 14 BASEADDR_V7M_SCB + V7M_SCB_AIRCR); in armv7m_restart()
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| D | head-nommu.S | 60 ldr r9, =BASEADDR_V7M_SCB
133 M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
134 M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
256 M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
257 M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
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| D | entry-v7m.S | 64 ldr r1, =BASEADDR_V7M_SCB
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-nvic.c | 42 unsigned long icsr = readl_relaxed(BASEADDR_V7M_SCB + V7M_SCB_ICSR); in nvic_handle_irq()
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| /linux-6.12.1/arch/arm/boot/compressed/ |
| D | head.S | 692 movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
693 movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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