| /linux-6.12.1/drivers/net/ethernet/smsc/ |
| D | smc9194.h | 60 #define BANK_SELECT 14 macro
204 #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
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| D | smc91c92_cs.c | 145 #define BANK_SELECT 14 /* Window select register. */ macro
146 #define SMC_SELECT_BANK(x) { outw(x, ioaddr + BANK_SELECT); }
773 if (inw(ioaddr + BANK_SELECT) >> 8 != 0x33) { in check_sig()
790 if ((inw(ioaddr + BANK_SELECT) >> 8 == 0x33) && in check_sig()
1038 save = inw(ioaddr + BANK_SELECT); in smc_dump()
1046 outw(save, ioaddr + BANK_SELECT); in smc_dump()
1056 dev->name, dev, inw(dev->base_addr + BANK_SELECT)); in smc_open()
1091 dev->name, inw(ioaddr + BANK_SELECT)); in smc_close()
1363 saved_bank = inw(ioaddr + BANK_SELECT); in smc_interrupt()
1621 saved_bank = inw(ioaddr + BANK_SELECT); in smc_set_xcvr()
[all …]
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| D | smc9194.c | 869 bank = inw( ioaddr + BANK_SELECT ); in smc_probe()
876 outw( 0x0, ioaddr + BANK_SELECT ); in smc_probe()
877 bank = inw( ioaddr + BANK_SELECT ); in smc_probe()
1329 saved_bank = inw( ioaddr + BANK_SELECT ); in smc_interrupt()
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| D | smc91x.h | 454 #define BANK_SELECT (14 << SMC_IO_SHIFT) macro
897 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
904 SMC_outw(lp, x, ioaddr, BANK_SELECT); \
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 197 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_0_init_cache_regs()
201 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_0_init_cache_regs()
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| D | gfxhub_v2_0.c | 234 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v2_0_init_cache_regs()
238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v2_0_init_cache_regs()
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| D | gfxhub_v3_0_3.c | 240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v3_0_3_init_cache_regs()
244 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v3_0_3_init_cache_regs()
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| D | gfxhub_v3_0.c | 235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v3_0_init_cache_regs()
239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v3_0_init_cache_regs()
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| D | gfxhub_v12_0.c | 243 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v12_0_init_cache_regs()
247 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v12_0_init_cache_regs()
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| D | mmhub_v3_0_2.c | 253 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v3_0_2_init_cache_regs()
257 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v3_0_2_init_cache_regs()
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| D | gfxhub_v11_5_0.c | 238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v11_5_0_init_cache_regs()
242 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v11_5_0_init_cache_regs()
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| D | mmhub_v3_0_1.c | 254 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v3_0_1_init_cache_regs()
258 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v3_0_1_init_cache_regs()
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| D | mmhub_v2_0.c | 305 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v2_0_init_cache_regs()
309 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v2_0_init_cache_regs()
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| D | mmhub_v2_3.c | 229 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v2_3_init_cache_regs()
233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v2_3_init_cache_regs()
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| D | mmhub_v3_3.c | 250 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v3_3_init_cache_regs()
254 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v3_3_init_cache_regs()
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| D | mmhub_v3_0.c | 261 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v3_0_init_cache_regs()
265 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v3_0_init_cache_regs()
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| D | mmhub_v4_1_0.c | 262 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v4_1_0_init_cache_regs()
266 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v4_1_0_init_cache_regs()
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| D | mmhub_v1_8.c | 251 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_8_init_cache_regs()
255 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_8_init_cache_regs()
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| D | gfxhub_v1_2.c | 246 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_2_xcc_init_cache_regs()
250 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_2_xcc_init_cache_regs()
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| D | mmhub_v1_0.c | 183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_0_init_cache_regs()
187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_0_init_cache_regs()
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| D | gfxhub_v2_1.c | 240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v2_1_init_cache_regs()
244 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v2_1_init_cache_regs()
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| D | mmhub_v1_7.c | 201 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_7_init_cache_regs()
205 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_7_init_cache_regs()
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| /linux-6.12.1/drivers/net/ethernet/microchip/ |
| D | encx24j600_hw.h | 22 #define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1)) macro
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| D | encx24j600-regmap.c | 24 int bank_opcode = BANK_SELECT(bank); in encx24j600_switch_bank()
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | rv770.c | 911 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable()
957 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable()
988 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
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