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Searched refs:AST_IO_VGACRI (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/ast/
Dast_mode.c255 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8c, (u8)((color_index & 0x0f) << 4)); in ast_set_vbios_color_reg()
257 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00); in ast_set_vbios_color_reg()
260 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8); in ast_set_vbios_color_reg()
261 ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, format->cpp[0] * 8); in ast_set_vbios_color_reg()
274 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8d, refresh_rate_index & 0xff); in ast_set_vbios_mode_reg()
275 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8e, mode_id & 0xff); in ast_set_vbios_mode_reg()
277 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00); in ast_set_vbios_mode_reg()
280 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8); in ast_set_vbios_mode_reg()
281 ast_set_index_reg(ast, AST_IO_VGACRI, 0x93, adjusted_mode->clock / 1000); in ast_set_vbios_mode_reg()
282 ast_set_index_reg(ast, AST_IO_VGACRI, 0x94, adjusted_mode->crtc_hdisplay); in ast_set_vbios_mode_reg()
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Dast_dp.c18 if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, AST_IO_VGACRDF_HPD)) in ast_astdp_is_connected()
40 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xe5, (u8)~AST_IO_VGACRE5_EDID_READ_DONE, 0x00); in ast_astdp_read_edid_block()
58 ast_set_index_reg(ast, AST_IO_VGACRI, 0xe4, vgacre4); in ast_astdp_read_edid_block()
79 vgacrd7 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd7); in ast_astdp_read_edid_block()
81 vgacrd6 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd6); in ast_astdp_read_edid_block()
91 ediddata[0] = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd8); in ast_astdp_read_edid_block()
92 ediddata[1] = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd9); in ast_astdp_read_edid_block()
93 ediddata[2] = ast_get_index_reg(ast, AST_IO_VGACRI, 0xda); in ast_astdp_read_edid_block()
94 ediddata[3] = ast_get_index_reg(ast, AST_IO_VGACRI, 0xdb); in ast_astdp_read_edid_block()
116 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xe5, (u8)~AST_IO_VGACRE5_EDID_READ_DONE, in ast_astdp_read_edid_block()
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Dast_ddc.c49 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0xf1, ujcrb7); in ast_ddc_algo_bit_data_setsda()
50 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x04); in ast_ddc_algo_bit_data_setsda()
65 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0xf4, ujcrb7); in ast_ddc_algo_bit_data_setscl()
66 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x01); in ast_ddc_algo_bit_data_setscl()
102 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; in ast_ddc_algo_bit_data_getsda()
104 val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; in ast_ddc_algo_bit_data_getsda()
109 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; in ast_ddc_algo_bit_data_getsda()
124 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; in ast_ddc_algo_bit_data_getscl()
126 val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; in ast_ddc_algo_bit_data_getscl()
131 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; in ast_ddc_algo_bit_data_getscl()
Dast_dp501.c39 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); in send_ack()
41 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack); in send_ack()
47 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); in send_nack()
49 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack); in send_nack()
57 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); in wait_ack()
73 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); in wait_nack()
86 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x40); in set_cmd_trigger()
91 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x00); in clear_cmd_trigger()
100 waitready = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff);
118 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, data); in ast_write_cmd()
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Dast_main.c49 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_detect_widescreen()
86 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); in ast_detect_tx_chip()
97 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff); in ast_detect_tx_chip()
116 if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, TX_TYPE_MASK) == in ast_detect_tx_chip()
Dast_drv.c115 __ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, AST_IO_VGACRA1_MMIO_ENABLED); in ast_enable_mmio_release()
122 __ast_write8_i(ioregs, AST_IO_VGACRI, 0xa1, in ast_enable_mmio()
131 __ast_write8_i(ioregs, AST_IO_VGACRI, 0x80, AST_IO_VGACR80_PASSWORD); in ast_open_key()
162 vgacrd0 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd0); in ast_detect_chip()
163 vgacrd1 = __ast_read8_i(ioregs, AST_IO_VGACRI, 0xd1); in ast_detect_chip()
Dast_mm.c42 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xaa, 0xff); in ast_get_vram_size()
58 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x99, 0xff); in ast_get_vram_size()
Dast_post.c52 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00); in ast_set_def_ext_reg()
61 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
70 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
71 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
77 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg); in ast_set_def_ext_reg()
262 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dram_reg()
342 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dram_reg()
366 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); /* Enable DVO */ in ast_post_gpu()
1579 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2300()
1651 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2300()
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Dast_reg.h31 #define AST_IO_VGACRI (0x54) macro