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Searched refs:AMDGPU_GPU_PAGE_ALIGN (Results 1 – 15 of 15) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vcn.c186 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_vcn_sw_init()
189 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)); in amdgpu_vcn_sw_init()
192 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); in amdgpu_vcn_sw_init()
195 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); in amdgpu_vcn_sw_init()
547 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_dec_send_msg()
606 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); in amdgpu_vcn_dec_get_create_msg()
641 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); in amdgpu_vcn_dec_get_destroy_msg()
726 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_dec_sw_send_msg()
871 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_enc_get_create_msg()
938 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_enc_get_destroy_msg()
Damdgpu_gart.h38 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) macro
Damdgpu_uvd.h37 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
Dvcn_v4_0_3.c383 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_3_mc_resume()
440 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_3_mc_resume()
458 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_3_mc_resume_dpg_mode()
548 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
944 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4); in vcn_v4_0_3_start_sriov()
1021 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_3_start_sriov()
Dvcn_v4_0.c428 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_mc_resume()
471 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_mc_resume()
488 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_mc_resume_dpg_mode()
574 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1337 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4); in vcn_v4_0_start_sriov()
1436 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_start_sriov()
Dvcn_v5_0_0.c340 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_0_mc_resume()
383 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); in vcn_v5_0_0_mc_resume()
401 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v5_0_0_mc_resume_dpg_mode()
487 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
Dvcn_v4_0_5.c376 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_5_mc_resume()
419 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_5_mc_resume()
437 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_5_mc_resume_dpg_mode()
528 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
Dvcn_v2_0.c377 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4); in vcn_v2_0_mc_resume()
426 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_0_mc_resume()
433 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4); in vcn_v2_0_mc_resume_dpg_mode()
520 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1925 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4); in vcn_v2_0_start_sriov()
Dvcn_v2_5.c470 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4); in vcn_v2_5_mc_resume()
513 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_5_mc_resume()
519 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4); in vcn_v2_5_mc_resume_dpg_mode()
606 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1290 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4); in vcn_v2_5_sriov_start()
Dvcn_v3_0.c495 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst]->size + 4); in vcn_v3_0_mc_resume()
540 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v3_0_mc_resume()
545 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4); in vcn_v3_0_mc_resume_dpg_mode()
632 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1378 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4); in vcn_v3_0_start_sriov()
Damdgpu_vm_pt.c124 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_pt_num_entries(adev, level) * 8); in amdgpu_vm_pt_size()
Damdgpu_vce.c466 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr); in amdgpu_vce_get_create_msg()
Dvcn_v1_0.c348 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4); in vcn_v1_0_mc_resume_spg_mode()
415 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4); in vcn_v1_0_mc_resume_dpg_mode()
Damdgpu_uvd.c320 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_uvd_sw_init()
Duvd_v7_0.c821 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); in uvd_v7_0_sriov_start()