Searched refs:ALCHEMY_GPIO2_BASE (Results 1 – 2 of 2) sorted by relevance
18 #define ALCHEMY_GPIO2_BASE 200 macro23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)78 gpio -= ALCHEMY_GPIO2_BASE; in au1500_gpio2_to_irq()97 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0; in au1500_irq_to_gpio()99 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4; in au1500_irq_to_gpio()101 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6; in au1500_irq_to_gpio()103 return ALCHEMY_GPIO2_BASE + 8; in au1500_irq_to_gpio()116 gpio -= ALCHEMY_GPIO2_BASE; in au1100_gpio2_to_irq()130 return ALCHEMY_GPIO2_BASE + 8; in au1100_irq_to_gpio()151 gpio -= ALCHEMY_GPIO2_BASE; in au1550_gpio2_to_irq()[all …]
40 return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); in gpio2_get()45 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); in gpio2_set()50 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE); in gpio2_direction_input()56 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE, in gpio2_direction_output()62 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); in gpio2_to_irq()112 .base = ALCHEMY_GPIO2_BASE,