Searched refs:AK4375_12_PLL_FB_CLK_DIVIDER2 (Results 1 – 1 of 1) sorted by relevance
68 #define AK4375_12_PLL_FB_CLK_DIVIDER2 0x12 /* Feedback clock divider [7:0] bits */ macro352 snd_soc_component_write(component, AK4375_12_PLL_FB_CLK_DIVIDER2, plm & 0x00ff); in ak4375_dai_set_pll()