1 // SPDX-License-Identifier: GPL-2.0
2 / {
3 	compatible = "cdns,xtensa-xtfpga";
4 	#address-cells = <1>;
5 	#size-cells = <1>;
6 	interrupt-parent = <&pic>;
7 
8 	chosen {
9 		bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
10 	};
11 
12 	memory@0 {
13 		device_type = "memory";
14 		reg = <0x00000000 0x06000000>;
15 	};
16 
17 	cpus {
18 		#address-cells = <1>;
19 		#size-cells = <0>;
20 		cpu@0 {
21 			compatible = "cdns,xtensa-cpu";
22 			reg = <0>;
23 			clocks = <&osc>;
24 		};
25 	};
26 
27 	pic: pic {
28 		compatible = "cdns,xtensa-pic";
29 		/* one cell: internal irq number,
30 		 * two cells: second cell == 0: internal irq number
31 		 *            second cell == 1: external irq number
32 		 */
33 		#interrupt-cells = <2>;
34 		interrupt-controller;
35 	};
36 
37 	clocks {
38 		clk54: clk54 {
39 			#clock-cells = <0>;
40 			compatible = "fixed-clock";
41 			clock-frequency = <54000000>;
42 		};
43 	};
44 
45 	soc {
46 		#address-cells = <1>;
47 		#size-cells = <1>;
48 		compatible = "simple-bus";
49 		ranges = <0x00000000 0xf0000000 0x10000000>;
50 
51 		osc: main-oscillator {
52 			#clock-cells = <0>;
53 			compatible = "cdns,xtfpga-clock";
54 			reg = <0x0d020004 0x4>;
55 		};
56 
57 		serial0: serial@0d050020 {
58 			device_type = "serial";
59 			compatible = "ns16550a";
60 			no-loopback-test;
61 			reg = <0x0d050020 0x20>;
62 			reg-shift = <2>;
63 			reg-io-width = <4>;
64 			native-endian;
65 			interrupts = <0 1>; /* external irq 0 */
66 			clocks = <&osc>;
67 		};
68 
69 		enet0: ethoc@0d030000 {
70 			compatible = "opencores,ethoc";
71 			reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
72 			native-endian;
73 			interrupts = <1 1>; /* external irq 1 */
74 			local-mac-address = [00 50 c2 13 6f 00];
75 			clocks = <&osc>;
76 		};
77 
78 		i2s0: xtfpga-i2s@0d080000 {
79 			#sound-dai-cells = <0>;
80 			compatible = "cdns,xtfpga-i2s";
81 			reg = <0x0d080000 0x40>;
82 			interrupts = <2 1>; /* external irq 2 */
83 			clocks = <&cdce706 4>;
84 		};
85 
86 		i2c0: i2c-master@0d090000 {
87 			compatible = "opencores,i2c-ocores";
88 			#address-cells = <1>;
89 			#size-cells = <0>;
90 			reg = <0x0d090000 0x20>;
91 			reg-shift = <2>;
92 			reg-io-width = <4>;
93 			native-endian;
94 			interrupts = <4 1>;
95 			clocks = <&osc>;
96 
97 			cdce706: clock-synth@69 {
98 				compatible = "ti,cdce706";
99 				#clock-cells = <1>;
100 				reg = <0x69>;
101 				clocks = <&clk54>;
102 				clock-names = "clk_in0";
103 			};
104 		};
105 
106 		spi0: spi@0d0a0000 {
107 			compatible = "cdns,xtfpga-spi";
108 			#address-cells = <1>;
109 			#size-cells = <0>;
110 			reg = <0x0d0a0000 0xc>;
111 
112 			tlv320aic23: sound-codec@0 {
113 				#sound-dai-cells = <0>;
114 				compatible = "tlv320aic23";
115 				reg = <0>;
116 				spi-max-frequency = <12500000>;
117 			};
118 		};
119 	};
120 
121 	sound {
122 		compatible = "simple-audio-card";
123 		simple-audio-card,format = "i2s";
124 		simple-audio-card,mclk-fs = <256>;
125 
126 		simple-audio-card,cpu {
127 			sound-dai = <&i2s0>;
128 		};
129 
130 		simple-audio-card,codec {
131 			sound-dai = <&tlv320aic23>;
132 			simple-audio-card,bitclock-master = <0>;
133 			simple-audio-card,frame-master = <0>;
134 			clocks = <&cdce706 4>;
135 		};
136 	};
137 };
138