1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef _XE_BO_TYPES_H_
7 #define _XE_BO_TYPES_H_
8 
9 #include <linux/iosys-map.h>
10 
11 #include <drm/ttm/ttm_bo.h>
12 #include <drm/ttm/ttm_device.h>
13 #include <drm/ttm/ttm_execbuf_util.h>
14 #include <drm/ttm/ttm_placement.h>
15 
16 #include "xe_ggtt_types.h"
17 
18 struct xe_device;
19 struct xe_vm;
20 
21 #define XE_BO_MAX_PLACEMENTS	3
22 
23 /* TODO: To be selected with VM_MADVISE */
24 #define	XE_BO_PRIORITY_NORMAL	1
25 
26 /** @xe_bo: XE buffer object */
27 struct xe_bo {
28 	/** @ttm: TTM base buffer object */
29 	struct ttm_buffer_object ttm;
30 	/** @size: Size of this buffer object */
31 	size_t size;
32 	/** @flags: flags for this buffer object */
33 	u32 flags;
34 	/** @vm: VM this BO is attached to, for extobj this will be NULL */
35 	struct xe_vm *vm;
36 	/** @tile: Tile this BO is attached to (kernel BO only) */
37 	struct xe_tile *tile;
38 	/** @placements: valid placements for this BO */
39 	struct ttm_place placements[XE_BO_MAX_PLACEMENTS];
40 	/** @placement: current placement for this BO */
41 	struct ttm_placement placement;
42 	/** @ggtt_node: GGTT node if this BO is mapped in the GGTT */
43 	struct xe_ggtt_node *ggtt_node;
44 	/** @vmap: iosys map of this buffer */
45 	struct iosys_map vmap;
46 	/** @ttm_kmap: TTM bo kmap object for internal use only. Keep off. */
47 	struct ttm_bo_kmap_obj kmap;
48 	/** @pinned_link: link to present / evicted list of pinned BO */
49 	struct list_head pinned_link;
50 #ifdef CONFIG_PROC_FS
51 	/**
52 	 * @client: @xe_drm_client which created the bo
53 	 */
54 	struct xe_drm_client *client;
55 	/**
56 	 * @client_link: Link into @xe_drm_client.objects_list
57 	 */
58 	struct list_head client_link;
59 #endif
60 	/** @freed: List node for delayed put. */
61 	struct llist_node freed;
62 	/** @update_index: Update index if PT BO */
63 	int update_index;
64 	/** @created: Whether the bo has passed initial creation */
65 	bool created;
66 
67 	/** @ccs_cleared */
68 	bool ccs_cleared;
69 
70 	/**
71 	 * @cpu_caching: CPU caching mode. Currently only used for userspace
72 	 * objects. Exceptions are system memory on DGFX, which is always
73 	 * WB.
74 	 */
75 	u16 cpu_caching;
76 
77 	/** @vram_userfault_link: Link into @mem_access.vram_userfault.list */
78 		struct list_head vram_userfault_link;
79 };
80 
81 #define intel_bo_to_drm_bo(bo) (&(bo)->ttm.base)
82 #define intel_bo_to_i915(bo) to_i915(intel_bo_to_drm_bo(bo)->dev)
83 
84 #endif
85