1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _vcn_5_0_0_SH_MASK_HEADER 24 #define _vcn_5_0_0_SH_MASK_HEADER 25 26 27 // addressBlock: uvd_uvddec 28 //UVD_TOP_CTRL 29 #define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 30 #define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 31 #define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 32 #define UVD_TOP_CTRL__STD_VERSION_MASK 0x00000010L 33 //UVD_CGC_GATE 34 #define UVD_CGC_GATE__SYS__SHIFT 0x0 35 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 36 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 37 #define UVD_CGC_GATE__REGS__SHIFT 0x3 38 #define UVD_CGC_GATE__RBC__SHIFT 0x4 39 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 40 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 41 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 42 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 43 #define UVD_CGC_GATE__MPC__SHIFT 0x9 44 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 45 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 46 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 47 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 48 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 49 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 50 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 51 #define UVD_CGC_GATE__WCB__SHIFT 0x11 52 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 53 #define UVD_CGC_GATE__MMSCH__SHIFT 0x14 54 #define UVD_CGC_GATE__LCM0__SHIFT 0x15 55 #define UVD_CGC_GATE__LCM1__SHIFT 0x16 56 #define UVD_CGC_GATE__MIF__SHIFT 0x17 57 #define UVD_CGC_GATE__VREG__SHIFT 0x18 58 #define UVD_CGC_GATE__PE__SHIFT 0x19 59 #define UVD_CGC_GATE__PPU__SHIFT 0x1a 60 #define UVD_CGC_GATE__SYS_MASK 0x00000001L 61 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 62 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 63 #define UVD_CGC_GATE__REGS_MASK 0x00000008L 64 #define UVD_CGC_GATE__RBC_MASK 0x00000010L 65 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 66 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 67 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 68 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 69 #define UVD_CGC_GATE__MPC_MASK 0x00000200L 70 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 71 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 72 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 73 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 74 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 75 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 76 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 77 #define UVD_CGC_GATE__WCB_MASK 0x00020000L 78 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 79 #define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 80 #define UVD_CGC_GATE__LCM0_MASK 0x00200000L 81 #define UVD_CGC_GATE__LCM1_MASK 0x00400000L 82 #define UVD_CGC_GATE__MIF_MASK 0x00800000L 83 #define UVD_CGC_GATE__VREG_MASK 0x01000000L 84 #define UVD_CGC_GATE__PE_MASK 0x02000000L 85 #define UVD_CGC_GATE__PPU_MASK 0x04000000L 86 //UVD_CGC_CTRL 87 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 88 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 89 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 90 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 91 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 92 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 93 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 94 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 95 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 96 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 97 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 98 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 99 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 100 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 101 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 102 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 103 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 104 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 105 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 106 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 107 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 108 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 109 #define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 110 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 111 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 112 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 113 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 114 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 115 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 116 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 117 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 118 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 119 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 120 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 121 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 122 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 123 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 124 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 125 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 126 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 127 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 128 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 129 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 130 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 131 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 132 #define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 133 //AVM_SUVD_CGC_GATE 134 #define AVM_SUVD_CGC_GATE__SRE__SHIFT 0x0 135 #define AVM_SUVD_CGC_GATE__SIT__SHIFT 0x1 136 #define AVM_SUVD_CGC_GATE__SMP__SHIFT 0x2 137 #define AVM_SUVD_CGC_GATE__SCM__SHIFT 0x3 138 #define AVM_SUVD_CGC_GATE__SDB__SHIFT 0x4 139 #define AVM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 140 #define AVM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 141 #define AVM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 142 #define AVM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 143 #define AVM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 144 #define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 145 #define AVM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 146 #define AVM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 147 #define AVM_SUVD_CGC_GATE__SCLR__SHIFT 0xd 148 #define AVM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 149 #define AVM_SUVD_CGC_GATE__ENT__SHIFT 0xf 150 #define AVM_SUVD_CGC_GATE__IME__SHIFT 0x10 151 #define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 152 #define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 153 #define AVM_SUVD_CGC_GATE__SITE__SHIFT 0x13 154 #define AVM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 155 #define AVM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 156 #define AVM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 157 #define AVM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 158 #define AVM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 159 #define AVM_SUVD_CGC_GATE__EFC__SHIFT 0x19 160 #define AVM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 161 #define AVM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 162 #define AVM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 163 #define AVM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 164 #define AVM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 165 #define AVM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 166 #define AVM_SUVD_CGC_GATE__SRE_MASK 0x00000001L 167 #define AVM_SUVD_CGC_GATE__SIT_MASK 0x00000002L 168 #define AVM_SUVD_CGC_GATE__SMP_MASK 0x00000004L 169 #define AVM_SUVD_CGC_GATE__SCM_MASK 0x00000008L 170 #define AVM_SUVD_CGC_GATE__SDB_MASK 0x00000010L 171 #define AVM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 172 #define AVM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 173 #define AVM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 174 #define AVM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 175 #define AVM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 176 #define AVM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 177 #define AVM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 178 #define AVM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 179 #define AVM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 180 #define AVM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 181 #define AVM_SUVD_CGC_GATE__ENT_MASK 0x00008000L 182 #define AVM_SUVD_CGC_GATE__IME_MASK 0x00010000L 183 #define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 184 #define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 185 #define AVM_SUVD_CGC_GATE__SITE_MASK 0x00080000L 186 #define AVM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 187 #define AVM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 188 #define AVM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 189 #define AVM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 190 #define AVM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 191 #define AVM_SUVD_CGC_GATE__EFC_MASK 0x02000000L 192 #define AVM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 193 #define AVM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 194 #define AVM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 195 #define AVM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 196 #define AVM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 197 #define AVM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 198 //EFC_SUVD_CGC_GATE 199 #define EFC_SUVD_CGC_GATE__SRE__SHIFT 0x0 200 #define EFC_SUVD_CGC_GATE__SIT__SHIFT 0x1 201 #define EFC_SUVD_CGC_GATE__SMP__SHIFT 0x2 202 #define EFC_SUVD_CGC_GATE__SCM__SHIFT 0x3 203 #define EFC_SUVD_CGC_GATE__SDB__SHIFT 0x4 204 #define EFC_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 205 #define EFC_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 206 #define EFC_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 207 #define EFC_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 208 #define EFC_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 209 #define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 210 #define EFC_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 211 #define EFC_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 212 #define EFC_SUVD_CGC_GATE__SCLR__SHIFT 0xd 213 #define EFC_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 214 #define EFC_SUVD_CGC_GATE__ENT__SHIFT 0xf 215 #define EFC_SUVD_CGC_GATE__IME__SHIFT 0x10 216 #define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 217 #define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 218 #define EFC_SUVD_CGC_GATE__SITE__SHIFT 0x13 219 #define EFC_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 220 #define EFC_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 221 #define EFC_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 222 #define EFC_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 223 #define EFC_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 224 #define EFC_SUVD_CGC_GATE__EFC__SHIFT 0x19 225 #define EFC_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 226 #define EFC_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 227 #define EFC_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 228 #define EFC_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 229 #define EFC_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 230 #define EFC_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 231 #define EFC_SUVD_CGC_GATE__SRE_MASK 0x00000001L 232 #define EFC_SUVD_CGC_GATE__SIT_MASK 0x00000002L 233 #define EFC_SUVD_CGC_GATE__SMP_MASK 0x00000004L 234 #define EFC_SUVD_CGC_GATE__SCM_MASK 0x00000008L 235 #define EFC_SUVD_CGC_GATE__SDB_MASK 0x00000010L 236 #define EFC_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 237 #define EFC_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 238 #define EFC_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 239 #define EFC_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 240 #define EFC_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 241 #define EFC_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 242 #define EFC_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 243 #define EFC_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 244 #define EFC_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 245 #define EFC_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 246 #define EFC_SUVD_CGC_GATE__ENT_MASK 0x00008000L 247 #define EFC_SUVD_CGC_GATE__IME_MASK 0x00010000L 248 #define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 249 #define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 250 #define EFC_SUVD_CGC_GATE__SITE_MASK 0x00080000L 251 #define EFC_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 252 #define EFC_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 253 #define EFC_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 254 #define EFC_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 255 #define EFC_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 256 #define EFC_SUVD_CGC_GATE__EFC_MASK 0x02000000L 257 #define EFC_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 258 #define EFC_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 259 #define EFC_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 260 #define EFC_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 261 #define EFC_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 262 #define EFC_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 263 //ENT_SUVD_CGC_GATE 264 #define ENT_SUVD_CGC_GATE__SRE__SHIFT 0x0 265 #define ENT_SUVD_CGC_GATE__SIT__SHIFT 0x1 266 #define ENT_SUVD_CGC_GATE__SMP__SHIFT 0x2 267 #define ENT_SUVD_CGC_GATE__SCM__SHIFT 0x3 268 #define ENT_SUVD_CGC_GATE__SDB__SHIFT 0x4 269 #define ENT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 270 #define ENT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 271 #define ENT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 272 #define ENT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 273 #define ENT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 274 #define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 275 #define ENT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 276 #define ENT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 277 #define ENT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 278 #define ENT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 279 #define ENT_SUVD_CGC_GATE__ENT__SHIFT 0xf 280 #define ENT_SUVD_CGC_GATE__IME__SHIFT 0x10 281 #define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 282 #define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 283 #define ENT_SUVD_CGC_GATE__SITE__SHIFT 0x13 284 #define ENT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 285 #define ENT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 286 #define ENT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 287 #define ENT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 288 #define ENT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 289 #define ENT_SUVD_CGC_GATE__EFC__SHIFT 0x19 290 #define ENT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 291 #define ENT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 292 #define ENT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 293 #define ENT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 294 #define ENT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 295 #define ENT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 296 #define ENT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 297 #define ENT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 298 #define ENT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 299 #define ENT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 300 #define ENT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 301 #define ENT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 302 #define ENT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 303 #define ENT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 304 #define ENT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 305 #define ENT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 306 #define ENT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 307 #define ENT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 308 #define ENT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 309 #define ENT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 310 #define ENT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 311 #define ENT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 312 #define ENT_SUVD_CGC_GATE__IME_MASK 0x00010000L 313 #define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 314 #define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 315 #define ENT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 316 #define ENT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 317 #define ENT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 318 #define ENT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 319 #define ENT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 320 #define ENT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 321 #define ENT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 322 #define ENT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 323 #define ENT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 324 #define ENT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 325 #define ENT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 326 #define ENT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 327 #define ENT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 328 //IME_SUVD_CGC_GATE 329 #define IME_SUVD_CGC_GATE__SRE__SHIFT 0x0 330 #define IME_SUVD_CGC_GATE__SIT__SHIFT 0x1 331 #define IME_SUVD_CGC_GATE__SMP__SHIFT 0x2 332 #define IME_SUVD_CGC_GATE__SCM__SHIFT 0x3 333 #define IME_SUVD_CGC_GATE__SDB__SHIFT 0x4 334 #define IME_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 335 #define IME_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 336 #define IME_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 337 #define IME_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 338 #define IME_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 339 #define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 340 #define IME_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 341 #define IME_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 342 #define IME_SUVD_CGC_GATE__SCLR__SHIFT 0xd 343 #define IME_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 344 #define IME_SUVD_CGC_GATE__ENT__SHIFT 0xf 345 #define IME_SUVD_CGC_GATE__IME__SHIFT 0x10 346 #define IME_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 347 #define IME_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 348 #define IME_SUVD_CGC_GATE__SITE__SHIFT 0x13 349 #define IME_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 350 #define IME_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 351 #define IME_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 352 #define IME_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 353 #define IME_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 354 #define IME_SUVD_CGC_GATE__EFC__SHIFT 0x19 355 #define IME_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 356 #define IME_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 357 #define IME_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 358 #define IME_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 359 #define IME_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 360 #define IME_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 361 #define IME_SUVD_CGC_GATE__SRE_MASK 0x00000001L 362 #define IME_SUVD_CGC_GATE__SIT_MASK 0x00000002L 363 #define IME_SUVD_CGC_GATE__SMP_MASK 0x00000004L 364 #define IME_SUVD_CGC_GATE__SCM_MASK 0x00000008L 365 #define IME_SUVD_CGC_GATE__SDB_MASK 0x00000010L 366 #define IME_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 367 #define IME_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 368 #define IME_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 369 #define IME_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 370 #define IME_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 371 #define IME_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 372 #define IME_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 373 #define IME_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 374 #define IME_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 375 #define IME_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 376 #define IME_SUVD_CGC_GATE__ENT_MASK 0x00008000L 377 #define IME_SUVD_CGC_GATE__IME_MASK 0x00010000L 378 #define IME_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 379 #define IME_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 380 #define IME_SUVD_CGC_GATE__SITE_MASK 0x00080000L 381 #define IME_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 382 #define IME_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 383 #define IME_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 384 #define IME_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 385 #define IME_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 386 #define IME_SUVD_CGC_GATE__EFC_MASK 0x02000000L 387 #define IME_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 388 #define IME_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 389 #define IME_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 390 #define IME_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 391 #define IME_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 392 #define IME_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 393 //PPU_SUVD_CGC_GATE 394 #define PPU_SUVD_CGC_GATE__SRE__SHIFT 0x0 395 #define PPU_SUVD_CGC_GATE__SIT__SHIFT 0x1 396 #define PPU_SUVD_CGC_GATE__SMP__SHIFT 0x2 397 #define PPU_SUVD_CGC_GATE__SCM__SHIFT 0x3 398 #define PPU_SUVD_CGC_GATE__SDB__SHIFT 0x4 399 #define PPU_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 400 #define PPU_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 401 #define PPU_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 402 #define PPU_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 403 #define PPU_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 404 #define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 405 #define PPU_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 406 #define PPU_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 407 #define PPU_SUVD_CGC_GATE__SCLR__SHIFT 0xd 408 #define PPU_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 409 #define PPU_SUVD_CGC_GATE__ENT__SHIFT 0xf 410 #define PPU_SUVD_CGC_GATE__IME__SHIFT 0x10 411 #define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 412 #define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 413 #define PPU_SUVD_CGC_GATE__SITE__SHIFT 0x13 414 #define PPU_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 415 #define PPU_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 416 #define PPU_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 417 #define PPU_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 418 #define PPU_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 419 #define PPU_SUVD_CGC_GATE__EFC__SHIFT 0x19 420 #define PPU_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 421 #define PPU_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 422 #define PPU_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 423 #define PPU_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 424 #define PPU_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 425 #define PPU_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 426 #define PPU_SUVD_CGC_GATE__SRE_MASK 0x00000001L 427 #define PPU_SUVD_CGC_GATE__SIT_MASK 0x00000002L 428 #define PPU_SUVD_CGC_GATE__SMP_MASK 0x00000004L 429 #define PPU_SUVD_CGC_GATE__SCM_MASK 0x00000008L 430 #define PPU_SUVD_CGC_GATE__SDB_MASK 0x00000010L 431 #define PPU_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 432 #define PPU_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 433 #define PPU_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 434 #define PPU_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 435 #define PPU_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 436 #define PPU_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 437 #define PPU_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 438 #define PPU_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 439 #define PPU_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 440 #define PPU_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 441 #define PPU_SUVD_CGC_GATE__ENT_MASK 0x00008000L 442 #define PPU_SUVD_CGC_GATE__IME_MASK 0x00010000L 443 #define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 444 #define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 445 #define PPU_SUVD_CGC_GATE__SITE_MASK 0x00080000L 446 #define PPU_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 447 #define PPU_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 448 #define PPU_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 449 #define PPU_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 450 #define PPU_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 451 #define PPU_SUVD_CGC_GATE__EFC_MASK 0x02000000L 452 #define PPU_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 453 #define PPU_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 454 #define PPU_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 455 #define PPU_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 456 #define PPU_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 457 #define PPU_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 458 //SAOE_SUVD_CGC_GATE 459 #define SAOE_SUVD_CGC_GATE__SRE__SHIFT 0x0 460 #define SAOE_SUVD_CGC_GATE__SIT__SHIFT 0x1 461 #define SAOE_SUVD_CGC_GATE__SMP__SHIFT 0x2 462 #define SAOE_SUVD_CGC_GATE__SCM__SHIFT 0x3 463 #define SAOE_SUVD_CGC_GATE__SDB__SHIFT 0x4 464 #define SAOE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 465 #define SAOE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 466 #define SAOE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 467 #define SAOE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 468 #define SAOE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 469 #define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 470 #define SAOE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 471 #define SAOE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 472 #define SAOE_SUVD_CGC_GATE__SCLR__SHIFT 0xd 473 #define SAOE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 474 #define SAOE_SUVD_CGC_GATE__ENT__SHIFT 0xf 475 #define SAOE_SUVD_CGC_GATE__IME__SHIFT 0x10 476 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 477 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 478 #define SAOE_SUVD_CGC_GATE__SITE__SHIFT 0x13 479 #define SAOE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 480 #define SAOE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 481 #define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 482 #define SAOE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 483 #define SAOE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 484 #define SAOE_SUVD_CGC_GATE__EFC__SHIFT 0x19 485 #define SAOE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 486 #define SAOE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 487 #define SAOE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 488 #define SAOE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 489 #define SAOE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 490 #define SAOE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 491 #define SAOE_SUVD_CGC_GATE__SRE_MASK 0x00000001L 492 #define SAOE_SUVD_CGC_GATE__SIT_MASK 0x00000002L 493 #define SAOE_SUVD_CGC_GATE__SMP_MASK 0x00000004L 494 #define SAOE_SUVD_CGC_GATE__SCM_MASK 0x00000008L 495 #define SAOE_SUVD_CGC_GATE__SDB_MASK 0x00000010L 496 #define SAOE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 497 #define SAOE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 498 #define SAOE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 499 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 500 #define SAOE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 501 #define SAOE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 502 #define SAOE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 503 #define SAOE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 504 #define SAOE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 505 #define SAOE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 506 #define SAOE_SUVD_CGC_GATE__ENT_MASK 0x00008000L 507 #define SAOE_SUVD_CGC_GATE__IME_MASK 0x00010000L 508 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 509 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 510 #define SAOE_SUVD_CGC_GATE__SITE_MASK 0x00080000L 511 #define SAOE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 512 #define SAOE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 513 #define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 514 #define SAOE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 515 #define SAOE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 516 #define SAOE_SUVD_CGC_GATE__EFC_MASK 0x02000000L 517 #define SAOE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 518 #define SAOE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 519 #define SAOE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 520 #define SAOE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 521 #define SAOE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 522 #define SAOE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 523 //SCM_SUVD_CGC_GATE 524 #define SCM_SUVD_CGC_GATE__SRE__SHIFT 0x0 525 #define SCM_SUVD_CGC_GATE__SIT__SHIFT 0x1 526 #define SCM_SUVD_CGC_GATE__SMP__SHIFT 0x2 527 #define SCM_SUVD_CGC_GATE__SCM__SHIFT 0x3 528 #define SCM_SUVD_CGC_GATE__SDB__SHIFT 0x4 529 #define SCM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 530 #define SCM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 531 #define SCM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 532 #define SCM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 533 #define SCM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 534 #define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 535 #define SCM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 536 #define SCM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 537 #define SCM_SUVD_CGC_GATE__SCLR__SHIFT 0xd 538 #define SCM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 539 #define SCM_SUVD_CGC_GATE__ENT__SHIFT 0xf 540 #define SCM_SUVD_CGC_GATE__IME__SHIFT 0x10 541 #define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 542 #define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 543 #define SCM_SUVD_CGC_GATE__SITE__SHIFT 0x13 544 #define SCM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 545 #define SCM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 546 #define SCM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 547 #define SCM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 548 #define SCM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 549 #define SCM_SUVD_CGC_GATE__EFC__SHIFT 0x19 550 #define SCM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 551 #define SCM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 552 #define SCM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 553 #define SCM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 554 #define SCM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 555 #define SCM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 556 #define SCM_SUVD_CGC_GATE__SRE_MASK 0x00000001L 557 #define SCM_SUVD_CGC_GATE__SIT_MASK 0x00000002L 558 #define SCM_SUVD_CGC_GATE__SMP_MASK 0x00000004L 559 #define SCM_SUVD_CGC_GATE__SCM_MASK 0x00000008L 560 #define SCM_SUVD_CGC_GATE__SDB_MASK 0x00000010L 561 #define SCM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 562 #define SCM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 563 #define SCM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 564 #define SCM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 565 #define SCM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 566 #define SCM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 567 #define SCM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 568 #define SCM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 569 #define SCM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 570 #define SCM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 571 #define SCM_SUVD_CGC_GATE__ENT_MASK 0x00008000L 572 #define SCM_SUVD_CGC_GATE__IME_MASK 0x00010000L 573 #define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 574 #define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 575 #define SCM_SUVD_CGC_GATE__SITE_MASK 0x00080000L 576 #define SCM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 577 #define SCM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 578 #define SCM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 579 #define SCM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 580 #define SCM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 581 #define SCM_SUVD_CGC_GATE__EFC_MASK 0x02000000L 582 #define SCM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 583 #define SCM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 584 #define SCM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 585 #define SCM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 586 #define SCM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 587 #define SCM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 588 //SDB_SUVD_CGC_GATE 589 #define SDB_SUVD_CGC_GATE__SRE__SHIFT 0x0 590 #define SDB_SUVD_CGC_GATE__SIT__SHIFT 0x1 591 #define SDB_SUVD_CGC_GATE__SMP__SHIFT 0x2 592 #define SDB_SUVD_CGC_GATE__SCM__SHIFT 0x3 593 #define SDB_SUVD_CGC_GATE__SDB__SHIFT 0x4 594 #define SDB_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 595 #define SDB_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 596 #define SDB_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 597 #define SDB_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 598 #define SDB_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 599 #define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 600 #define SDB_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 601 #define SDB_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 602 #define SDB_SUVD_CGC_GATE__SCLR__SHIFT 0xd 603 #define SDB_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 604 #define SDB_SUVD_CGC_GATE__ENT__SHIFT 0xf 605 #define SDB_SUVD_CGC_GATE__IME__SHIFT 0x10 606 #define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 607 #define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 608 #define SDB_SUVD_CGC_GATE__SITE__SHIFT 0x13 609 #define SDB_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 610 #define SDB_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 611 #define SDB_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 612 #define SDB_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 613 #define SDB_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 614 #define SDB_SUVD_CGC_GATE__EFC__SHIFT 0x19 615 #define SDB_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 616 #define SDB_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 617 #define SDB_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 618 #define SDB_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 619 #define SDB_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 620 #define SDB_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 621 #define SDB_SUVD_CGC_GATE__SRE_MASK 0x00000001L 622 #define SDB_SUVD_CGC_GATE__SIT_MASK 0x00000002L 623 #define SDB_SUVD_CGC_GATE__SMP_MASK 0x00000004L 624 #define SDB_SUVD_CGC_GATE__SCM_MASK 0x00000008L 625 #define SDB_SUVD_CGC_GATE__SDB_MASK 0x00000010L 626 #define SDB_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 627 #define SDB_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 628 #define SDB_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 629 #define SDB_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 630 #define SDB_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 631 #define SDB_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 632 #define SDB_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 633 #define SDB_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 634 #define SDB_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 635 #define SDB_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 636 #define SDB_SUVD_CGC_GATE__ENT_MASK 0x00008000L 637 #define SDB_SUVD_CGC_GATE__IME_MASK 0x00010000L 638 #define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 639 #define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 640 #define SDB_SUVD_CGC_GATE__SITE_MASK 0x00080000L 641 #define SDB_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 642 #define SDB_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 643 #define SDB_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 644 #define SDB_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 645 #define SDB_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 646 #define SDB_SUVD_CGC_GATE__EFC_MASK 0x02000000L 647 #define SDB_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 648 #define SDB_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 649 #define SDB_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 650 #define SDB_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 651 #define SDB_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 652 #define SDB_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 653 //SIT0_NXT_SUVD_CGC_GATE 654 #define SIT0_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 655 #define SIT0_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 656 #define SIT0_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 657 #define SIT0_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 658 #define SIT0_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 659 #define SIT0_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 660 #define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 661 #define SIT0_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 662 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 663 #define SIT0_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 664 #define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 665 #define SIT0_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 666 #define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 667 #define SIT0_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 668 #define SIT0_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 669 #define SIT0_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf 670 #define SIT0_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 671 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 672 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 673 #define SIT0_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 674 #define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 675 #define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 676 #define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 677 #define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 678 #define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 679 #define SIT0_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 680 #define SIT0_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 681 #define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 682 #define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 683 #define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 684 #define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 685 #define SIT0_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 686 #define SIT0_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 687 #define SIT0_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 688 #define SIT0_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 689 #define SIT0_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 690 #define SIT0_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 691 #define SIT0_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 692 #define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 693 #define SIT0_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 694 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 695 #define SIT0_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 696 #define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 697 #define SIT0_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 698 #define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 699 #define SIT0_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 700 #define SIT0_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 701 #define SIT0_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 702 #define SIT0_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L 703 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 704 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 705 #define SIT0_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 706 #define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 707 #define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 708 #define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 709 #define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 710 #define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 711 #define SIT0_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 712 #define SIT0_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 713 #define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 714 #define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 715 #define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 716 #define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 717 #define SIT0_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 718 //SIT1_NXT_SUVD_CGC_GATE 719 #define SIT1_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 720 #define SIT1_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 721 #define SIT1_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 722 #define SIT1_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 723 #define SIT1_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 724 #define SIT1_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 725 #define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 726 #define SIT1_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 727 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 728 #define SIT1_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 729 #define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 730 #define SIT1_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 731 #define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 732 #define SIT1_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 733 #define SIT1_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 734 #define SIT1_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf 735 #define SIT1_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 736 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 737 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 738 #define SIT1_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 739 #define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 740 #define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 741 #define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 742 #define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 743 #define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 744 #define SIT1_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 745 #define SIT1_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 746 #define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 747 #define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 748 #define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 749 #define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 750 #define SIT1_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 751 #define SIT1_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 752 #define SIT1_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 753 #define SIT1_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 754 #define SIT1_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 755 #define SIT1_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 756 #define SIT1_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 757 #define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 758 #define SIT1_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 759 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 760 #define SIT1_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 761 #define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 762 #define SIT1_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 763 #define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 764 #define SIT1_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 765 #define SIT1_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 766 #define SIT1_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 767 #define SIT1_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L 768 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 769 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 770 #define SIT1_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 771 #define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 772 #define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 773 #define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 774 #define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 775 #define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 776 #define SIT1_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 777 #define SIT1_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 778 #define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 779 #define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 780 #define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 781 #define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 782 #define SIT1_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 783 //SIT2_NXT_SUVD_CGC_GATE 784 #define SIT2_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 785 #define SIT2_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 786 #define SIT2_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 787 #define SIT2_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 788 #define SIT2_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 789 #define SIT2_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 790 #define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 791 #define SIT2_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 792 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 793 #define SIT2_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 794 #define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 795 #define SIT2_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 796 #define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 797 #define SIT2_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 798 #define SIT2_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 799 #define SIT2_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf 800 #define SIT2_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 801 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 802 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 803 #define SIT2_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 804 #define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 805 #define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 806 #define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 807 #define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 808 #define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 809 #define SIT2_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 810 #define SIT2_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 811 #define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 812 #define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 813 #define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 814 #define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 815 #define SIT2_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 816 #define SIT2_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 817 #define SIT2_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 818 #define SIT2_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 819 #define SIT2_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 820 #define SIT2_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 821 #define SIT2_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 822 #define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 823 #define SIT2_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 824 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 825 #define SIT2_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 826 #define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 827 #define SIT2_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 828 #define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 829 #define SIT2_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 830 #define SIT2_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 831 #define SIT2_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 832 #define SIT2_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L 833 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 834 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 835 #define SIT2_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 836 #define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 837 #define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 838 #define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 839 #define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 840 #define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 841 #define SIT2_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 842 #define SIT2_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 843 #define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 844 #define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 845 #define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 846 #define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 847 #define SIT2_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 848 //SIT_SUVD_CGC_GATE 849 #define SIT_SUVD_CGC_GATE__SRE__SHIFT 0x0 850 #define SIT_SUVD_CGC_GATE__SIT__SHIFT 0x1 851 #define SIT_SUVD_CGC_GATE__SMP__SHIFT 0x2 852 #define SIT_SUVD_CGC_GATE__SCM__SHIFT 0x3 853 #define SIT_SUVD_CGC_GATE__SDB__SHIFT 0x4 854 #define SIT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 855 #define SIT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 856 #define SIT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 857 #define SIT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 858 #define SIT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 859 #define SIT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 860 #define SIT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 861 #define SIT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 862 #define SIT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 863 #define SIT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 864 #define SIT_SUVD_CGC_GATE__ENT__SHIFT 0xf 865 #define SIT_SUVD_CGC_GATE__IME__SHIFT 0x10 866 #define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 867 #define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 868 #define SIT_SUVD_CGC_GATE__SITE__SHIFT 0x13 869 #define SIT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 870 #define SIT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 871 #define SIT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 872 #define SIT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 873 #define SIT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 874 #define SIT_SUVD_CGC_GATE__EFC__SHIFT 0x19 875 #define SIT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 876 #define SIT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 877 #define SIT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 878 #define SIT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 879 #define SIT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 880 #define SIT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 881 #define SIT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 882 #define SIT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 883 #define SIT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 884 #define SIT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 885 #define SIT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 886 #define SIT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 887 #define SIT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 888 #define SIT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 889 #define SIT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 890 #define SIT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 891 #define SIT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 892 #define SIT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 893 #define SIT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 894 #define SIT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 895 #define SIT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 896 #define SIT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 897 #define SIT_SUVD_CGC_GATE__IME_MASK 0x00010000L 898 #define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 899 #define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 900 #define SIT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 901 #define SIT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 902 #define SIT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 903 #define SIT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 904 #define SIT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 905 #define SIT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 906 #define SIT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 907 #define SIT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 908 #define SIT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 909 #define SIT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 910 #define SIT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 911 #define SIT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 912 #define SIT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 913 //SMPA_SUVD_CGC_GATE 914 #define SMPA_SUVD_CGC_GATE__SRE__SHIFT 0x0 915 #define SMPA_SUVD_CGC_GATE__SIT__SHIFT 0x1 916 #define SMPA_SUVD_CGC_GATE__SMP__SHIFT 0x2 917 #define SMPA_SUVD_CGC_GATE__SCM__SHIFT 0x3 918 #define SMPA_SUVD_CGC_GATE__SDB__SHIFT 0x4 919 #define SMPA_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 920 #define SMPA_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 921 #define SMPA_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 922 #define SMPA_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 923 #define SMPA_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 924 #define SMPA_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 925 #define SMPA_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 926 #define SMPA_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 927 #define SMPA_SUVD_CGC_GATE__SCLR__SHIFT 0xd 928 #define SMPA_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 929 #define SMPA_SUVD_CGC_GATE__ENT__SHIFT 0xf 930 #define SMPA_SUVD_CGC_GATE__IME__SHIFT 0x10 931 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 932 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 933 #define SMPA_SUVD_CGC_GATE__SITE__SHIFT 0x13 934 #define SMPA_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 935 #define SMPA_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 936 #define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 937 #define SMPA_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 938 #define SMPA_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 939 #define SMPA_SUVD_CGC_GATE__EFC__SHIFT 0x19 940 #define SMPA_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 941 #define SMPA_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 942 #define SMPA_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 943 #define SMPA_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 944 #define SMPA_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 945 #define SMPA_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 946 #define SMPA_SUVD_CGC_GATE__SRE_MASK 0x00000001L 947 #define SMPA_SUVD_CGC_GATE__SIT_MASK 0x00000002L 948 #define SMPA_SUVD_CGC_GATE__SMP_MASK 0x00000004L 949 #define SMPA_SUVD_CGC_GATE__SCM_MASK 0x00000008L 950 #define SMPA_SUVD_CGC_GATE__SDB_MASK 0x00000010L 951 #define SMPA_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 952 #define SMPA_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 953 #define SMPA_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 954 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 955 #define SMPA_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 956 #define SMPA_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 957 #define SMPA_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 958 #define SMPA_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 959 #define SMPA_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 960 #define SMPA_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 961 #define SMPA_SUVD_CGC_GATE__ENT_MASK 0x00008000L 962 #define SMPA_SUVD_CGC_GATE__IME_MASK 0x00010000L 963 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 964 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 965 #define SMPA_SUVD_CGC_GATE__SITE_MASK 0x00080000L 966 #define SMPA_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 967 #define SMPA_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 968 #define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 969 #define SMPA_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 970 #define SMPA_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 971 #define SMPA_SUVD_CGC_GATE__EFC_MASK 0x02000000L 972 #define SMPA_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 973 #define SMPA_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 974 #define SMPA_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 975 #define SMPA_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 976 #define SMPA_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 977 #define SMPA_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 978 //SMP_SUVD_CGC_GATE 979 #define SMP_SUVD_CGC_GATE__SRE__SHIFT 0x0 980 #define SMP_SUVD_CGC_GATE__SIT__SHIFT 0x1 981 #define SMP_SUVD_CGC_GATE__SMP__SHIFT 0x2 982 #define SMP_SUVD_CGC_GATE__SCM__SHIFT 0x3 983 #define SMP_SUVD_CGC_GATE__SDB__SHIFT 0x4 984 #define SMP_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 985 #define SMP_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 986 #define SMP_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 987 #define SMP_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 988 #define SMP_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 989 #define SMP_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 990 #define SMP_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 991 #define SMP_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 992 #define SMP_SUVD_CGC_GATE__SCLR__SHIFT 0xd 993 #define SMP_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 994 #define SMP_SUVD_CGC_GATE__ENT__SHIFT 0xf 995 #define SMP_SUVD_CGC_GATE__IME__SHIFT 0x10 996 #define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 997 #define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 998 #define SMP_SUVD_CGC_GATE__SITE__SHIFT 0x13 999 #define SMP_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1000 #define SMP_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1001 #define SMP_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1002 #define SMP_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1003 #define SMP_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1004 #define SMP_SUVD_CGC_GATE__EFC__SHIFT 0x19 1005 #define SMP_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1006 #define SMP_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1007 #define SMP_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1008 #define SMP_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1009 #define SMP_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1010 #define SMP_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1011 #define SMP_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1012 #define SMP_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1013 #define SMP_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1014 #define SMP_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1015 #define SMP_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1016 #define SMP_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1017 #define SMP_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1018 #define SMP_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1019 #define SMP_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1020 #define SMP_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1021 #define SMP_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1022 #define SMP_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1023 #define SMP_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1024 #define SMP_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1025 #define SMP_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1026 #define SMP_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1027 #define SMP_SUVD_CGC_GATE__IME_MASK 0x00010000L 1028 #define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1029 #define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1030 #define SMP_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1031 #define SMP_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1032 #define SMP_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1033 #define SMP_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1034 #define SMP_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1035 #define SMP_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1036 #define SMP_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1037 #define SMP_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1038 #define SMP_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1039 #define SMP_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1040 #define SMP_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1041 #define SMP_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1042 #define SMP_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1043 //SRE_SUVD_CGC_GATE 1044 #define SRE_SUVD_CGC_GATE__SRE__SHIFT 0x0 1045 #define SRE_SUVD_CGC_GATE__SIT__SHIFT 0x1 1046 #define SRE_SUVD_CGC_GATE__SMP__SHIFT 0x2 1047 #define SRE_SUVD_CGC_GATE__SCM__SHIFT 0x3 1048 #define SRE_SUVD_CGC_GATE__SDB__SHIFT 0x4 1049 #define SRE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1050 #define SRE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1051 #define SRE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1052 #define SRE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1053 #define SRE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1054 #define SRE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1055 #define SRE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1056 #define SRE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1057 #define SRE_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1058 #define SRE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1059 #define SRE_SUVD_CGC_GATE__ENT__SHIFT 0xf 1060 #define SRE_SUVD_CGC_GATE__IME__SHIFT 0x10 1061 #define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1062 #define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1063 #define SRE_SUVD_CGC_GATE__SITE__SHIFT 0x13 1064 #define SRE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1065 #define SRE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1066 #define SRE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1067 #define SRE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1068 #define SRE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1069 #define SRE_SUVD_CGC_GATE__EFC__SHIFT 0x19 1070 #define SRE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1071 #define SRE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1072 #define SRE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1073 #define SRE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1074 #define SRE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1075 #define SRE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1076 #define SRE_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1077 #define SRE_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1078 #define SRE_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1079 #define SRE_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1080 #define SRE_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1081 #define SRE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1082 #define SRE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1083 #define SRE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1084 #define SRE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1085 #define SRE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1086 #define SRE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1087 #define SRE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1088 #define SRE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1089 #define SRE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1090 #define SRE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1091 #define SRE_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1092 #define SRE_SUVD_CGC_GATE__IME_MASK 0x00010000L 1093 #define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1094 #define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1095 #define SRE_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1096 #define SRE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1097 #define SRE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1098 #define SRE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1099 #define SRE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1100 #define SRE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1101 #define SRE_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1102 #define SRE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1103 #define SRE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1104 #define SRE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1105 #define SRE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1106 #define SRE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1107 #define SRE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1108 //UVD_SUVD_CGC_GATE 1109 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 1110 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 1111 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 1112 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 1113 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 1114 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1115 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1116 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1117 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1118 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1119 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1120 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1121 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1122 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1123 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1124 #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 1125 #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 1126 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1127 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1128 #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 1129 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1130 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1131 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1132 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1133 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1134 #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 1135 #define UVD_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1136 #define UVD_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1137 #define UVD_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1138 #define UVD_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1139 #define UVD_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1140 #define UVD_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1141 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1142 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1143 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1144 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1145 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1146 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1147 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1148 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1149 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1150 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1151 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1152 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1153 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1154 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1155 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1156 #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1157 #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 1158 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1159 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1160 #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1161 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1162 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1163 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1164 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1165 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1166 #define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1167 #define UVD_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1168 #define UVD_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1169 #define UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1170 #define UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1171 #define UVD_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1172 #define UVD_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1173 //AVM_SUVD_CGC_GATE2 1174 #define AVM_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1175 #define AVM_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1176 #define AVM_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1177 #define AVM_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1178 #define AVM_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1179 #define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1180 #define AVM_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1181 #define AVM_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1182 #define AVM_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1183 #define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1184 #define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1185 #define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1186 #define AVM_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1187 #define AVM_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1188 #define AVM_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1189 #define AVM_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1190 #define AVM_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1191 #define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1192 #define AVM_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1193 #define AVM_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1194 #define AVM_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1195 #define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1196 #define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1197 #define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1198 //DBR_SUVD_CGC_GATE2 1199 #define DBR_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1200 #define DBR_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1201 #define DBR_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1202 #define DBR_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1203 #define DBR_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1204 #define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1205 #define DBR_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1206 #define DBR_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1207 #define DBR_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1208 #define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1209 #define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1210 #define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1211 #define DBR_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1212 #define DBR_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1213 #define DBR_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1214 #define DBR_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1215 #define DBR_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1216 #define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1217 #define DBR_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1218 #define DBR_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1219 #define DBR_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1220 #define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1221 #define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1222 #define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1223 //ENT_SUVD_CGC_GATE2 1224 #define ENT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1225 #define ENT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1226 #define ENT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1227 #define ENT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1228 #define ENT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1229 #define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1230 #define ENT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1231 #define ENT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1232 #define ENT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1233 #define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1234 #define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1235 #define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1236 #define ENT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1237 #define ENT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1238 #define ENT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1239 #define ENT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1240 #define ENT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1241 #define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1242 #define ENT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1243 #define ENT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1244 #define ENT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1245 #define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1246 #define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1247 #define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1248 //IME_SUVD_CGC_GATE2 1249 #define IME_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1250 #define IME_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1251 #define IME_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1252 #define IME_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1253 #define IME_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1254 #define IME_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1255 #define IME_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1256 #define IME_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1257 #define IME_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1258 #define IME_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1259 #define IME_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1260 #define IME_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1261 #define IME_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1262 #define IME_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1263 #define IME_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1264 #define IME_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1265 #define IME_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1266 #define IME_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1267 #define IME_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1268 #define IME_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1269 #define IME_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1270 #define IME_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1271 #define IME_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1272 #define IME_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1273 //SAOE_SUVD_CGC_GATE2 1274 #define SAOE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1275 #define SAOE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1276 #define SAOE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1277 #define SAOE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1278 #define SAOE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1279 #define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1280 #define SAOE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1281 #define SAOE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1282 #define SAOE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1283 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1284 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1285 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1286 #define SAOE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1287 #define SAOE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1288 #define SAOE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1289 #define SAOE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1290 #define SAOE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1291 #define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1292 #define SAOE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1293 #define SAOE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1294 #define SAOE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1295 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1296 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1297 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1298 //SDB_SUVD_CGC_GATE2 1299 #define SDB_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1300 #define SDB_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1301 #define SDB_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1302 #define SDB_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1303 #define SDB_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1304 #define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1305 #define SDB_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1306 #define SDB_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1307 #define SDB_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1308 #define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1309 #define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1310 #define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1311 #define SDB_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1312 #define SDB_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1313 #define SDB_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1314 #define SDB_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1315 #define SDB_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1316 #define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1317 #define SDB_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1318 #define SDB_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1319 #define SDB_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1320 #define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1321 #define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1322 #define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1323 //SIT0_NXT_SUVD_CGC_GATE2 1324 #define SIT0_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1325 #define SIT0_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1326 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1327 #define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1328 #define SIT0_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1329 #define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1330 #define SIT0_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1331 #define SIT0_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1332 #define SIT0_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1333 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1334 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1335 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1336 #define SIT0_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1337 #define SIT0_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1338 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1339 #define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1340 #define SIT0_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1341 #define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1342 #define SIT0_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1343 #define SIT0_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1344 #define SIT0_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1345 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1346 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1347 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1348 //SIT1_NXT_SUVD_CGC_GATE2 1349 #define SIT1_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1350 #define SIT1_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1351 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1352 #define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1353 #define SIT1_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1354 #define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1355 #define SIT1_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1356 #define SIT1_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1357 #define SIT1_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1358 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1359 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1360 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1361 #define SIT1_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1362 #define SIT1_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1363 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1364 #define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1365 #define SIT1_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1366 #define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1367 #define SIT1_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1368 #define SIT1_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1369 #define SIT1_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1370 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1371 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1372 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1373 //SIT2_NXT_SUVD_CGC_GATE2 1374 #define SIT2_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1375 #define SIT2_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1376 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1377 #define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1378 #define SIT2_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1379 #define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1380 #define SIT2_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1381 #define SIT2_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1382 #define SIT2_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1383 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1384 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1385 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1386 #define SIT2_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1387 #define SIT2_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1388 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1389 #define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1390 #define SIT2_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1391 #define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1392 #define SIT2_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1393 #define SIT2_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1394 #define SIT2_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1395 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1396 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1397 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1398 //SIT_SUVD_CGC_GATE2 1399 #define SIT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1400 #define SIT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1401 #define SIT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1402 #define SIT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1403 #define SIT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1404 #define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1405 #define SIT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1406 #define SIT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1407 #define SIT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1408 #define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1409 #define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1410 #define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1411 #define SIT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1412 #define SIT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1413 #define SIT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1414 #define SIT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1415 #define SIT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1416 #define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1417 #define SIT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1418 #define SIT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1419 #define SIT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1420 #define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1421 #define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1422 #define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1423 //SMPA_SUVD_CGC_GATE2 1424 #define SMPA_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1425 #define SMPA_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1426 #define SMPA_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1427 #define SMPA_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1428 #define SMPA_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1429 #define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1430 #define SMPA_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1431 #define SMPA_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1432 #define SMPA_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1433 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1434 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1435 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1436 #define SMPA_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1437 #define SMPA_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1438 #define SMPA_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1439 #define SMPA_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1440 #define SMPA_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1441 #define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1442 #define SMPA_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1443 #define SMPA_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1444 #define SMPA_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1445 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1446 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1447 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1448 //SMP_SUVD_CGC_GATE2 1449 #define SMP_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1450 #define SMP_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1451 #define SMP_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1452 #define SMP_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1453 #define SMP_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1454 #define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1455 #define SMP_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1456 #define SMP_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1457 #define SMP_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1458 #define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1459 #define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1460 #define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1461 #define SMP_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1462 #define SMP_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1463 #define SMP_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1464 #define SMP_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1465 #define SMP_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1466 #define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1467 #define SMP_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1468 #define SMP_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1469 #define SMP_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1470 #define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1471 #define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1472 #define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1473 //SRE_SUVD_CGC_GATE2 1474 #define SRE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1475 #define SRE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1476 #define SRE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1477 #define SRE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1478 #define SRE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1479 #define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1480 #define SRE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1481 #define SRE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1482 #define SRE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1483 #define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1484 #define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1485 #define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1486 #define SRE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1487 #define SRE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1488 #define SRE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1489 #define SRE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1490 #define SRE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1491 #define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1492 #define SRE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1493 #define SRE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1494 #define SRE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1495 #define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1496 #define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1497 #define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1498 //UVD_SUVD_CGC_GATE2 1499 #define UVD_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1500 #define UVD_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1501 #define UVD_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1502 #define UVD_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1503 #define UVD_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1504 #define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1505 #define UVD_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1506 #define UVD_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1507 #define UVD_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1508 #define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1509 #define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1510 #define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1511 #define UVD_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1512 #define UVD_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1513 #define UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1514 #define UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1515 #define UVD_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1516 #define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1517 #define UVD_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1518 #define UVD_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1519 #define UVD_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1520 #define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1521 #define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1522 #define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1523 //AVM_SUVD_CGC_CTRL 1524 #define AVM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1525 #define AVM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1526 #define AVM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1527 #define AVM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1528 #define AVM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1529 #define AVM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1530 #define AVM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1531 #define AVM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1532 #define AVM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1533 #define AVM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1534 #define AVM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1535 #define AVM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1536 #define AVM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1537 #define AVM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1538 #define AVM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1539 #define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1540 #define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1541 #define AVM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1542 #define AVM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1543 #define AVM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1544 #define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1545 #define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1546 #define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1547 #define AVM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1548 #define AVM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1549 #define AVM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1550 #define AVM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1551 #define AVM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1552 #define AVM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1553 #define AVM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1554 #define AVM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1555 #define AVM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1556 #define AVM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1557 #define AVM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1558 #define AVM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1559 #define AVM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1560 #define AVM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1561 #define AVM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1562 #define AVM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1563 #define AVM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1564 #define AVM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1565 #define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1566 #define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1567 #define AVM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1568 #define AVM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1569 #define AVM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1570 #define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1571 #define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1572 #define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1573 #define AVM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1574 #define AVM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1575 #define AVM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1576 //DBR_SUVD_CGC_CTRL 1577 #define DBR_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1578 #define DBR_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1579 #define DBR_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1580 #define DBR_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1581 #define DBR_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1582 #define DBR_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1583 #define DBR_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1584 #define DBR_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1585 #define DBR_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1586 #define DBR_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1587 #define DBR_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1588 #define DBR_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1589 #define DBR_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1590 #define DBR_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1591 #define DBR_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1592 #define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1593 #define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1594 #define DBR_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1595 #define DBR_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1596 #define DBR_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1597 #define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1598 #define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1599 #define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1600 #define DBR_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1601 #define DBR_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1602 #define DBR_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1603 #define DBR_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1604 #define DBR_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1605 #define DBR_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1606 #define DBR_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1607 #define DBR_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1608 #define DBR_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1609 #define DBR_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1610 #define DBR_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1611 #define DBR_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1612 #define DBR_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1613 #define DBR_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1614 #define DBR_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1615 #define DBR_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1616 #define DBR_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1617 #define DBR_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1618 #define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1619 #define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1620 #define DBR_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1621 #define DBR_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1622 #define DBR_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1623 #define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1624 #define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1625 #define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1626 #define DBR_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1627 #define DBR_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1628 #define DBR_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1629 //EFC_SUVD_CGC_CTRL 1630 #define EFC_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1631 #define EFC_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1632 #define EFC_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1633 #define EFC_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1634 #define EFC_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1635 #define EFC_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1636 #define EFC_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1637 #define EFC_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1638 #define EFC_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1639 #define EFC_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1640 #define EFC_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1641 #define EFC_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1642 #define EFC_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1643 #define EFC_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1644 #define EFC_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1645 #define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1646 #define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1647 #define EFC_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1648 #define EFC_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1649 #define EFC_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1650 #define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1651 #define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1652 #define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1653 #define EFC_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1654 #define EFC_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1655 #define EFC_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1656 #define EFC_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1657 #define EFC_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1658 #define EFC_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1659 #define EFC_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1660 #define EFC_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1661 #define EFC_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1662 #define EFC_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1663 #define EFC_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1664 #define EFC_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1665 #define EFC_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1666 #define EFC_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1667 #define EFC_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1668 #define EFC_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1669 #define EFC_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1670 #define EFC_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1671 #define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1672 #define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1673 #define EFC_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1674 #define EFC_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1675 #define EFC_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1676 #define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1677 #define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1678 #define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1679 #define EFC_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1680 #define EFC_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1681 #define EFC_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1682 //ENT_SUVD_CGC_CTRL 1683 #define ENT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1684 #define ENT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1685 #define ENT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1686 #define ENT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1687 #define ENT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1688 #define ENT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1689 #define ENT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1690 #define ENT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1691 #define ENT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1692 #define ENT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1693 #define ENT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1694 #define ENT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1695 #define ENT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1696 #define ENT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1697 #define ENT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1698 #define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1699 #define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1700 #define ENT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1701 #define ENT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1702 #define ENT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1703 #define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1704 #define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1705 #define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1706 #define ENT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1707 #define ENT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1708 #define ENT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1709 #define ENT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1710 #define ENT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1711 #define ENT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1712 #define ENT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1713 #define ENT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1714 #define ENT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1715 #define ENT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1716 #define ENT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1717 #define ENT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1718 #define ENT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1719 #define ENT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1720 #define ENT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1721 #define ENT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1722 #define ENT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1723 #define ENT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1724 #define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1725 #define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1726 #define ENT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1727 #define ENT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1728 #define ENT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1729 #define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1730 #define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1731 #define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1732 #define ENT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1733 #define ENT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1734 #define ENT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1735 //IME_SUVD_CGC_CTRL 1736 #define IME_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1737 #define IME_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1738 #define IME_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1739 #define IME_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1740 #define IME_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1741 #define IME_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1742 #define IME_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1743 #define IME_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1744 #define IME_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1745 #define IME_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1746 #define IME_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1747 #define IME_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1748 #define IME_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1749 #define IME_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1750 #define IME_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1751 #define IME_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1752 #define IME_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1753 #define IME_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1754 #define IME_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1755 #define IME_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1756 #define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1757 #define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1758 #define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1759 #define IME_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1760 #define IME_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1761 #define IME_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1762 #define IME_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1763 #define IME_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1764 #define IME_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1765 #define IME_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1766 #define IME_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1767 #define IME_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1768 #define IME_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1769 #define IME_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1770 #define IME_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1771 #define IME_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1772 #define IME_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1773 #define IME_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1774 #define IME_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1775 #define IME_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1776 #define IME_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1777 #define IME_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1778 #define IME_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1779 #define IME_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1780 #define IME_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1781 #define IME_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1782 #define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1783 #define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1784 #define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1785 #define IME_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1786 #define IME_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1787 #define IME_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1788 //PPU_SUVD_CGC_CTRL 1789 #define PPU_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1790 #define PPU_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1791 #define PPU_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1792 #define PPU_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1793 #define PPU_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1794 #define PPU_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1795 #define PPU_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1796 #define PPU_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1797 #define PPU_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1798 #define PPU_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1799 #define PPU_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1800 #define PPU_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1801 #define PPU_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1802 #define PPU_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1803 #define PPU_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1804 #define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1805 #define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1806 #define PPU_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1807 #define PPU_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1808 #define PPU_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1809 #define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1810 #define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1811 #define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1812 #define PPU_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1813 #define PPU_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1814 #define PPU_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1815 #define PPU_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1816 #define PPU_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1817 #define PPU_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1818 #define PPU_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1819 #define PPU_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1820 #define PPU_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1821 #define PPU_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1822 #define PPU_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1823 #define PPU_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1824 #define PPU_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1825 #define PPU_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1826 #define PPU_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1827 #define PPU_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1828 #define PPU_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1829 #define PPU_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1830 #define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1831 #define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1832 #define PPU_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1833 #define PPU_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1834 #define PPU_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1835 #define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1836 #define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1837 #define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1838 #define PPU_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1839 #define PPU_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1840 #define PPU_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1841 //SAOE_SUVD_CGC_CTRL 1842 #define SAOE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1843 #define SAOE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1844 #define SAOE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1845 #define SAOE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1846 #define SAOE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1847 #define SAOE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1848 #define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1849 #define SAOE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1850 #define SAOE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1851 #define SAOE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1852 #define SAOE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1853 #define SAOE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1854 #define SAOE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1855 #define SAOE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1856 #define SAOE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1857 #define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1858 #define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1859 #define SAOE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1860 #define SAOE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1861 #define SAOE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1862 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1863 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1864 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1865 #define SAOE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1866 #define SAOE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1867 #define SAOE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1868 #define SAOE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1869 #define SAOE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1870 #define SAOE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1871 #define SAOE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1872 #define SAOE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1873 #define SAOE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1874 #define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1875 #define SAOE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1876 #define SAOE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1877 #define SAOE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1878 #define SAOE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1879 #define SAOE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1880 #define SAOE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1881 #define SAOE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1882 #define SAOE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1883 #define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1884 #define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1885 #define SAOE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1886 #define SAOE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1887 #define SAOE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1888 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1889 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1890 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1891 #define SAOE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1892 #define SAOE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1893 #define SAOE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1894 //SCM_SUVD_CGC_CTRL 1895 #define SCM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1896 #define SCM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1897 #define SCM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1898 #define SCM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1899 #define SCM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1900 #define SCM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1901 #define SCM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1902 #define SCM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1903 #define SCM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1904 #define SCM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1905 #define SCM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1906 #define SCM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1907 #define SCM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1908 #define SCM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1909 #define SCM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1910 #define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1911 #define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1912 #define SCM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1913 #define SCM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1914 #define SCM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1915 #define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1916 #define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1917 #define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1918 #define SCM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1919 #define SCM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1920 #define SCM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1921 #define SCM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1922 #define SCM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1923 #define SCM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1924 #define SCM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1925 #define SCM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1926 #define SCM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1927 #define SCM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1928 #define SCM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1929 #define SCM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1930 #define SCM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1931 #define SCM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1932 #define SCM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1933 #define SCM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1934 #define SCM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1935 #define SCM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1936 #define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1937 #define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1938 #define SCM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1939 #define SCM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1940 #define SCM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1941 #define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1942 #define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1943 #define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1944 #define SCM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1945 #define SCM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1946 #define SCM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1947 //SDB_SUVD_CGC_CTRL 1948 #define SDB_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1949 #define SDB_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1950 #define SDB_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1951 #define SDB_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1952 #define SDB_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1953 #define SDB_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1954 #define SDB_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1955 #define SDB_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1956 #define SDB_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1957 #define SDB_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1958 #define SDB_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1959 #define SDB_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1960 #define SDB_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1961 #define SDB_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1962 #define SDB_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1963 #define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1964 #define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1965 #define SDB_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1966 #define SDB_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1967 #define SDB_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1968 #define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1969 #define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1970 #define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1971 #define SDB_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1972 #define SDB_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1973 #define SDB_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1974 #define SDB_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1975 #define SDB_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1976 #define SDB_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1977 #define SDB_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1978 #define SDB_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1979 #define SDB_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1980 #define SDB_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1981 #define SDB_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1982 #define SDB_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1983 #define SDB_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1984 #define SDB_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1985 #define SDB_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1986 #define SDB_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1987 #define SDB_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1988 #define SDB_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1989 #define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1990 #define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1991 #define SDB_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1992 #define SDB_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1993 #define SDB_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1994 #define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1995 #define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1996 #define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1997 #define SDB_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1998 #define SDB_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1999 #define SDB_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2000 //SIT0_NXT_SUVD_CGC_CTRL 2001 #define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2002 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2003 #define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2004 #define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2005 #define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2006 #define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2007 #define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2008 #define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2009 #define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2010 #define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2011 #define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2012 #define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2013 #define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2014 #define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2015 #define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2016 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2017 #define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2018 #define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2019 #define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2020 #define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2021 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2022 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2023 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2024 #define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2025 #define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2026 #define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2027 #define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2028 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2029 #define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2030 #define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2031 #define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2032 #define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2033 #define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2034 #define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2035 #define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2036 #define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2037 #define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2038 #define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2039 #define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2040 #define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2041 #define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2042 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2043 #define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2044 #define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2045 #define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2046 #define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2047 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2048 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2049 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2050 #define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2051 #define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2052 #define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2053 //SIT1_NXT_SUVD_CGC_CTRL 2054 #define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2055 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2056 #define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2057 #define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2058 #define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2059 #define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2060 #define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2061 #define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2062 #define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2063 #define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2064 #define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2065 #define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2066 #define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2067 #define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2068 #define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2069 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2070 #define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2071 #define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2072 #define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2073 #define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2074 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2075 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2076 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2077 #define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2078 #define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2079 #define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2080 #define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2081 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2082 #define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2083 #define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2084 #define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2085 #define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2086 #define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2087 #define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2088 #define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2089 #define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2090 #define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2091 #define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2092 #define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2093 #define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2094 #define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2095 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2096 #define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2097 #define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2098 #define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2099 #define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2100 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2101 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2102 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2103 #define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2104 #define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2105 #define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2106 //SIT2_NXT_SUVD_CGC_CTRL 2107 #define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2108 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2109 #define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2110 #define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2111 #define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2112 #define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2113 #define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2114 #define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2115 #define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2116 #define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2117 #define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2118 #define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2119 #define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2120 #define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2121 #define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2122 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2123 #define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2124 #define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2125 #define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2126 #define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2127 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2128 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2129 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2130 #define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2131 #define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2132 #define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2133 #define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2134 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2135 #define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2136 #define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2137 #define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2138 #define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2139 #define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2140 #define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2141 #define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2142 #define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2143 #define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2144 #define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2145 #define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2146 #define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2147 #define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2148 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2149 #define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2150 #define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2151 #define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2152 #define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2153 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2154 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2155 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2156 #define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2157 #define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2158 #define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2159 //SIT_SUVD_CGC_CTRL 2160 #define SIT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2161 #define SIT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2162 #define SIT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2163 #define SIT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2164 #define SIT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2165 #define SIT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2166 #define SIT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2167 #define SIT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2168 #define SIT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2169 #define SIT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2170 #define SIT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2171 #define SIT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2172 #define SIT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2173 #define SIT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2174 #define SIT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2175 #define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2176 #define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2177 #define SIT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2178 #define SIT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2179 #define SIT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2180 #define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2181 #define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2182 #define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2183 #define SIT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2184 #define SIT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2185 #define SIT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2186 #define SIT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2187 #define SIT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2188 #define SIT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2189 #define SIT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2190 #define SIT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2191 #define SIT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2192 #define SIT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2193 #define SIT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2194 #define SIT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2195 #define SIT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2196 #define SIT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2197 #define SIT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2198 #define SIT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2199 #define SIT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2200 #define SIT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2201 #define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2202 #define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2203 #define SIT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2204 #define SIT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2205 #define SIT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2206 #define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2207 #define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2208 #define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2209 #define SIT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2210 #define SIT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2211 #define SIT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2212 //SMPA_SUVD_CGC_CTRL 2213 #define SMPA_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2214 #define SMPA_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2215 #define SMPA_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2216 #define SMPA_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2217 #define SMPA_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2218 #define SMPA_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2219 #define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2220 #define SMPA_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2221 #define SMPA_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2222 #define SMPA_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2223 #define SMPA_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2224 #define SMPA_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2225 #define SMPA_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2226 #define SMPA_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2227 #define SMPA_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2228 #define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2229 #define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2230 #define SMPA_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2231 #define SMPA_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2232 #define SMPA_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2233 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2234 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2235 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2236 #define SMPA_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2237 #define SMPA_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2238 #define SMPA_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2239 #define SMPA_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2240 #define SMPA_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2241 #define SMPA_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2242 #define SMPA_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2243 #define SMPA_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2244 #define SMPA_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2245 #define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2246 #define SMPA_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2247 #define SMPA_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2248 #define SMPA_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2249 #define SMPA_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2250 #define SMPA_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2251 #define SMPA_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2252 #define SMPA_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2253 #define SMPA_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2254 #define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2255 #define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2256 #define SMPA_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2257 #define SMPA_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2258 #define SMPA_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2259 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2260 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2261 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2262 #define SMPA_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2263 #define SMPA_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2264 #define SMPA_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2265 //SMP_SUVD_CGC_CTRL 2266 #define SMP_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2267 #define SMP_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2268 #define SMP_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2269 #define SMP_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2270 #define SMP_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2271 #define SMP_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2272 #define SMP_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2273 #define SMP_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2274 #define SMP_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2275 #define SMP_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2276 #define SMP_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2277 #define SMP_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2278 #define SMP_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2279 #define SMP_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2280 #define SMP_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2281 #define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2282 #define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2283 #define SMP_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2284 #define SMP_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2285 #define SMP_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2286 #define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2287 #define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2288 #define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2289 #define SMP_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2290 #define SMP_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2291 #define SMP_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2292 #define SMP_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2293 #define SMP_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2294 #define SMP_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2295 #define SMP_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2296 #define SMP_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2297 #define SMP_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2298 #define SMP_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2299 #define SMP_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2300 #define SMP_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2301 #define SMP_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2302 #define SMP_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2303 #define SMP_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2304 #define SMP_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2305 #define SMP_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2306 #define SMP_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2307 #define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2308 #define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2309 #define SMP_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2310 #define SMP_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2311 #define SMP_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2312 #define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2313 #define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2314 #define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2315 #define SMP_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2316 #define SMP_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2317 #define SMP_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2318 //SRE_SUVD_CGC_CTRL 2319 #define SRE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2320 #define SRE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2321 #define SRE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2322 #define SRE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2323 #define SRE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2324 #define SRE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2325 #define SRE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2326 #define SRE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2327 #define SRE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2328 #define SRE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2329 #define SRE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2330 #define SRE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2331 #define SRE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2332 #define SRE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2333 #define SRE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2334 #define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2335 #define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2336 #define SRE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2337 #define SRE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2338 #define SRE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2339 #define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2340 #define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2341 #define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2342 #define SRE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2343 #define SRE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2344 #define SRE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2345 #define SRE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2346 #define SRE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2347 #define SRE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2348 #define SRE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2349 #define SRE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2350 #define SRE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2351 #define SRE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2352 #define SRE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2353 #define SRE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2354 #define SRE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2355 #define SRE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2356 #define SRE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2357 #define SRE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2358 #define SRE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2359 #define SRE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2360 #define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2361 #define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2362 #define SRE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2363 #define SRE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2364 #define SRE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2365 #define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2366 #define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2367 #define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2368 #define SRE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2369 #define SRE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2370 #define SRE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2371 //UVD_SUVD_CGC_CTRL 2372 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2373 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2374 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2375 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2376 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2377 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2378 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2379 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2380 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2381 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2382 #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2383 #define UVD_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2384 #define UVD_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2385 #define UVD_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2386 #define UVD_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2387 #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2388 #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2389 #define UVD_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2390 #define UVD_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2391 #define UVD_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2392 #define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2393 #define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2394 #define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2395 #define UVD_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2396 #define UVD_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2397 #define UVD_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2398 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2399 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2400 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2401 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2402 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2403 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2404 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2405 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2406 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2407 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2408 #define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2409 #define UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2410 #define UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2411 #define UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2412 #define UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2413 #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2414 #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2415 #define UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2416 #define UVD_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2417 #define UVD_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2418 #define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2419 #define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2420 #define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2421 #define UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2422 #define UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2423 #define UVD_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2424 //UVD_CGC_CTRL3 2425 #define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY__SHIFT 0x0 2426 #define UVD_CGC_CTRL3__LCM0_MODE__SHIFT 0xb 2427 #define UVD_CGC_CTRL3__LCM1_MODE__SHIFT 0xc 2428 #define UVD_CGC_CTRL3__MIF_MODE__SHIFT 0xd 2429 #define UVD_CGC_CTRL3__VREG_MODE__SHIFT 0xe 2430 #define UVD_CGC_CTRL3__PE_MODE__SHIFT 0xf 2431 #define UVD_CGC_CTRL3__PPU_MODE__SHIFT 0x10 2432 #define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY_MASK 0x000000FFL 2433 #define UVD_CGC_CTRL3__LCM0_MODE_MASK 0x00000800L 2434 #define UVD_CGC_CTRL3__LCM1_MODE_MASK 0x00001000L 2435 #define UVD_CGC_CTRL3__MIF_MODE_MASK 0x00002000L 2436 #define UVD_CGC_CTRL3__VREG_MODE_MASK 0x00004000L 2437 #define UVD_CGC_CTRL3__PE_MODE_MASK 0x00008000L 2438 #define UVD_CGC_CTRL3__PPU_MODE_MASK 0x00010000L 2439 //UVD_GPCOM_VCPU_DATA0 2440 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 2441 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 2442 //UVD_GPCOM_VCPU_DATA1 2443 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 2444 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 2445 //UVD_GPCOM_SYS_CMD 2446 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 2447 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 2448 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 2449 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 2450 #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 2451 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 2452 //UVD_GPCOM_SYS_DATA0 2453 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 2454 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 2455 //UVD_GPCOM_SYS_DATA1 2456 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 2457 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 2458 //UVD_VCPU_INT_EN 2459 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2460 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2461 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2462 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 2463 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 2464 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 2465 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2466 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 2467 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 2468 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 2469 #define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 2470 #define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 2471 #define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT 0xd 2472 #define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT 0xe 2473 #define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf 2474 #define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 2475 #define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 2476 #define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 2477 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2478 #define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 2479 #define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 2480 #define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 2481 #define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2482 #define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2483 #define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2484 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 2485 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 2486 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2487 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2488 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2489 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 2490 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 2491 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 2492 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2493 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 2494 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 2495 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 2496 #define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 2497 #define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 2498 #define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN_MASK 0x00002000L 2499 #define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN_MASK 0x00004000L 2500 #define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L 2501 #define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 2502 #define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 2503 #define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 2504 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2505 #define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 2506 #define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 2507 #define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 2508 #define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2509 #define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2510 #define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2511 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 2512 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 2513 //UVD_VCPU_INT_STATUS 2514 #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 2515 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 2516 #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 2517 #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3 2518 #define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4 2519 #define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5 2520 #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 2521 #define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7 2522 #define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9 2523 #define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa 2524 #define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb 2525 #define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc 2526 #define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT__SHIFT 0xd 2527 #define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0xe 2528 #define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf 2529 #define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10 2530 #define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11 2531 #define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12 2532 #define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14 2533 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 2534 #define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18 2535 #define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19 2536 #define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a 2537 #define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 2538 #define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c 2539 #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 2540 #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e 2541 #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f 2542 #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 2543 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 2544 #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 2545 #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L 2546 #define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L 2547 #define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L 2548 #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 2549 #define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L 2550 #define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L 2551 #define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L 2552 #define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L 2553 #define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L 2554 #define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT_MASK 0x00002000L 2555 #define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00004000L 2556 #define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L 2557 #define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L 2558 #define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L 2559 #define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L 2560 #define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L 2561 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 2562 #define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L 2563 #define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L 2564 #define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L 2565 #define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 2566 #define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L 2567 #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 2568 #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L 2569 #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L 2570 //UVD_VCPU_INT_ACK 2571 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2572 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2573 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2574 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 2575 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 2576 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 2577 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2578 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 2579 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 2580 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 2581 #define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 2582 #define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 2583 #define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT 0xd 2584 #define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT 0xe 2585 #define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf 2586 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 2587 #define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 2588 #define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 2589 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2590 #define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 2591 #define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 2592 #define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 2593 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2594 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2595 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2596 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 2597 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 2598 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2599 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2600 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2601 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 2602 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 2603 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 2604 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2605 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 2606 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 2607 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 2608 #define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 2609 #define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 2610 #define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK_MASK 0x00002000L 2611 #define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK_MASK 0x00004000L 2612 #define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L 2613 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 2614 #define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 2615 #define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 2616 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2617 #define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 2618 #define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 2619 #define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 2620 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2621 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2622 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2623 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 2624 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 2625 //UVD_VCPU_INT_ROUTE 2626 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 2627 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 2628 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 2629 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 2630 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 2631 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 2632 //UVD_DRV_FW_MSG 2633 #define UVD_DRV_FW_MSG__MSG__SHIFT 0x0 2634 #define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL 2635 //UVD_FW_DRV_MSG_ACK 2636 #define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0 2637 #define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L 2638 //UVD_SUVD_INT_EN 2639 #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 2640 #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 2641 #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 2642 #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb 2643 #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc 2644 #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 2645 #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 2646 #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 2647 #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 2648 #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d 2649 #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN__SHIFT 0x1e 2650 #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL 2651 #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L 2652 #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L 2653 #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L 2654 #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L 2655 #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L 2656 #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L 2657 #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L 2658 #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L 2659 #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L 2660 #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN_MASK 0x40000000L 2661 //UVD_SUVD_INT_STATUS 2662 #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 2663 #define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 2664 #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 2665 #define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb 2666 #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc 2667 #define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 2668 #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 2669 #define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 2670 #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 2671 #define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d 2672 #define UVD_SUVD_INT_STATUS__FBC_ERR_INT__SHIFT 0x1e 2673 #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL 2674 #define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L 2675 #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L 2676 #define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L 2677 #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L 2678 #define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L 2679 #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L 2680 #define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L 2681 #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L 2682 #define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L 2683 #define UVD_SUVD_INT_STATUS__FBC_ERR_INT_MASK 0x40000000L 2684 //UVD_SUVD_INT_ACK 2685 #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 2686 #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 2687 #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 2688 #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb 2689 #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc 2690 #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 2691 #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 2692 #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 2693 #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 2694 #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d 2695 #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK__SHIFT 0x1e 2696 #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL 2697 #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L 2698 #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L 2699 #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L 2700 #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L 2701 #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L 2702 #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L 2703 #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L 2704 #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L 2705 #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L 2706 #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK_MASK 0x40000000L 2707 //UVD_ENC_VCPU_INT_EN 2708 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 2709 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 2710 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 2711 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 2712 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 2713 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 2714 //UVD_ENC_VCPU_INT_STATUS 2715 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0 2716 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1 2717 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2 2718 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L 2719 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L 2720 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L 2721 //UVD_ENC_VCPU_INT_ACK 2722 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 2723 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 2724 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 2725 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 2726 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 2727 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 2728 //UVD_MASTINT_EN 2729 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 2730 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 2731 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 2732 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 2733 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 2734 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 2735 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 2736 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 2737 //UVD_SYS_INT_EN 2738 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2739 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2740 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2741 #define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 2742 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2743 #define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 2744 #define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 2745 #define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT 0xd 2746 #define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT 0xe 2747 #define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf 2748 #define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 2749 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2750 #define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 2751 #define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 2752 #define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2753 #define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2754 #define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2755 #define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 2756 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2757 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2758 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2759 #define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 2760 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2761 #define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 2762 #define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 2763 #define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN_MASK 0x00002000L 2764 #define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN_MASK 0x00004000L 2765 #define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L 2766 #define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 2767 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2768 #define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 2769 #define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 2770 #define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2771 #define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2772 #define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2773 #define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 2774 //UVD_SYS_INT_STATUS 2775 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 2776 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 2777 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 2778 #define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 2779 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 2780 #define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 2781 #define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 2782 #define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT__SHIFT 0xd 2783 #define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0xe 2784 #define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf 2785 #define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 2786 #define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 2787 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 2788 #define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 2789 #define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 2790 #define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 2791 #define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 2792 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 2793 #define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 2794 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 2795 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 2796 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 2797 #define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 2798 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 2799 #define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 2800 #define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 2801 #define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT_MASK 0x00002000L 2802 #define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00004000L 2803 #define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L 2804 #define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 2805 #define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 2806 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 2807 #define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 2808 #define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 2809 #define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 2810 #define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 2811 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 2812 #define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 2813 //UVD_SYS_INT_ACK 2814 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2815 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2816 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2817 #define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 2818 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2819 #define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 2820 #define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 2821 #define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT 0xd 2822 #define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT 0xe 2823 #define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf 2824 #define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 2825 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2826 #define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 2827 #define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 2828 #define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2829 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2830 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2831 #define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 2832 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2833 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2834 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2835 #define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 2836 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2837 #define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 2838 #define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 2839 #define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK_MASK 0x00002000L 2840 #define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK_MASK 0x00004000L 2841 #define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L 2842 #define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 2843 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2844 #define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 2845 #define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 2846 #define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2847 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2848 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2849 #define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 2850 //UVD_JOB_DONE 2851 #define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 2852 #define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 2853 //UVD_CBUF_ID 2854 #define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 2855 #define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 2856 //UVD_CONTEXT_ID 2857 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 2858 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 2859 //UVD_CONTEXT_ID2 2860 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 2861 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 2862 //UVD_NO_OP 2863 #define UVD_NO_OP__NO_OP__SHIFT 0x0 2864 #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 2865 //UVD_RB_BASE_LO 2866 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 2867 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 2868 //UVD_RB_BASE_HI 2869 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 2870 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 2871 //UVD_RB_SIZE 2872 #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 2873 #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 2874 //UVD_RB_BASE_LO2 2875 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 2876 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 2877 //UVD_RB_BASE_HI2 2878 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 2879 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 2880 //UVD_RB_SIZE2 2881 #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 2882 #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 2883 //UVD_RB_BASE_LO3 2884 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 2885 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 2886 //UVD_RB_BASE_HI3 2887 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 2888 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 2889 //UVD_RB_SIZE3 2890 #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 2891 #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 2892 //UVD_RB_BASE_LO4 2893 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 2894 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 2895 //UVD_RB_BASE_HI4 2896 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 2897 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 2898 //UVD_RB_SIZE4 2899 #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 2900 #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 2901 //UVD_OUT_RB_BASE_LO 2902 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 2903 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 2904 //UVD_OUT_RB_BASE_HI 2905 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 2906 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 2907 //UVD_OUT_RB_SIZE 2908 #define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 2909 #define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 2910 //UVD_IOV_ACTIVE_FCN_ID 2911 #define UVD_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 2912 #define UVD_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 2913 #define UVD_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000003FL 2914 #define UVD_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 2915 //UVD_IOV_MAILBOX 2916 #define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 2917 #define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL 2918 //UVD_IOV_MAILBOX_RESP 2919 #define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 2920 #define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 2921 //UVD_RB_ARB_CTRL 2922 #define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 2923 #define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 2924 #define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 2925 #define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 2926 #define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 2927 #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 2928 #define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 2929 #define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 2930 #define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 2931 #define UVD_RB_ARB_CTRL__UVD_RB_DBG_EN__SHIFT 0x9 2932 #define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 2933 #define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 2934 #define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 2935 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 2936 #define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 2937 #define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 2938 #define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 2939 #define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 2940 #define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 2941 #define UVD_RB_ARB_CTRL__UVD_RB_DBG_EN_MASK 0x00000200L 2942 //UVD_CTX_INDEX 2943 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 2944 #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 2945 //UVD_CTX_DATA 2946 #define UVD_CTX_DATA__DATA__SHIFT 0x0 2947 #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 2948 //UVD_CXW_WR 2949 #define UVD_CXW_WR__DAT__SHIFT 0x0 2950 #define UVD_CXW_WR__STAT__SHIFT 0x1f 2951 #define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 2952 #define UVD_CXW_WR__STAT_MASK 0x80000000L 2953 //UVD_CXW_WR_INT_ID 2954 #define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 2955 #define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 2956 //UVD_CXW_WR_INT_CTX_ID 2957 #define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 2958 #define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 2959 //UVD_CXW_INT_ID 2960 #define UVD_CXW_INT_ID__ID__SHIFT 0x0 2961 #define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 2962 //UVD_MPEG2_ERROR 2963 #define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 2964 #define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL 2965 //UVD_YBASE 2966 #define UVD_YBASE__DUM__SHIFT 0x0 2967 #define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 2968 //UVD_UVBASE 2969 #define UVD_UVBASE__DUM__SHIFT 0x0 2970 #define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 2971 //UVD_PITCH 2972 #define UVD_PITCH__DUM__SHIFT 0x0 2973 #define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 2974 //UVD_WIDTH 2975 #define UVD_WIDTH__DUM__SHIFT 0x0 2976 #define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 2977 //UVD_HEIGHT 2978 #define UVD_HEIGHT__DUM__SHIFT 0x0 2979 #define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 2980 //UVD_PICCOUNT 2981 #define UVD_PICCOUNT__DUM__SHIFT 0x0 2982 #define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 2983 //UVD_MPRD_INITIAL_XY 2984 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 2985 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 2986 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL 2987 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L 2988 //UVD_MPEG2_CTRL 2989 #define UVD_MPEG2_CTRL__EN__SHIFT 0x0 2990 #define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 2991 #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 2992 #define UVD_MPEG2_CTRL__EN_MASK 0x00000001L 2993 #define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L 2994 #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L 2995 //UVD_MB_CTL_BUF_BASE 2996 #define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 2997 #define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 2998 //UVD_PIC_CTL_BUF_BASE 2999 #define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 3000 #define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 3001 //UVD_DXVA_BUF_SIZE 3002 #define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 3003 #define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 3004 #define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL 3005 #define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L 3006 //UVD_SCRATCH_NP 3007 #define UVD_SCRATCH_NP__DATA__SHIFT 0x0 3008 #define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 3009 //UVD_CLK_SWT_HANDSHAKE 3010 #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 3011 #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 3012 #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L 3013 #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L 3014 //UVD_GP_SCRATCH0 3015 #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 3016 #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 3017 //UVD_GP_SCRATCH1 3018 #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 3019 #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 3020 //UVD_GP_SCRATCH2 3021 #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 3022 #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 3023 //UVD_GP_SCRATCH3 3024 #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 3025 #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 3026 //UVD_GP_SCRATCH4 3027 #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 3028 #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 3029 //UVD_GP_SCRATCH5 3030 #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 3031 #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 3032 //UVD_GP_SCRATCH6 3033 #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 3034 #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 3035 //UVD_GP_SCRATCH7 3036 #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 3037 #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 3038 //UVD_GP_SCRATCH8 3039 #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 3040 #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 3041 //UVD_GP_SCRATCH9 3042 #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 3043 #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 3044 //UVD_GP_SCRATCH10 3045 #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 3046 #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 3047 //UVD_GP_SCRATCH11 3048 #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 3049 #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 3050 //UVD_GP_SCRATCH12 3051 #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 3052 #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 3053 //UVD_GP_SCRATCH13 3054 #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 3055 #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 3056 //UVD_GP_SCRATCH14 3057 #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 3058 #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 3059 //UVD_GP_SCRATCH15 3060 #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 3061 #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 3062 //UVD_GP_SCRATCH16 3063 #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 3064 #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 3065 //UVD_GP_SCRATCH17 3066 #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 3067 #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 3068 //UVD_GP_SCRATCH18 3069 #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 3070 #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 3071 //UVD_GP_SCRATCH19 3072 #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 3073 #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 3074 //UVD_GP_SCRATCH20 3075 #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 3076 #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 3077 //UVD_GP_SCRATCH21 3078 #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 3079 #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 3080 //UVD_GP_SCRATCH22 3081 #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 3082 #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 3083 //UVD_GP_SCRATCH23 3084 #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 3085 #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 3086 //UVD_AUDIO_RB_BASE_LO 3087 #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3088 #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3089 //UVD_AUDIO_RB_BASE_HI 3090 #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3091 #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3092 //UVD_AUDIO_RB_SIZE 3093 #define UVD_AUDIO_RB_SIZE__RB_SIZE__SHIFT 0x4 3094 #define UVD_AUDIO_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3095 //UVD_VCPU_INT_STATUS2 3096 #define UVD_VCPU_INT_STATUS2__SW_RB6_INT__SHIFT 0x0 3097 #define UVD_VCPU_INT_STATUS2__SW_RB6_INT_MASK 0x00000001L 3098 //UVD_VCPU_INT_ACK2 3099 #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK__SHIFT 0x0 3100 #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK_MASK 0x00000001L 3101 //UVD_VCPU_INT_EN2 3102 #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN__SHIFT 0x0 3103 #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN_MASK 0x00000001L 3104 //UVD_SUVD_CGC_STATUS2 3105 #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK__SHIFT 0x0 3106 #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK__SHIFT 0x1 3107 #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK__SHIFT 0x3 3108 #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK__SHIFT 0x4 3109 #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK__SHIFT 0x5 3110 #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK__SHIFT 0x6 3111 #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK__SHIFT 0x7 3112 #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK__SHIFT 0x8 3113 #define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK__SHIFT 0x9 3114 #define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK__SHIFT 0xa 3115 #define UVD_SUVD_CGC_STATUS2__SIT0_DCLK__SHIFT 0xb 3116 #define UVD_SUVD_CGC_STATUS2__SIT1_DCLK__SHIFT 0xc 3117 #define UVD_SUVD_CGC_STATUS2__SIT2_DCLK__SHIFT 0xd 3118 #define UVD_SUVD_CGC_STATUS2__FBC_PCLK__SHIFT 0x1c 3119 #define UVD_SUVD_CGC_STATUS2__FBC_CCLK__SHIFT 0x1d 3120 #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK_MASK 0x00000001L 3121 #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK_MASK 0x00000002L 3122 #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK_MASK 0x00000008L 3123 #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK_MASK 0x00000010L 3124 #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK_MASK 0x00000020L 3125 #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK_MASK 0x00000040L 3126 #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK_MASK 0x00000080L 3127 #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK_MASK 0x00000100L 3128 #define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK_MASK 0x00000200L 3129 #define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK_MASK 0x00000400L 3130 #define UVD_SUVD_CGC_STATUS2__SIT0_DCLK_MASK 0x00000800L 3131 #define UVD_SUVD_CGC_STATUS2__SIT1_DCLK_MASK 0x00001000L 3132 #define UVD_SUVD_CGC_STATUS2__SIT2_DCLK_MASK 0x00002000L 3133 #define UVD_SUVD_CGC_STATUS2__FBC_PCLK_MASK 0x10000000L 3134 #define UVD_SUVD_CGC_STATUS2__FBC_CCLK_MASK 0x20000000L 3135 //UVD_SUVD_INT_STATUS2 3136 #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT__SHIFT 0x0 3137 #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT__SHIFT 0x5 3138 #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT__SHIFT 0x6 3139 #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT__SHIFT 0xb 3140 #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT_MASK 0x0000001FL 3141 #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT_MASK 0x00000020L 3142 #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT_MASK 0x000007C0L 3143 #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT_MASK 0x00000800L 3144 //UVD_SUVD_INT_EN2 3145 #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN__SHIFT 0x0 3146 #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN__SHIFT 0x5 3147 #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN__SHIFT 0x6 3148 #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN__SHIFT 0xb 3149 #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN_MASK 0x0000001FL 3150 #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN_MASK 0x00000020L 3151 #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN_MASK 0x000007C0L 3152 #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN_MASK 0x00000800L 3153 //UVD_SUVD_INT_ACK2 3154 #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK__SHIFT 0x0 3155 #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK__SHIFT 0x5 3156 #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK__SHIFT 0x6 3157 #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK__SHIFT 0xb 3158 #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK_MASK 0x0000001FL 3159 #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK_MASK 0x00000020L 3160 #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK_MASK 0x000007C0L 3161 #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK_MASK 0x00000800L 3162 //UVD_STATUS 3163 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 3164 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 3165 #define UVD_STATUS__FILL_0__SHIFT 0x8 3166 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 3167 #define UVD_STATUS__DRM_BUSY__SHIFT 0x11 3168 #define UVD_STATUS__FILL_1__SHIFT 0x12 3169 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 3170 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 3171 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 3172 #define UVD_STATUS__FILL_0_MASK 0x0000FF00L 3173 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 3174 #define UVD_STATUS__DRM_BUSY_MASK 0x00020000L 3175 #define UVD_STATUS__FILL_1_MASK 0x7FFC0000L 3176 #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 3177 //UVD_ENC_PIPE_BUSY 3178 #define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3179 #define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3180 #define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3181 #define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3182 #define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3183 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3184 #define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3185 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3186 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3187 #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 3188 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3189 #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 3190 #define UVD_ENC_PIPE_BUSY__EFC_BUSY__SHIFT 0xc 3191 #define UVD_ENC_PIPE_BUSY__MDM_PPU_BUSY__SHIFT 0xd 3192 #define UVD_ENC_PIPE_BUSY__MIF_AUTODMA_BUSY__SHIFT 0xe 3193 #define UVD_ENC_PIPE_BUSY__CDEFE_BUSY__SHIFT 0xf 3194 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3195 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3196 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3197 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3198 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3199 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3200 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3201 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3202 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3203 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3204 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3205 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3206 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3207 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 3208 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 3209 #define UVD_ENC_PIPE_BUSY__SAOE_BUSY__SHIFT 0x1f 3210 #define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3211 #define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3212 #define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3213 #define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3214 #define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3215 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3216 #define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3217 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3218 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3219 #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 3220 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3221 #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 3222 #define UVD_ENC_PIPE_BUSY__EFC_BUSY_MASK 0x00001000L 3223 #define UVD_ENC_PIPE_BUSY__MDM_PPU_BUSY_MASK 0x00002000L 3224 #define UVD_ENC_PIPE_BUSY__MIF_AUTODMA_BUSY_MASK 0x00004000L 3225 #define UVD_ENC_PIPE_BUSY__CDEFE_BUSY_MASK 0x00008000L 3226 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3227 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3228 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3229 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3230 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3231 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3232 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3233 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3234 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3235 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3236 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3237 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3238 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3239 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 3240 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 3241 #define UVD_ENC_PIPE_BUSY__SAOE_BUSY_MASK 0x80000000L 3242 //UVD_FW_POWER_STATUS 3243 #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0 3244 #define UVD_FW_POWER_STATUS__UVDTC_PWR_OFF__SHIFT 0x1 3245 #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2 3246 #define UVD_FW_POWER_STATUS__UVDTA_PWR_OFF__SHIFT 0x3 3247 #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x4 3248 #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x5 3249 #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x6 3250 #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF__SHIFT 0x7 3251 #define UVD_FW_POWER_STATUS__UVDTB_PWR_OFF__SHIFT 0x8 3252 #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF__SHIFT 0x9 3253 #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF__SHIFT 0xa 3254 #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L 3255 #define UVD_FW_POWER_STATUS__UVDTC_PWR_OFF_MASK 0x00000002L 3256 #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L 3257 #define UVD_FW_POWER_STATUS__UVDTA_PWR_OFF_MASK 0x00000008L 3258 #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000010L 3259 #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000020L 3260 #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000040L 3261 #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF_MASK 0x00000080L 3262 #define UVD_FW_POWER_STATUS__UVDTB_PWR_OFF_MASK 0x00000100L 3263 #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF_MASK 0x00000200L 3264 #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF_MASK 0x00000400L 3265 //UVD_CNTL 3266 #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 3267 #define UVD_CNTL__SUVD_EN__SHIFT 0x13 3268 #define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c 3269 #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f 3270 #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 3271 #define UVD_CNTL__SUVD_EN_MASK 0x00080000L 3272 #define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L 3273 #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L 3274 //UVD_SOFT_RESET 3275 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 3276 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 3277 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 3278 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 3279 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 3280 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 3281 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 3282 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 3283 #define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 3284 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 3285 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 3286 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 3287 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 3288 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 3289 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 3290 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 3291 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 3292 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 3293 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 3294 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 3295 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 3296 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 3297 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 3298 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 3299 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 3300 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 3301 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 3302 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 3303 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 3304 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 3305 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 3306 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 3307 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 3308 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 3309 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 3310 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 3311 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 3312 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 3313 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 3314 #define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 3315 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 3316 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 3317 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 3318 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 3319 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 3320 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 3321 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 3322 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 3323 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 3324 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 3325 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 3326 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 3327 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 3328 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 3329 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 3330 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 3331 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 3332 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 3333 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 3334 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 3335 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 3336 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 3337 //UVD_SOFT_RESET2 3338 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 3339 #define UVD_SOFT_RESET2__PPU_SOFT_RESET__SHIFT 0x1 3340 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 3341 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 3342 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 3343 #define UVD_SOFT_RESET2__PPU_SOFT_RESET_MASK 0x00000002L 3344 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 3345 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 3346 //UVD_MMSCH_SOFT_RESET 3347 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 3348 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 3349 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 3350 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 3351 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 3352 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 3353 //UVD_WIG_CTRL 3354 #define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 3355 #define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 3356 #define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 3357 #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 3358 #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 3359 #define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L 3360 #define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L 3361 #define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L 3362 #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L 3363 #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L 3364 //UVD_CGC_STATUS 3365 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 3366 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 3367 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 3368 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 3369 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 3370 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 3371 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 3372 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 3373 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 3374 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 3375 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 3376 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 3377 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 3378 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 3379 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 3380 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 3381 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 3382 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 3383 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 3384 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 3385 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 3386 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 3387 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 3388 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 3389 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 3390 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 3391 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 3392 #define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 3393 #define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 3394 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 3395 #define UVD_CGC_STATUS__LRBBM_DCLK__SHIFT 0x1e 3396 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 3397 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 3398 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 3399 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 3400 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 3401 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 3402 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 3403 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 3404 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 3405 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 3406 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 3407 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 3408 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 3409 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 3410 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 3411 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 3412 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 3413 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 3414 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 3415 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 3416 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 3417 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 3418 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 3419 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 3420 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 3421 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 3422 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 3423 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 3424 #define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 3425 #define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 3426 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 3427 #define UVD_CGC_STATUS__LRBBM_DCLK_MASK 0x40000000L 3428 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 3429 //UVD_CGC_UDEC_STATUS 3430 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 3431 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 3432 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 3433 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 3434 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 3435 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 3436 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 3437 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 3438 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 3439 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 3440 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 3441 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 3442 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 3443 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 3444 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 3445 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 3446 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 3447 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 3448 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 3449 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 3450 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 3451 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 3452 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 3453 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 3454 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 3455 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 3456 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 3457 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 3458 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 3459 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 3460 //UVD_SUVD_CGC_STATUS 3461 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 3462 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 3463 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 3464 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 3465 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 3466 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 3467 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 3468 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 3469 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 3470 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 3471 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 3472 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 3473 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 3474 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 3475 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 3476 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 3477 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 3478 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 3479 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 3480 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 3481 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 3482 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 3483 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 3484 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 3485 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 3486 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 3487 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 3488 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 3489 #define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 3490 #define UVD_SUVD_CGC_STATUS__SAOE_DCLK__SHIFT 0x1d 3491 #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK__SHIFT 0x1e 3492 #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK__SHIFT 0x1f 3493 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 3494 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 3495 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 3496 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 3497 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 3498 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 3499 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 3500 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 3501 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 3502 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 3503 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 3504 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 3505 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 3506 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 3507 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 3508 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 3509 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 3510 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 3511 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 3512 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 3513 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 3514 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 3515 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 3516 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 3517 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 3518 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 3519 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 3520 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 3521 #define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 3522 #define UVD_SUVD_CGC_STATUS__SAOE_DCLK_MASK 0x20000000L 3523 #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK_MASK 0x40000000L 3524 #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK_MASK 0x80000000L 3525 //UVD_GPCOM_VCPU_CMD 3526 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 3527 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 3528 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 3529 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 3530 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 3531 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 3532 3533 3534 // addressBlock: uvd_vcn_cdefe_cdefe_broadcast_dec0 3535 //CDEFE_SUVD_CGC_GATE 3536 #define CDEFE_SUVD_CGC_GATE__SRE__SHIFT 0x0 3537 #define CDEFE_SUVD_CGC_GATE__SIT__SHIFT 0x1 3538 #define CDEFE_SUVD_CGC_GATE__SMP__SHIFT 0x2 3539 #define CDEFE_SUVD_CGC_GATE__SCM__SHIFT 0x3 3540 #define CDEFE_SUVD_CGC_GATE__SDB__SHIFT 0x4 3541 #define CDEFE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 3542 #define CDEFE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 3543 #define CDEFE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 3544 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 3545 #define CDEFE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 3546 #define CDEFE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 3547 #define CDEFE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 3548 #define CDEFE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 3549 #define CDEFE_SUVD_CGC_GATE__SCLR__SHIFT 0xd 3550 #define CDEFE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 3551 #define CDEFE_SUVD_CGC_GATE__ENT__SHIFT 0xf 3552 #define CDEFE_SUVD_CGC_GATE__IME__SHIFT 0x10 3553 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 3554 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 3555 #define CDEFE_SUVD_CGC_GATE__SITE__SHIFT 0x13 3556 #define CDEFE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 3557 #define CDEFE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 3558 #define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 3559 #define CDEFE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 3560 #define CDEFE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 3561 #define CDEFE_SUVD_CGC_GATE__EFC__SHIFT 0x19 3562 #define CDEFE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 3563 #define CDEFE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 3564 #define CDEFE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 3565 #define CDEFE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 3566 #define CDEFE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 3567 #define CDEFE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 3568 #define CDEFE_SUVD_CGC_GATE__SRE_MASK 0x00000001L 3569 #define CDEFE_SUVD_CGC_GATE__SIT_MASK 0x00000002L 3570 #define CDEFE_SUVD_CGC_GATE__SMP_MASK 0x00000004L 3571 #define CDEFE_SUVD_CGC_GATE__SCM_MASK 0x00000008L 3572 #define CDEFE_SUVD_CGC_GATE__SDB_MASK 0x00000010L 3573 #define CDEFE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 3574 #define CDEFE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 3575 #define CDEFE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 3576 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 3577 #define CDEFE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 3578 #define CDEFE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 3579 #define CDEFE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 3580 #define CDEFE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 3581 #define CDEFE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 3582 #define CDEFE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 3583 #define CDEFE_SUVD_CGC_GATE__ENT_MASK 0x00008000L 3584 #define CDEFE_SUVD_CGC_GATE__IME_MASK 0x00010000L 3585 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 3586 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 3587 #define CDEFE_SUVD_CGC_GATE__SITE_MASK 0x00080000L 3588 #define CDEFE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 3589 #define CDEFE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 3590 #define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 3591 #define CDEFE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 3592 #define CDEFE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 3593 #define CDEFE_SUVD_CGC_GATE__EFC_MASK 0x02000000L 3594 #define CDEFE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 3595 #define CDEFE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 3596 #define CDEFE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 3597 #define CDEFE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 3598 #define CDEFE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 3599 #define CDEFE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 3600 //CDEFE_SUVD_CGC_GATE2 3601 #define CDEFE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 3602 #define CDEFE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 3603 #define CDEFE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 3604 #define CDEFE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 3605 #define CDEFE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 3606 #define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 3607 #define CDEFE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 3608 #define CDEFE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 3609 #define CDEFE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 3610 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 3611 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 3612 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 3613 #define CDEFE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 3614 #define CDEFE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 3615 #define CDEFE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 3616 #define CDEFE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 3617 #define CDEFE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 3618 #define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 3619 #define CDEFE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 3620 #define CDEFE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 3621 #define CDEFE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 3622 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 3623 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 3624 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 3625 //CDEFE_SUVD_CGC_CTRL 3626 #define CDEFE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 3627 #define CDEFE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 3628 #define CDEFE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 3629 #define CDEFE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 3630 #define CDEFE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 3631 #define CDEFE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 3632 #define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 3633 #define CDEFE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 3634 #define CDEFE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 3635 #define CDEFE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 3636 #define CDEFE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 3637 #define CDEFE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 3638 #define CDEFE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 3639 #define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 3640 #define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 3641 #define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 3642 #define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 3643 #define CDEFE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 3644 #define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 3645 #define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 3646 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 3647 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 3648 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 3649 #define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 3650 #define CDEFE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 3651 #define CDEFE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 3652 #define CDEFE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 3653 #define CDEFE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 3654 #define CDEFE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 3655 #define CDEFE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 3656 #define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 3657 #define CDEFE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 3658 #define CDEFE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 3659 #define CDEFE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 3660 #define CDEFE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 3661 #define CDEFE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 3662 #define CDEFE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 3663 #define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 3664 #define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 3665 #define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 3666 #define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 3667 #define CDEFE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 3668 #define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 3669 #define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 3670 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 3671 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 3672 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 3673 #define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 3674 3675 3676 // addressBlock: uvd_ecpudec 3677 //UVD_VCPU_CACHE_OFFSET0 3678 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 3679 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 3680 //UVD_VCPU_CACHE_SIZE0 3681 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 3682 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 3683 //UVD_VCPU_CACHE_OFFSET1 3684 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 3685 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 3686 //UVD_VCPU_CACHE_SIZE1 3687 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 3688 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 3689 //UVD_VCPU_CACHE_OFFSET2 3690 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 3691 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 3692 //UVD_VCPU_CACHE_SIZE2 3693 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 3694 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 3695 //UVD_VCPU_CACHE_OFFSET3 3696 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 3697 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 3698 //UVD_VCPU_CACHE_SIZE3 3699 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 3700 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 3701 //UVD_VCPU_CACHE_OFFSET4 3702 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 3703 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 3704 //UVD_VCPU_CACHE_SIZE4 3705 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 3706 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 3707 //UVD_VCPU_CACHE_OFFSET5 3708 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 3709 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 3710 //UVD_VCPU_CACHE_SIZE5 3711 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 3712 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 3713 //UVD_VCPU_CACHE_OFFSET6 3714 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 3715 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 3716 //UVD_VCPU_CACHE_SIZE6 3717 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 3718 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 3719 //UVD_VCPU_CACHE_OFFSET7 3720 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 3721 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 3722 //UVD_VCPU_CACHE_SIZE7 3723 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 3724 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 3725 //UVD_VCPU_CACHE_OFFSET8 3726 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 3727 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 3728 //UVD_VCPU_CACHE_SIZE8 3729 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 3730 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 3731 //UVD_VCPU_NONCACHE_OFFSET0 3732 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 3733 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 3734 //UVD_VCPU_NONCACHE_SIZE0 3735 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 3736 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 3737 //UVD_VCPU_NONCACHE_OFFSET1 3738 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 3739 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 3740 //UVD_VCPU_NONCACHE_SIZE1 3741 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 3742 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 3743 //UVD_VCPU_CNTL 3744 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 3745 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 3746 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 3747 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 3748 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 3749 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 3750 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 3751 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 3752 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 3753 #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 3754 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 3755 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 3756 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 3757 #define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c 3758 #define UVD_VCPU_CNTL__RUNSTALL__SHIFT 0x1d 3759 #define UVD_VCPU_CNTL__SRE_CMDIF_DRST__SHIFT 0x1e 3760 #define UVD_VCPU_CNTL__SRE_CMDIF_VRST__SHIFT 0x1f 3761 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 3762 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x00000010L 3763 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 3764 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 3765 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 3766 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 3767 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 3768 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 3769 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 3770 #define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000E000L 3771 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 3772 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 3773 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 3774 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L 3775 #define UVD_VCPU_CNTL__RUNSTALL_MASK 0x20000000L 3776 #define UVD_VCPU_CNTL__SRE_CMDIF_DRST_MASK 0x40000000L 3777 #define UVD_VCPU_CNTL__SRE_CMDIF_VRST_MASK 0x80000000L 3778 //UVD_VCPU_PRID 3779 #define UVD_VCPU_PRID__PRID__SHIFT 0x0 3780 #define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 3781 //UVD_VCPU_TRCE 3782 #define UVD_VCPU_TRCE__PC__SHIFT 0x0 3783 #define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 3784 //UVD_VCPU_TRCE_RD 3785 #define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 3786 #define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 3787 //UVD_VCPU_IND_INDEX 3788 #define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 3789 #define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL 3790 //UVD_VCPU_IND_DATA 3791 #define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 3792 #define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL 3793 3794 3795 // addressBlock: uvd_lmi_adpdec 3796 //UVD_LMI_RE_64BIT_BAR_LOW 3797 #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3798 #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3799 //UVD_LMI_RE_64BIT_BAR_HIGH 3800 #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3801 #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3802 //UVD_LMI_IT_64BIT_BAR_LOW 3803 #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3804 #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3805 //UVD_LMI_IT_64BIT_BAR_HIGH 3806 #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3807 #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3808 //UVD_LMI_MP_64BIT_BAR_LOW 3809 #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3810 #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3811 //UVD_LMI_MP_64BIT_BAR_HIGH 3812 #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3813 #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3814 //UVD_LMI_CM_64BIT_BAR_LOW 3815 #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3816 #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3817 //UVD_LMI_CM_64BIT_BAR_HIGH 3818 #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3819 #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3820 //UVD_LMI_DB_64BIT_BAR_LOW 3821 #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3822 #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3823 //UVD_LMI_DB_64BIT_BAR_HIGH 3824 #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3825 #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3826 //UVD_LMI_DBW_64BIT_BAR_LOW 3827 #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3828 #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3829 //UVD_LMI_DBW_64BIT_BAR_HIGH 3830 #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3831 #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3832 //UVD_LMI_IDCT_64BIT_BAR_LOW 3833 #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3834 #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3835 //UVD_LMI_IDCT_64BIT_BAR_HIGH 3836 #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3837 #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3838 //UVD_LMI_MPRD_S0_64BIT_BAR_LOW 3839 #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3840 #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3841 //UVD_LMI_MPRD_S0_64BIT_BAR_HIGH 3842 #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3843 #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3844 //UVD_LMI_MPRD_S1_64BIT_BAR_LOW 3845 #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3846 #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3847 //UVD_LMI_MPRD_S1_64BIT_BAR_HIGH 3848 #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3849 #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3850 //UVD_LMI_MPRD_DBW_64BIT_BAR_LOW 3851 #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3852 #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3853 //UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 3854 #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3855 #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3856 //UVD_LMI_RBC_RB_64BIT_BAR_LOW 3857 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3858 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3859 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 3860 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3861 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3862 //UVD_LMI_RBC_IB_64BIT_BAR_LOW 3863 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3864 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3865 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 3866 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3867 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3868 //UVD_LMI_LBSI_64BIT_BAR_LOW 3869 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3870 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3871 //UVD_LMI_LBSI_64BIT_BAR_HIGH 3872 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3873 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3874 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 3875 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3876 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3877 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 3878 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3879 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3880 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 3881 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3882 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3883 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 3884 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3885 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3886 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 3887 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3888 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3889 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 3890 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3891 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3892 //UVD_LMI_CENC_64BIT_BAR_LOW 3893 #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3894 #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3895 //UVD_LMI_CENC_64BIT_BAR_HIGH 3896 #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3897 #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3898 //UVD_LMI_SRE_64BIT_BAR_LOW 3899 #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3900 #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3901 //UVD_LMI_SRE_64BIT_BAR_HIGH 3902 #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3903 #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3904 //UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 3905 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3906 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3907 //UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 3908 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3909 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3910 //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 3911 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3912 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3913 //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 3914 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3915 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3916 //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 3917 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3918 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3919 //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 3920 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3921 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3922 //UVD_LMI_MIF_DBW_64BIT_BAR_LOW 3923 #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3924 #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3925 //UVD_LMI_MIF_DBW_64BIT_BAR_HIGH 3926 #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3927 #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3928 //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 3929 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3930 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3931 //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 3932 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3933 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3934 //UVD_LMI_MIF_BSP0_64BIT_BAR_LOW 3935 #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3936 #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3937 //UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 3938 #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3939 #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3940 //UVD_LMI_MIF_BSP1_64BIT_BAR_LOW 3941 #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3942 #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3943 //UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 3944 #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3945 #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3946 //UVD_LMI_MIF_BSP2_64BIT_BAR_LOW 3947 #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3948 #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3949 //UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 3950 #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3951 #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3952 //UVD_LMI_MIF_BSP3_64BIT_BAR_LOW 3953 #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3954 #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3955 //UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 3956 #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3957 #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3958 //UVD_LMI_MIF_BSD0_64BIT_BAR_LOW 3959 #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3960 #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3961 //UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 3962 #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3963 #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3964 //UVD_LMI_MIF_BSD1_64BIT_BAR_LOW 3965 #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3966 #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3967 //UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 3968 #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3969 #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3970 //UVD_LMI_MIF_BSD2_64BIT_BAR_LOW 3971 #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3972 #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3973 //UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 3974 #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3975 #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3976 //UVD_LMI_MIF_BSD3_64BIT_BAR_LOW 3977 #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3978 #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3979 //UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 3980 #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3981 #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3982 //UVD_LMI_MIF_BSD4_64BIT_BAR_LOW 3983 #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3984 #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3985 //UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 3986 #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3987 #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3988 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 3989 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3990 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3991 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 3992 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3993 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3994 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 3995 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3996 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3997 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 3998 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3999 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4000 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 4001 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4002 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4003 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 4004 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4005 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4006 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 4007 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4008 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4009 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 4010 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4011 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4012 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 4013 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4014 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4015 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 4016 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4017 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4018 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 4019 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4020 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4021 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 4022 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4023 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4024 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 4025 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4026 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4027 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 4028 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4029 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4030 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 4031 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4032 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4033 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 4034 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4035 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4036 //UVD_LMI_MIF_SCLR_64BIT_BAR_LOW 4037 #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4038 #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4039 //UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 4040 #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4041 #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4042 //UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 4043 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4044 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4045 //UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 4046 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4047 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4048 //UVD_LMI_SPH_64BIT_BAR_HIGH 4049 #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4050 #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4051 //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 4052 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4053 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4054 //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 4055 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4056 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4057 //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 4058 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4059 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4060 //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 4061 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4062 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4063 //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 4064 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4065 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4066 //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 4067 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4068 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4069 //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 4070 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4071 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4072 //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 4073 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4074 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4075 //UVD_ADP_ATOMIC_CONFIG 4076 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0 4077 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4 4078 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8 4079 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc 4080 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10 4081 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL 4082 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L 4083 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L 4084 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L 4085 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L 4086 //UVD_LMI_ARB_CTRL2 4087 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 4088 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 4089 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 4090 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 4091 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 4092 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 4093 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 4094 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 4095 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 4096 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 4097 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 4098 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 4099 //UVD_LMI_VCPU_CACHE_VMIDS_MULTI 4100 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 4101 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 4102 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 4103 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 4104 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 4105 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 4106 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 4107 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 4108 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 4109 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 4110 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 4111 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 4112 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 4113 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 4114 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 4115 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 4116 //UVD_LMI_VCPU_NC_VMIDS_MULTI 4117 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 4118 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 4119 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 4120 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 4121 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 4122 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 4123 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 4124 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 4125 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 4126 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 4127 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 4128 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 4129 //UVD_LMI_LAT_CTRL 4130 #define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 4131 #define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 4132 #define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 4133 #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 4134 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 4135 #define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 4136 #define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 4137 #define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 4138 #define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 4139 #define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 4140 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 4141 #define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 4142 //UVD_LMI_LAT_CNTR 4143 #define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 4144 #define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 4145 #define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 4146 #define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 4147 //UVD_LMI_AVG_LAT_CNTR 4148 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 4149 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 4150 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 4151 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 4152 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 4153 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 4154 //UVD_LMI_SPH 4155 #define UVD_LMI_SPH__ADDR__SHIFT 0x0 4156 #define UVD_LMI_SPH__STS__SHIFT 0x1c 4157 #define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 4158 #define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 4159 #define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 4160 #define UVD_LMI_SPH__STS_MASK 0x30000000L 4161 #define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 4162 #define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 4163 //UVD_LMI_VCPU_CACHE_VMID 4164 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 4165 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 4166 //UVD_LMI_CTRL2 4167 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 4168 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 4169 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 4170 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 4171 #define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 4172 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 4173 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 4174 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 4175 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 4176 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 4177 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 4178 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 4179 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 4180 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 4181 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 4182 #define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 4183 #define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 4184 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 4185 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 4186 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 4187 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 4188 #define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 4189 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 4190 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 4191 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 4192 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 4193 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 4194 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 4195 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 4196 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 4197 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 4198 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 4199 #define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 4200 #define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 4201 //UVD_LMI_URGENT_CTRL 4202 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 4203 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 4204 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 4205 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 4206 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 4207 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 4208 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 4209 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 4210 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 4211 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 4212 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 4213 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 4214 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 4215 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 4216 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 4217 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 4218 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 4219 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 4220 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 4221 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 4222 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 4223 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 4224 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 4225 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 4226 //UVD_LMI_CTRL 4227 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 4228 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 4229 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 4230 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 4231 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 4232 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 4233 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 4234 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 4235 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 4236 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 4237 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 4238 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 4239 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 4240 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 4241 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 4242 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 4243 #define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c 4244 #define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d 4245 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 4246 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 4247 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 4248 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 4249 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 4250 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 4251 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 4252 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 4253 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L 4254 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 4255 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 4256 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 4257 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 4258 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 4259 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 4260 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 4261 #define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L 4262 #define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L 4263 //UVD_LMI_STATUS 4264 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 4265 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 4266 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 4267 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 4268 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 4269 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 4270 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 4271 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 4272 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 4273 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 4274 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 4275 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 4276 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 4277 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 4278 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 4279 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 4280 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 4281 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 4282 #define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 4283 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 4284 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 4285 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 4286 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 4287 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 4288 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 4289 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 4290 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 4291 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 4292 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 4293 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 4294 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 4295 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 4296 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 4297 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 4298 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 4299 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 4300 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 4301 #define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 4302 //UVD_LMI_PERFMON_CTRL 4303 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 4304 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 4305 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 4306 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 4307 //UVD_LMI_PERFMON_COUNT_LO 4308 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 4309 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 4310 //UVD_LMI_PERFMON_COUNT_HI 4311 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 4312 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 4313 //UVD_LMI_ADP_SWAP_CNTL 4314 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 4315 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 4316 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 4317 #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 4318 #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 4319 #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 4320 #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 4321 #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP__SHIFT 0x14 4322 #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 4323 #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 4324 #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 4325 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 4326 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 4327 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 4328 #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 4329 #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 4330 #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 4331 #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 4332 #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP_MASK 0x00300000L 4333 #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 4334 #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 4335 #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 4336 //UVD_LMI_RBC_RB_VMID 4337 #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 4338 #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 4339 //UVD_LMI_RBC_IB_VMID 4340 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 4341 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 4342 //UVD_LMI_MC_CREDITS 4343 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 4344 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 4345 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 4346 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 4347 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 4348 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 4349 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 4350 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 4351 //UVD_LMI_ADP_IND_INDEX 4352 #define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 4353 #define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL 4354 //UVD_LMI_ADP_IND_DATA 4355 #define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 4356 #define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL 4357 //UVD_LMI_ADP_PF_EN 4358 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN__SHIFT 0x0 4359 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN__SHIFT 0x1 4360 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN__SHIFT 0x2 4361 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN_MASK 0x00000001L 4362 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN_MASK 0x00000002L 4363 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN_MASK 0x00000004L 4364 //UVD_LMI_PREF_CTRL 4365 #define UVD_LMI_PREF_CTRL__PREF_RST__SHIFT 0x0 4366 #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS__SHIFT 0x1 4367 #define UVD_LMI_PREF_CTRL__PREF_WSTRB__SHIFT 0x2 4368 #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE__SHIFT 0x3 4369 #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE__SHIFT 0x4 4370 #define UVD_LMI_PREF_CTRL__PREF_SIZE__SHIFT 0x13 4371 #define UVD_LMI_PREF_CTRL__PREF_RST_MASK 0x00000001L 4372 #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS_MASK 0x00000002L 4373 #define UVD_LMI_PREF_CTRL__PREF_WSTRB_MASK 0x00000004L 4374 #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE_MASK 0x00000008L 4375 #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE_MASK 0x00000070L 4376 #define UVD_LMI_PREF_CTRL__PREF_SIZE_MASK 0xFFF80000L 4377 4378 4379 // addressBlock: uvd_uvd_jpeg0_jpegnpdec 4380 //UVD_JPEG_CNTL 4381 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 4382 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 4383 #define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT 0x8 4384 #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 4385 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 4386 #define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK 0x00007F00L 4387 //UVD_JPEG_RB_BASE 4388 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 4389 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 4390 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 4391 #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 4392 //UVD_JPEG_RB_WPTR 4393 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 4394 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 4395 //UVD_JPEG_RB_RPTR 4396 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 4397 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 4398 //UVD_JPEG_RB_SIZE 4399 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 4400 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 4401 //UVD_JPEG_DEC_CNT 4402 #define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0 4403 #define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL 4404 //UVD_JPEG_SPS_INFO 4405 #define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 4406 #define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 4407 #define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL 4408 #define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L 4409 //UVD_JPEG_SPS1_INFO 4410 #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 4411 #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 4412 #define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 4413 #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L 4414 #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L 4415 #define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L 4416 //UVD_JPEG_RE_TIMER 4417 #define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 4418 #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 4419 #define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL 4420 #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L 4421 //UVD_JPEG_DEC_SCRATCH0 4422 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 4423 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 4424 //UVD_JPEG_INT_EN 4425 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 4426 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 4427 #define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 4428 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 4429 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 4430 #define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 4431 #define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 4432 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 4433 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 4434 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 4435 #define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 4436 #define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 4437 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 4438 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 4439 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 4440 #define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 4441 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 4442 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 4443 #define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 4444 #define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 4445 #define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 4446 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 4447 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 4448 #define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 4449 #define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 4450 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 4451 //UVD_JPEG_INT_STAT 4452 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 4453 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 4454 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 4455 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 4456 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 4457 #define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 4458 #define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 4459 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 4460 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 4461 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 4462 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 4463 #define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 4464 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 4465 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 4466 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 4467 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 4468 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 4469 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 4470 #define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 4471 #define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 4472 #define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 4473 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 4474 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 4475 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 4476 #define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 4477 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 4478 //UVD_JPEG_TIER_CNTL0 4479 #define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 4480 #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 4481 #define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 4482 #define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 4483 #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 4484 #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb 4485 #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe 4486 #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 4487 #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 4488 #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 4489 #define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a 4490 #define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c 4491 #define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e 4492 #define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L 4493 #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL 4494 #define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L 4495 #define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L 4496 #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L 4497 #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L 4498 #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L 4499 #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L 4500 #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L 4501 #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L 4502 #define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L 4503 #define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L 4504 #define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L 4505 //UVD_JPEG_TIER_CNTL1 4506 #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 4507 #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 4508 #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL 4509 #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L 4510 //UVD_JPEG_TIER_CNTL2 4511 #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 4512 #define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 4513 #define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 4514 #define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 4515 #define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 4516 #define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 4517 #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa 4518 #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe 4519 #define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 4520 #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L 4521 #define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L 4522 #define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL 4523 #define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L 4524 #define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L 4525 #define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L 4526 #define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L 4527 #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L 4528 #define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L 4529 //UVD_JPEG_TIER_STATUS 4530 #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 4531 #define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 4532 #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L 4533 #define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L 4534 4535 4536 // addressBlock: uvd_uvd_jpeg_sclk0_jpegnpsclkdec 4537 //UVD_JPEG_OUTBUF_CNTL 4538 #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 4539 #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 4540 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 4541 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 4542 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 4543 #define UVD_JPEG_OUTBUF_CNTL__DIS_OBUF_AVAIL_CHECK__SHIFT 0x10 4544 #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L 4545 #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L 4546 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L 4547 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L 4548 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L 4549 #define UVD_JPEG_OUTBUF_CNTL__DIS_OBUF_AVAIL_CHECK_MASK 0x00010000L 4550 //UVD_JPEG_OUTBUF_WPTR 4551 #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 4552 #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL 4553 //UVD_JPEG_OUTBUF_RPTR 4554 #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 4555 #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL 4556 //UVD_JPEG_PITCH 4557 #define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 4558 #define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 4559 //UVD_JPEG_UV_PITCH 4560 #define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 4561 #define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 4562 //JPEG_DEC_Y_GFX8_TILING_SURFACE 4563 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 4564 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 4565 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 4566 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 4567 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 4568 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 4569 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 4570 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 4571 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 4572 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 4573 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 4574 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 4575 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 4576 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 4577 //JPEG_DEC_UV_GFX8_TILING_SURFACE 4578 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 4579 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 4580 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 4581 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 4582 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 4583 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 4584 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 4585 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 4586 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 4587 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 4588 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 4589 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 4590 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 4591 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 4592 //JPEG_DEC_GFX8_ADDR_CONFIG 4593 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 4594 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 4595 //JPEG_DEC_Y_GFX10_TILING_SURFACE 4596 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 4597 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 4598 //JPEG_DEC_UV_GFX10_TILING_SURFACE 4599 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 4600 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 4601 //JPEG_DEC_GFX10_ADDR_CONFIG 4602 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 4603 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 4604 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 4605 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 4606 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 4607 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 4608 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 4609 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 4610 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 4611 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 4612 //JPEG_DEC_ADDR_MODE 4613 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 4614 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 4615 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 4616 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 4617 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 4618 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 4619 //UVD_JPEG_OUTPUT_XY 4620 #define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 4621 #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 4622 #define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL 4623 #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L 4624 //UVD_JPEG_GPCOM_CMD 4625 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 4626 #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 4627 //UVD_JPEG_GPCOM_DATA0 4628 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 4629 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 4630 //UVD_JPEG_GPCOM_DATA1 4631 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 4632 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 4633 //UVD_JPEG_SCRATCH1 4634 #define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 4635 #define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 4636 //UVD_JPEG_DEC_SOFT_RST 4637 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 4638 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 4639 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 4640 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 4641 4642 4643 // addressBlock: uvd_uvd_jrbc0_uvd_jrbc_dec 4644 //UVD_JRBC_RB_WPTR 4645 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 4646 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 4647 //UVD_JRBC_RB_CNTL 4648 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 4649 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 4650 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 4651 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 4652 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 4653 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 4654 //UVD_JRBC_IB_SIZE 4655 #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 4656 #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 4657 //UVD_JRBC_URGENT_CNTL 4658 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 4659 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 4660 //UVD_JRBC_RB_REF_DATA 4661 #define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 4662 #define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 4663 //UVD_JRBC_RB_COND_RD_TIMER 4664 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 4665 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 4666 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 4667 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 4668 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 4669 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 4670 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 4671 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 4672 //UVD_JRBC_SOFT_RESET 4673 #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 4674 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 4675 #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 4676 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 4677 //UVD_JRBC_STATUS 4678 #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 4679 #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 4680 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 4681 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 4682 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 4683 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 4684 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 4685 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 4686 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 4687 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 4688 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 4689 #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 4690 #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 4691 #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 4692 #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 4693 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 4694 #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 4695 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 4696 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 4697 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 4698 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 4699 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 4700 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 4701 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 4702 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 4703 #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 4704 #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 4705 #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 4706 #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 4707 #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 4708 //UVD_JRBC_RB_RPTR 4709 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 4710 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 4711 //UVD_JRBC_RB_BUF_STATUS 4712 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 4713 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 4714 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 4715 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 4716 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 4717 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 4718 //UVD_JRBC_IB_BUF_STATUS 4719 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 4720 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 4721 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 4722 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 4723 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 4724 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 4725 //UVD_JRBC_IB_SIZE_UPDATE 4726 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 4727 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 4728 //UVD_JRBC_IB_COND_RD_TIMER 4729 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 4730 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 4731 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 4732 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 4733 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 4734 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 4735 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 4736 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 4737 //UVD_JRBC_IB_REF_DATA 4738 #define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 4739 #define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 4740 //UVD_JPEG_PREEMPT_CMD 4741 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 4742 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 4743 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 4744 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 4745 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 4746 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 4747 //UVD_JPEG_PREEMPT_FENCE_DATA0 4748 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 4749 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 4750 //UVD_JPEG_PREEMPT_FENCE_DATA1 4751 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 4752 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 4753 //UVD_JRBC_RB_SIZE 4754 #define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 4755 #define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 4756 //UVD_JRBC_SCRATCH0 4757 #define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 4758 #define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 4759 4760 4761 // addressBlock: uvd_uvd_jmi0_uvd_jmi_dec 4762 //UVD_JPEG_DEC_PF_CTRL 4763 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 4764 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 4765 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 4766 #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 4767 //UVD_LMI_JRBC_CTRL 4768 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 4769 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 4770 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 4771 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 4772 #define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 4773 #define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 4774 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 4775 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 4776 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 4777 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 4778 #define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 4779 #define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 4780 //UVD_LMI_JPEG_CTRL 4781 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 4782 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 4783 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 4784 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 4785 #define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 4786 #define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 4787 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 4788 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 4789 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 4790 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 4791 #define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 4792 #define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 4793 //JPEG_LMI_DROP 4794 #define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 4795 #define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 4796 #define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 4797 #define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 4798 #define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 4799 #define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 4800 #define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 4801 #define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 4802 //UVD_LMI_JRBC_IB_VMID 4803 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 4804 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 4805 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 4806 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 4807 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 4808 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 4809 //UVD_LMI_JRBC_RB_VMID 4810 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 4811 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 4812 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 4813 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 4814 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 4815 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 4816 //UVD_LMI_JPEG_VMID 4817 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 4818 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 4819 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 4820 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 4821 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 4822 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 4823 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 4824 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4825 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4826 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 4827 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4828 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4829 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW 4830 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4831 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4832 //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 4833 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4834 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4835 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 4836 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4837 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4838 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 4839 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4840 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4841 //UVD_LMI_JPEG_PREEMPT_VMID 4842 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 4843 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 4844 //UVD_JMI_DEC_SWAP_CNTL 4845 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 4846 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 4847 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 4848 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 4849 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 4850 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 4851 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 4852 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 4853 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 4854 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 4855 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 4856 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 4857 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 4858 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 4859 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 4860 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 4861 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 4862 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 4863 //UVD_JMI_ATOMIC_CNTL 4864 #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 4865 #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 4866 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 4867 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 4868 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 4869 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 4870 #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 4871 #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 4872 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 4873 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 4874 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 4875 #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 4876 //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 4877 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4878 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4879 //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 4880 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4881 #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4882 //UVD_LMI_JPEG_READ_64BIT_BAR_LOW 4883 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4884 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4885 //UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 4886 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4887 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4888 //UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 4889 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4890 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4891 //UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 4892 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4893 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4894 //UVD_LMI_JRBC_IB_64BIT_BAR_LOW 4895 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4896 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4897 //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 4898 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4899 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4900 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 4901 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4902 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4903 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 4904 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4905 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4906 //UVD_JMI_ATOMIC_CNTL2 4907 #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 4908 #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 4909 #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 4910 #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 4911 4912 4913 // addressBlock: uvd_uvd_jmi_common_dec 4914 //UVD_JADP_MCIF_URGENT_CTRL 4915 #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 4916 #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 4917 #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb 4918 #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 4919 #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 4920 #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 4921 #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a 4922 #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL 4923 #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L 4924 #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L 4925 #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L 4926 #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L 4927 #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L 4928 #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L 4929 //UVD_JMI_URGENT_CTRL 4930 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 4931 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 4932 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 4933 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 4934 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 4935 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L 4936 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L 4937 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L 4938 //UVD_JMI_CTRL 4939 #define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 4940 #define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 4941 #define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 4942 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 4943 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 4944 #define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 4945 #define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 4946 #define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 4947 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 4948 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 4949 //JPEG_MEMCHECK_CLAMPING_CNTL 4950 #define JPEG_MEMCHECK_CLAMPING_CNTL__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x0 4951 #define JPEG_MEMCHECK_CLAMPING_CNTL__CLAMP_TO_SAFE_ADDR_EN_MASK 0x00000001L 4952 //JPEG_MEMCHECK_SAFE_ADDR 4953 #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 4954 #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL 4955 //JPEG_MEMCHECK_SAFE_ADDR_64BIT 4956 #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 4957 #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL 4958 //UVD_JMI_LAT_CTRL 4959 #define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 4960 #define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 4961 #define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 4962 #define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa 4963 #define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 4964 #define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 4965 #define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL 4966 #define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L 4967 #define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L 4968 #define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L 4969 #define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 4970 #define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L 4971 //UVD_JMI_LAT_CNTR 4972 #define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 4973 #define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 4974 #define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 4975 #define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 4976 //UVD_JMI_AVG_LAT_CNTR 4977 #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 4978 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 4979 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 4980 #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 4981 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 4982 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 4983 //UVD_JMI_PERFMON_CTRL 4984 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 4985 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 4986 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 4987 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 4988 //UVD_JMI_PERFMON_COUNT_LO 4989 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 4990 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 4991 //UVD_JMI_PERFMON_COUNT_HI 4992 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 4993 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 4994 //UVD_JMI_CLEAN_STATUS 4995 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 4996 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 4997 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 4998 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 4999 #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0x4 5000 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_READ_CLEAN__SHIFT 0x8 5001 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_WRITE_CLEAN__SHIFT 0x10 5002 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L 5003 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L 5004 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L 5005 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L 5006 #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00000010L 5007 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_READ_CLEAN_MASK 0x00000100L 5008 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_WRITE_CLEAN_MASK 0x00010000L 5009 //UVD_JMI_CNTL 5010 #define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 5011 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 5012 #define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 5013 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 5014 5015 5016 // addressBlock: uvd_uvd_jpeg_common_dec 5017 //JPEG_SOFT_RESET_STATUS 5018 #define JPEG_SOFT_RESET_STATUS__JPEG0_DEC_RESET_STATUS__SHIFT 0x0 5019 #define JPEG_SOFT_RESET_STATUS__DJRBC0_RESET_STATUS__SHIFT 0x8 5020 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x11 5021 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x12 5022 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x18 5023 #define JPEG_SOFT_RESET_STATUS__JPEG0_DEC_RESET_STATUS_MASK 0x00000001L 5024 #define JPEG_SOFT_RESET_STATUS__DJRBC0_RESET_STATUS_MASK 0x00000100L 5025 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00020000L 5026 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00040000L 5027 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x01000000L 5028 //JPEG_SYS_INT_EN 5029 #define JPEG_SYS_INT_EN__DJPEG0_CORE__SHIFT 0x0 5030 #define JPEG_SYS_INT_EN__DJRBC0__SHIFT 0x8 5031 #define JPEG_SYS_INT_EN__DJPEG0_PF_RPT__SHIFT 0x10 5032 #define JPEG_SYS_INT_EN__DJPEG0_RAS_CNTL__SHIFT 0x18 5033 #define JPEG_SYS_INT_EN__DJPEG0_CORE_MASK 0x00000001L 5034 #define JPEG_SYS_INT_EN__DJRBC0_MASK 0x00000100L 5035 #define JPEG_SYS_INT_EN__DJPEG0_PF_RPT_MASK 0x00010000L 5036 #define JPEG_SYS_INT_EN__DJPEG0_RAS_CNTL_MASK 0x01000000L 5037 //JPEG_SYS_INT_EN1 5038 #define JPEG_SYS_INT_EN1__EJPEG_PF_RPT__SHIFT 0x0 5039 #define JPEG_SYS_INT_EN1__EJPEG_CORE__SHIFT 0x1 5040 #define JPEG_SYS_INT_EN1__EJRBC__SHIFT 0x2 5041 #define JPEG_SYS_INT_EN1__EJPEG_RAS_CNTL__SHIFT 0x3 5042 #define JPEG_SYS_INT_EN1__EJPEG_PF_RPT_MASK 0x00000001L 5043 #define JPEG_SYS_INT_EN1__EJPEG_CORE_MASK 0x00000002L 5044 #define JPEG_SYS_INT_EN1__EJRBC_MASK 0x00000004L 5045 #define JPEG_SYS_INT_EN1__EJPEG_RAS_CNTL_MASK 0x00000008L 5046 //JPEG_SYS_INT_STATUS 5047 #define JPEG_SYS_INT_STATUS__DJPEG0_CORE__SHIFT 0x0 5048 #define JPEG_SYS_INT_STATUS__DJRBC0__SHIFT 0x8 5049 #define JPEG_SYS_INT_STATUS__DJPEG0_PF_RPT__SHIFT 0x10 5050 #define JPEG_SYS_INT_STATUS__DJPEG0_RAS_CNTL__SHIFT 0x18 5051 #define JPEG_SYS_INT_STATUS__DJPEG0_CORE_MASK 0x00000001L 5052 #define JPEG_SYS_INT_STATUS__DJRBC0_MASK 0x00000100L 5053 #define JPEG_SYS_INT_STATUS__DJPEG0_PF_RPT_MASK 0x00010000L 5054 #define JPEG_SYS_INT_STATUS__DJPEG0_RAS_CNTL_MASK 0x01000000L 5055 //JPEG_SYS_INT_STATUS1 5056 #define JPEG_SYS_INT_STATUS1__EJPEG_PF_RPT__SHIFT 0x0 5057 #define JPEG_SYS_INT_STATUS1__EJPEG_CORE__SHIFT 0x1 5058 #define JPEG_SYS_INT_STATUS1__EJRBC__SHIFT 0x2 5059 #define JPEG_SYS_INT_STATUS1__EJPEG_RAS_CNTL__SHIFT 0x3 5060 #define JPEG_SYS_INT_STATUS1__EJPEG_PF_RPT_MASK 0x00000001L 5061 #define JPEG_SYS_INT_STATUS1__EJPEG_CORE_MASK 0x00000002L 5062 #define JPEG_SYS_INT_STATUS1__EJRBC_MASK 0x00000004L 5063 #define JPEG_SYS_INT_STATUS1__EJPEG_RAS_CNTL_MASK 0x00000008L 5064 //JPEG_SYS_INT_ACK 5065 #define JPEG_SYS_INT_ACK__DJPEG0_CORE__SHIFT 0x0 5066 #define JPEG_SYS_INT_ACK__DJRBC0__SHIFT 0x8 5067 #define JPEG_SYS_INT_ACK__DJPEG0_PF_RPT__SHIFT 0x10 5068 #define JPEG_SYS_INT_ACK__DJPEG0_RAS_CNTL__SHIFT 0x18 5069 #define JPEG_SYS_INT_ACK__DJPEG0_CORE_MASK 0x00000001L 5070 #define JPEG_SYS_INT_ACK__DJRBC0_MASK 0x00000100L 5071 #define JPEG_SYS_INT_ACK__DJPEG0_PF_RPT_MASK 0x00010000L 5072 #define JPEG_SYS_INT_ACK__DJPEG0_RAS_CNTL_MASK 0x01000000L 5073 //JPEG_SYS_INT_ACK1 5074 #define JPEG_SYS_INT_ACK1__EJPEG_PF_RPT__SHIFT 0x0 5075 #define JPEG_SYS_INT_ACK1__EJPEG_CORE__SHIFT 0x1 5076 #define JPEG_SYS_INT_ACK1__EJRBC__SHIFT 0x2 5077 #define JPEG_SYS_INT_ACK1__EJPEG_RAS_CNTL__SHIFT 0x3 5078 #define JPEG_SYS_INT_ACK1__EJPEG_PF_RPT_MASK 0x00000001L 5079 #define JPEG_SYS_INT_ACK1__EJPEG_CORE_MASK 0x00000002L 5080 #define JPEG_SYS_INT_ACK1__EJRBC_MASK 0x00000004L 5081 #define JPEG_SYS_INT_ACK1__EJPEG_RAS_CNTL_MASK 0x00000008L 5082 //JPEG_MEMCHECK_SYS_INT_EN 5083 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_RD_ERR_EN__SHIFT 0x0 5084 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH0_RD_ERR_EN__SHIFT 0x8 5085 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_WR_ERR_EN__SHIFT 0x10 5086 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF0_WR_ERR_EN__SHIFT 0x18 5087 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_RD_ERR_EN_MASK 0x00000001L 5088 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH0_RD_ERR_EN_MASK 0x00000100L 5089 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_WR_ERR_EN_MASK 0x00010000L 5090 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF0_WR_ERR_EN_MASK 0x01000000L 5091 //JPEG_MEMCHECK_SYS_INT_EN1 5092 #define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_RD_ERR_EN__SHIFT 0x0 5093 #define JPEG_MEMCHECK_SYS_INT_EN1__PELFETCH_RD_ERR_EN__SHIFT 0x1 5094 #define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_RD_ERR_EN__SHIFT 0x2 5095 #define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_WR_ERR_EN__SHIFT 0x3 5096 #define JPEG_MEMCHECK_SYS_INT_EN1__BS_WR_ERR_EN__SHIFT 0x4 5097 #define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_WR_ERR_EN__SHIFT 0x5 5098 #define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_RD_ERR_EN_MASK 0x00000001L 5099 #define JPEG_MEMCHECK_SYS_INT_EN1__PELFETCH_RD_ERR_EN_MASK 0x00000002L 5100 #define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_RD_ERR_EN_MASK 0x00000004L 5101 #define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_WR_ERR_EN_MASK 0x00000008L 5102 #define JPEG_MEMCHECK_SYS_INT_EN1__BS_WR_ERR_EN_MASK 0x00000010L 5103 #define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_WR_ERR_EN_MASK 0x00000020L 5104 //JPEG_MEMCHECK_SYS_INT_STAT 5105 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_HI_ERR__SHIFT 0x0 5106 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_LO_ERR__SHIFT 0x8 5107 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_HI_ERR__SHIFT 0x10 5108 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_LO_ERR__SHIFT 0x18 5109 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_HI_ERR_MASK 0x00000001L 5110 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_LO_ERR_MASK 0x00000100L 5111 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_HI_ERR_MASK 0x00010000L 5112 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_LO_ERR_MASK 0x01000000L 5113 //JPEG_MEMCHECK_SYS_INT_STAT1 5114 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_HI_ERR__SHIFT 0x0 5115 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_LO_ERR__SHIFT 0x8 5116 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_HI_ERR__SHIFT 0x10 5117 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_LO_ERR__SHIFT 0x18 5118 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_HI_ERR_MASK 0x00000001L 5119 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_LO_ERR_MASK 0x00000100L 5120 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_HI_ERR_MASK 0x00010000L 5121 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_LO_ERR_MASK 0x01000000L 5122 //JPEG_MEMCHECK_SYS_INT_STAT2 5123 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_HI_ERR__SHIFT 0x0 5124 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_LO_ERR__SHIFT 0x1 5125 #define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_HI_ERR__SHIFT 0x2 5126 #define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_LO_ERR__SHIFT 0x3 5127 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_HI_ERR__SHIFT 0x4 5128 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_LO_ERR__SHIFT 0x5 5129 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_HI_ERR__SHIFT 0x6 5130 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_LO_ERR__SHIFT 0x7 5131 #define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_HI_ERR__SHIFT 0x8 5132 #define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_LO_ERR__SHIFT 0x9 5133 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_HI_ERR__SHIFT 0xa 5134 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_LO_ERR__SHIFT 0xb 5135 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_HI_ERR_MASK 0x00000001L 5136 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_LO_ERR_MASK 0x00000002L 5137 #define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_HI_ERR_MASK 0x00000004L 5138 #define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_LO_ERR_MASK 0x00000008L 5139 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_HI_ERR_MASK 0x00000010L 5140 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_LO_ERR_MASK 0x00000020L 5141 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_HI_ERR_MASK 0x00000040L 5142 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_LO_ERR_MASK 0x00000080L 5143 #define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_HI_ERR_MASK 0x00000100L 5144 #define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_LO_ERR_MASK 0x00000200L 5145 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_HI_ERR_MASK 0x00000400L 5146 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_LO_ERR_MASK 0x00000800L 5147 //JPEG_MEMCHECK_SYS_INT_ACK 5148 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_HI_ERR__SHIFT 0x0 5149 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_LO_ERR__SHIFT 0x8 5150 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_HI_ERR__SHIFT 0x10 5151 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_LO_ERR__SHIFT 0x18 5152 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_HI_ERR_MASK 0x00000001L 5153 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_LO_ERR_MASK 0x00000100L 5154 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_HI_ERR_MASK 0x00010000L 5155 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_LO_ERR_MASK 0x01000000L 5156 //JPEG_MEMCHECK_SYS_INT_ACK1 5157 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_HI_ERR__SHIFT 0x0 5158 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_LO_ERR__SHIFT 0x8 5159 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_HI_ERR__SHIFT 0x10 5160 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_LO_ERR__SHIFT 0x18 5161 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_HI_ERR_MASK 0x00000001L 5162 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_LO_ERR_MASK 0x00000100L 5163 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_HI_ERR_MASK 0x00010000L 5164 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_LO_ERR_MASK 0x01000000L 5165 //JPEG_MEMCHECK_SYS_INT_ACK2 5166 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_HI_ERR__SHIFT 0x0 5167 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_LO_ERR__SHIFT 0x1 5168 #define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_HI_ERR__SHIFT 0x2 5169 #define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_LO_ERR__SHIFT 0x3 5170 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_HI_ERR__SHIFT 0x4 5171 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_LO_ERR__SHIFT 0x5 5172 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_HI_ERR__SHIFT 0x6 5173 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_LO_ERR__SHIFT 0x7 5174 #define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_HI_ERR__SHIFT 0x8 5175 #define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_LO_ERR__SHIFT 0x9 5176 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_HI_ERR__SHIFT 0xa 5177 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_LO_ERR__SHIFT 0xb 5178 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_HI_ERR_MASK 0x00000001L 5179 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_LO_ERR_MASK 0x00000002L 5180 #define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_HI_ERR_MASK 0x00000004L 5181 #define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_LO_ERR_MASK 0x00000008L 5182 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_HI_ERR_MASK 0x00000010L 5183 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_LO_ERR_MASK 0x00000020L 5184 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_HI_ERR_MASK 0x00000040L 5185 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_LO_ERR_MASK 0x00000080L 5186 #define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_HI_ERR_MASK 0x00000100L 5187 #define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_LO_ERR_MASK 0x00000200L 5188 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_HI_ERR_MASK 0x00000400L 5189 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_LO_ERR_MASK 0x00000800L 5190 //JPEG_MASTINT_EN 5191 #define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 5192 #define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 5193 #define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 5194 #define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 5195 //JPEG_IH_CTRL 5196 #define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 5197 #define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 5198 #define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 5199 #define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 5200 #define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 5201 #define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 5202 #define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 5203 #define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 5204 #define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 5205 #define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 5206 #define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 5207 #define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 5208 //JRBBM_ARB_CTRL 5209 #define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x0 5210 #define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 5211 #define JRBBM_ARB_CTRL__DJRBC0_DROP__SHIFT 0x2 5212 #define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 5213 #define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 5214 #define JRBBM_ARB_CTRL__DJRBC0_DROP_MASK 0x00000004L 5215 5216 5217 // addressBlock: uvd_uvd_jpeg_common_sclk_dec 5218 //JPEG_CGC_GATE 5219 #define JPEG_CGC_GATE__JPEG0_DEC__SHIFT 0x0 5220 #define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x8 5221 #define JPEG_CGC_GATE__JMCIF__SHIFT 0x9 5222 #define JPEG_CGC_GATE__JRBBM__SHIFT 0xa 5223 #define JPEG_CGC_GATE__JPEG0_DEC_MASK 0x00000001L 5224 #define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000100L 5225 #define JPEG_CGC_GATE__JMCIF_MASK 0x00000200L 5226 #define JPEG_CGC_GATE__JRBBM_MASK 0x00000400L 5227 //JPEG_CGC_CTRL 5228 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 5229 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 5230 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 5231 #define JPEG_CGC_CTRL__JPEG0_DEC_MODE__SHIFT 0x10 5232 #define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x18 5233 #define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x19 5234 #define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x1a 5235 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 5236 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 5237 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x00001FE0L 5238 #define JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK 0x00010000L 5239 #define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x01000000L 5240 #define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x02000000L 5241 #define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x04000000L 5242 //JPEG_CGC_STATUS 5243 #define JPEG_CGC_STATUS__JPEG0_DEC_VCLK_ACTIVE__SHIFT 0x0 5244 #define JPEG_CGC_STATUS__JPEG0_DEC_SCLK_ACTIVE__SHIFT 0x1 5245 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x10 5246 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x11 5247 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x12 5248 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x13 5249 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x14 5250 #define JPEG_CGC_STATUS__JPEG0_DEC_VCLK_ACTIVE_MASK 0x00000001L 5251 #define JPEG_CGC_STATUS__JPEG0_DEC_SCLK_ACTIVE_MASK 0x00000002L 5252 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00010000L 5253 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00020000L 5254 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00040000L 5255 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00080000L 5256 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00100000L 5257 //JPEG_COMN_CGC_MEM_CTRL 5258 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 5259 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 5260 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 5261 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN__SHIFT 0x3 5262 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 5263 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 5264 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 5265 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN_MASK 0x00000008L 5266 //JPEG_DEC_CGC_MEM_CTRL 5267 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_EN__SHIFT 0x0 5268 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_DS_EN__SHIFT 0x1 5269 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_SD_EN__SHIFT 0x2 5270 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_SW_EN__SHIFT 0x3 5271 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_EN_MASK 0x00000001L 5272 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_DS_EN_MASK 0x00000002L 5273 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_SD_EN_MASK 0x00000004L 5274 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_SW_EN_MASK 0x00000008L 5275 //JPEG_ENC_CGC_MEM_CTRL 5276 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 5277 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 5278 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 5279 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN__SHIFT 0x3 5280 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 5281 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 5282 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 5283 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN_MASK 0x00000008L 5284 //JPEG_PERF_BANK_CONF 5285 #define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 5286 #define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 5287 #define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 5288 #define JPEG_PERF_BANK_CONF__CORE_SEL__SHIFT 0x15 5289 #define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 5290 #define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 5291 #define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 5292 #define JPEG_PERF_BANK_CONF__CORE_SEL_MASK 0x00E00000L 5293 //JPEG_PERF_BANK_EVENT_SEL 5294 #define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 5295 #define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 5296 #define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 5297 #define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 5298 #define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 5299 #define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 5300 #define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 5301 #define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 5302 //JPEG_PERF_BANK_COUNT0 5303 #define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 5304 #define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 5305 //JPEG_PERF_BANK_COUNT1 5306 #define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 5307 #define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 5308 //JPEG_PERF_BANK_COUNT2 5309 #define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 5310 #define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 5311 //JPEG_PERF_BANK_COUNT3 5312 #define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 5313 #define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 5314 5315 5316 // addressBlock: uvd_uvd_pg_dec 5317 //UVD_IPX_DLDO_CONFIG 5318 #define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT 0x2 5319 #define UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT 0x4 5320 #define UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT 0x6 5321 #define UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT 0x8 5322 #define UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT 0xa 5323 #define UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT 0xc 5324 #define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK 0x0000000CL 5325 #define UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG_MASK 0x00000030L 5326 #define UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG_MASK 0x000000C0L 5327 #define UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG_MASK 0x00000300L 5328 #define UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG_MASK 0x00000C00L 5329 #define UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG_MASK 0x00003000L 5330 //UVD_IPX_DLDO_STATUS 5331 #define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT 0x1 5332 #define UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT 0x2 5333 #define UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT 0x3 5334 #define UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT 0x4 5335 #define UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT 0x5 5336 #define UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT 0x6 5337 #define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK 0x00000002L 5338 #define UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK 0x00000004L 5339 #define UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK 0x00000008L 5340 #define UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK 0x00000010L 5341 #define UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK 0x00000020L 5342 #define UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK 0x00000040L 5343 //UVD_POWER_STATUS 5344 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 5345 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 5346 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 5347 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 5348 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 5349 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 5350 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 5351 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L 5352 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 5353 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 5354 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 5355 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 5356 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 5357 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 5358 //UVD_JPEG_POWER_STATUS 5359 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 5360 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 5361 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 5362 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 5363 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 5364 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 5365 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 5366 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 5367 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 5368 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 5369 //UVD_MC_DJPEG_RD_SPACE 5370 #define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE__SHIFT 0x0 5371 #define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE_MASK 0x0003FFFFL 5372 //UVD_MC_DJPEG_WR_SPACE 5373 #define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE__SHIFT 0x0 5374 #define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE_MASK 0x0003FFFFL 5375 //UVD_PG_IND_INDEX 5376 #define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 5377 #define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 5378 //UVD_PG_IND_DATA 5379 #define UVD_PG_IND_DATA__DATA__SHIFT 0x0 5380 #define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 5381 //CC_UVD_HARVESTING 5382 #define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 5383 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 5384 #define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 5385 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 5386 //UVD_DPG_LMA_CTL 5387 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 5388 #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 5389 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 5390 #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 5391 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0xe 5392 #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 5393 #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 5394 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 5395 #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 5396 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFFC000L 5397 //UVD_DPG_LMA_DATA 5398 #define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 5399 #define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 5400 //UVD_DPG_LMA_MASK 5401 #define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 5402 #define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 5403 //UVD_DPG_PAUSE 5404 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 5405 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 5406 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 5407 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 5408 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 5409 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 5410 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 5411 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 5412 //UVD_SCRATCH1 5413 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 5414 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 5415 //UVD_SCRATCH2 5416 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 5417 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 5418 //UVD_SCRATCH3 5419 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 5420 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 5421 //UVD_SCRATCH4 5422 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 5423 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 5424 //UVD_SCRATCH5 5425 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 5426 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 5427 //UVD_SCRATCH6 5428 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 5429 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 5430 //UVD_SCRATCH7 5431 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 5432 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 5433 //UVD_SCRATCH8 5434 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 5435 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 5436 //UVD_SCRATCH9 5437 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 5438 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 5439 //UVD_SCRATCH10 5440 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 5441 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 5442 //UVD_SCRATCH11 5443 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 5444 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 5445 //UVD_SCRATCH12 5446 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 5447 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 5448 //UVD_SCRATCH13 5449 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 5450 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 5451 //UVD_SCRATCH14 5452 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 5453 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 5454 //UVD_FREE_COUNTER_REG 5455 #define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 5456 #define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 5457 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 5458 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5459 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5460 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 5461 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5462 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5463 //UVD_DPG_VCPU_CACHE_OFFSET0 5464 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 5465 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 5466 //UVD_DPG_LMI_VCPU_CACHE_VMID 5467 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 5468 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 5469 //UVD_REG_FILTER_EN 5470 #define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN__SHIFT 0x0 5471 #define UVD_REG_FILTER_EN__MMSCH_HI_PRIV__SHIFT 0x1 5472 #define UVD_REG_FILTER_EN__VIDEO_PRIV_EN__SHIFT 0x2 5473 #define UVD_REG_FILTER_EN__JPEG_PRIV_EN__SHIFT 0x3 5474 #define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN_MASK 0x00000001L 5475 #define UVD_REG_FILTER_EN__MMSCH_HI_PRIV_MASK 0x00000002L 5476 #define UVD_REG_FILTER_EN__VIDEO_PRIV_EN_MASK 0x00000004L 5477 #define UVD_REG_FILTER_EN__JPEG_PRIV_EN_MASK 0x00000008L 5478 //UVD_SECURITY_REG_VIO_REPORT 5479 #define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO__SHIFT 0x0 5480 #define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO__SHIFT 0x1 5481 #define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO__SHIFT 0x2 5482 #define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO__SHIFT 0x3 5483 #define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO__SHIFT 0x4 5484 #define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO__SHIFT 0x5 5485 #define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO_MASK 0x00000001L 5486 #define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO_MASK 0x00000002L 5487 #define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO_MASK 0x00000004L 5488 #define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO_MASK 0x00000008L 5489 #define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO_MASK 0x00000010L 5490 #define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO_MASK 0x00000020L 5491 //UVD_FW_VERSION 5492 #define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0 5493 #define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL 5494 //UVD_PF_STATUS 5495 #define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 5496 #define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 5497 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 5498 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 5499 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 5500 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 5501 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 5502 #define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 5503 #define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 5504 #define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 5505 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 5506 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 5507 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 5508 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 5509 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 5510 #define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 5511 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 5512 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 5513 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 5514 #define UVD_PF_STATUS__JPEG2_PF_OCCURED__SHIFT 0x13 5515 #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED__SHIFT 0x14 5516 #define UVD_PF_STATUS__JPEG2_PF_CLEAR__SHIFT 0x15 5517 #define UVD_PF_STATUS__ENCODER5_PF_OCCURED__SHIFT 0x16 5518 #define UVD_PF_STATUS__ENCODER5_PF_CLEAR__SHIFT 0x17 5519 #define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 5520 #define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 5521 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 5522 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 5523 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 5524 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 5525 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 5526 #define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 5527 #define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 5528 #define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 5529 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 5530 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 5531 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 5532 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 5533 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 5534 #define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 5535 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 5536 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 5537 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 5538 #define UVD_PF_STATUS__JPEG2_PF_OCCURED_MASK 0x00080000L 5539 #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED_MASK 0x00100000L 5540 #define UVD_PF_STATUS__JPEG2_PF_CLEAR_MASK 0x00200000L 5541 #define UVD_PF_STATUS__ENCODER5_PF_OCCURED_MASK 0x00400000L 5542 #define UVD_PF_STATUS__ENCODER5_PF_CLEAR_MASK 0x00800000L 5543 //UVD_DPG_CLK_EN_VCPU_REPORT 5544 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 5545 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 5546 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 5547 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 5548 //CC_UVD_VCPU_ERR_DETECT_BOT_LO 5549 #define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO__SHIFT 0xc 5550 #define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO_MASK 0xFFFFF000L 5551 //CC_UVD_VCPU_ERR_DETECT_BOT_HI 5552 #define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI__SHIFT 0x0 5553 #define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI_MASK 0x0000FFFFL 5554 //CC_UVD_VCPU_ERR_DETECT_TOP_LO 5555 #define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO__SHIFT 0xc 5556 #define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO_MASK 0xFFFFF000L 5557 //CC_UVD_VCPU_ERR_DETECT_TOP_HI 5558 #define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI__SHIFT 0x0 5559 #define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI_MASK 0x0000FFFFL 5560 //CC_UVD_VCPU_ERR 5561 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS__SHIFT 0x0 5562 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR__SHIFT 0x1 5563 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN__SHIFT 0x2 5564 #define CC_UVD_VCPU_ERR__UVD_TMZ_DBG_DIS__SHIFT 0x3 5565 #define CC_UVD_VCPU_ERR__RESET_ON_FAULT__SHIFT 0x4 5566 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS_MASK 0x00000001L 5567 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR_MASK 0x00000002L 5568 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN_MASK 0x00000004L 5569 #define CC_UVD_VCPU_ERR__UVD_TMZ_DBG_DIS_MASK 0x00000008L 5570 #define CC_UVD_VCPU_ERR__RESET_ON_FAULT_MASK 0x00000010L 5571 //CC_UVD_VCPU_ERR_INST_ADDR_LO 5572 #define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO__SHIFT 0x0 5573 #define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO_MASK 0xFFFFFFFFL 5574 //CC_UVD_VCPU_ERR_INST_ADDR_HI 5575 #define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI__SHIFT 0x0 5576 #define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI_MASK 0x0000FFFFL 5577 //UVD_LMI_MMSCH_NC_SPACE 5578 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE__SHIFT 0x0 5579 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE__SHIFT 0x3 5580 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE__SHIFT 0x6 5581 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE__SHIFT 0x9 5582 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE__SHIFT 0xc 5583 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE__SHIFT 0xf 5584 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE__SHIFT 0x12 5585 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE__SHIFT 0x15 5586 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE_MASK 0x00000007L 5587 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE_MASK 0x00000038L 5588 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE_MASK 0x000001C0L 5589 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE_MASK 0x00000E00L 5590 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE_MASK 0x00007000L 5591 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE_MASK 0x00038000L 5592 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE_MASK 0x001C0000L 5593 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE_MASK 0x00E00000L 5594 //UVD_LMI_ATOMIC_SPACE 5595 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE__SHIFT 0x0 5596 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE__SHIFT 0x3 5597 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE__SHIFT 0x6 5598 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE__SHIFT 0x9 5599 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE_MASK 0x00000007L 5600 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE_MASK 0x00000038L 5601 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE_MASK 0x000001C0L 5602 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE_MASK 0x00000E00L 5603 //UVD_GFX8_ADDR_CONFIG 5604 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 5605 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 5606 //UVD_GFX10_ADDR_CONFIG 5607 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 5608 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 5609 #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 5610 #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 5611 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 5612 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 5613 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 5614 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 5615 #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 5616 #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 5617 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 5618 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 5619 //UVD_GPCNT2_CNTL 5620 #define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 5621 #define UVD_GPCNT2_CNTL__START__SHIFT 0x1 5622 #define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 5623 #define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 5624 #define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 5625 #define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 5626 //UVD_GPCNT2_TARGET_LOWER 5627 #define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 5628 #define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 5629 //UVD_GPCNT2_STATUS_LOWER 5630 #define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 5631 #define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 5632 //UVD_GPCNT2_TARGET_UPPER 5633 #define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 5634 #define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 5635 //UVD_GPCNT2_STATUS_UPPER 5636 #define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 5637 #define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 5638 //UVD_GPCNT3_CNTL 5639 #define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 5640 #define UVD_GPCNT3_CNTL__START__SHIFT 0x1 5641 #define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 5642 #define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 5643 #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 5644 #define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 5645 #define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 5646 #define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 5647 #define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 5648 #define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 5649 //UVD_GPCNT3_TARGET_LOWER 5650 #define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 5651 #define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 5652 //UVD_GPCNT3_STATUS_LOWER 5653 #define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 5654 #define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 5655 //UVD_GPCNT3_TARGET_UPPER 5656 #define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 5657 #define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 5658 //UVD_GPCNT3_STATUS_UPPER 5659 #define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 5660 #define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 5661 //UVD_VCLK_DS_CNTL 5662 #define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 5663 #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 5664 #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 5665 #define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L 5666 #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L 5667 #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 5668 //UVD_DCLK_DS_CNTL 5669 #define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 5670 #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 5671 #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 5672 #define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L 5673 #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L 5674 #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 5675 //UVD_TSC_LOWER 5676 #define UVD_TSC_LOWER__COUNT__SHIFT 0x0 5677 #define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL 5678 //UVD_TSC_UPPER 5679 #define UVD_TSC_UPPER__COUNT__SHIFT 0x0 5680 #define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL 5681 //VCN_FEATURES 5682 #define VCN_FEATURES__HAS_VIDEO_DEC__SHIFT 0x0 5683 #define VCN_FEATURES__HAS_VIDEO_ENC__SHIFT 0x1 5684 #define VCN_FEATURES__HAS_MJPEG_DEC__SHIFT 0x2 5685 #define VCN_FEATURES__HAS_MJPEG_ENC__SHIFT 0x3 5686 #define VCN_FEATURES__HAS_VIDEO_VIRT__SHIFT 0x4 5687 #define VCN_FEATURES__HAS_H264_LEGACY_DEC__SHIFT 0x5 5688 #define VCN_FEATURES__HAS_UDEC_DEC__SHIFT 0x6 5689 #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC__SHIFT 0x7 5690 #define VCN_FEATURES__HAS_SCLR_DEC__SHIFT 0x8 5691 #define VCN_FEATURES__HAS_VP9_DEC__SHIFT 0x9 5692 #define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa 5693 #define VCN_FEATURES__HAS_EFC_ENC__SHIFT 0xb 5694 #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC__SHIFT 0xc 5695 #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC__SHIFT 0xd 5696 #define VCN_FEATURES__HAS_AV1_ENC__SHIFT 0xe 5697 #define VCN_FEATURES__INSTANCE_ID__SHIFT 0x1c 5698 #define VCN_FEATURES__HAS_VIDEO_DEC_MASK 0x00000001L 5699 #define VCN_FEATURES__HAS_VIDEO_ENC_MASK 0x00000002L 5700 #define VCN_FEATURES__HAS_MJPEG_DEC_MASK 0x00000004L 5701 #define VCN_FEATURES__HAS_MJPEG_ENC_MASK 0x00000008L 5702 #define VCN_FEATURES__HAS_VIDEO_VIRT_MASK 0x00000010L 5703 #define VCN_FEATURES__HAS_H264_LEGACY_DEC_MASK 0x00000020L 5704 #define VCN_FEATURES__HAS_UDEC_DEC_MASK 0x00000040L 5705 #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC_MASK 0x00000080L 5706 #define VCN_FEATURES__HAS_SCLR_DEC_MASK 0x00000100L 5707 #define VCN_FEATURES__HAS_VP9_DEC_MASK 0x00000200L 5708 #define VCN_FEATURES__HAS_AV1_DEC_MASK 0x00000400L 5709 #define VCN_FEATURES__HAS_EFC_ENC_MASK 0x00000800L 5710 #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC_MASK 0x00001000L 5711 #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC_MASK 0x00002000L 5712 #define VCN_FEATURES__HAS_AV1_ENC_MASK 0x00004000L 5713 #define VCN_FEATURES__INSTANCE_ID_MASK 0xF0000000L 5714 //UVD_GPUIOV_STATUS 5715 #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE__SHIFT 0x0 5716 #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE_MASK 0x00000001L 5717 //UVD_SCRATCH15 5718 #define UVD_SCRATCH15__SCRATCH15_DATA__SHIFT 0x0 5719 #define UVD_SCRATCH15__SCRATCH15_DATA_MASK 0xFFFFFFFFL 5720 //UVD_VERSION 5721 #define UVD_VERSION__VARIANT_TYPE__SHIFT 0x0 5722 #define UVD_VERSION__MINOR_VERSION__SHIFT 0x8 5723 #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 5724 #define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c 5725 #define UVD_VERSION__VARIANT_TYPE_MASK 0x000000FFL 5726 #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FF00L 5727 #define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L 5728 #define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L 5729 //VCN_UMSCH_CNTL 5730 #define VCN_UMSCH_CNTL__umsch_fw_en__SHIFT 0x0 5731 #define VCN_UMSCH_CNTL__umsch_fw_en_MASK 0x00000001L 5732 //VCN_JPEG_DB_CTRL 5733 #define VCN_JPEG_DB_CTRL__OFFSET__SHIFT 0x2 5734 #define VCN_JPEG_DB_CTRL__EN__SHIFT 0x1e 5735 #define VCN_JPEG_DB_CTRL__HIT__SHIFT 0x1f 5736 #define VCN_JPEG_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 5737 #define VCN_JPEG_DB_CTRL__EN_MASK 0x40000000L 5738 #define VCN_JPEG_DB_CTRL__HIT_MASK 0x80000000L 5739 //VCN_RB1_DB_CTRL 5740 #define VCN_RB1_DB_CTRL__OFFSET__SHIFT 0x2 5741 #define VCN_RB1_DB_CTRL__EN__SHIFT 0x1e 5742 #define VCN_RB1_DB_CTRL__HIT__SHIFT 0x1f 5743 #define VCN_RB1_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 5744 #define VCN_RB1_DB_CTRL__EN_MASK 0x40000000L 5745 #define VCN_RB1_DB_CTRL__HIT_MASK 0x80000000L 5746 //VCN_RB2_DB_CTRL 5747 #define VCN_RB2_DB_CTRL__OFFSET__SHIFT 0x2 5748 #define VCN_RB2_DB_CTRL__EN__SHIFT 0x1e 5749 #define VCN_RB2_DB_CTRL__HIT__SHIFT 0x1f 5750 #define VCN_RB2_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 5751 #define VCN_RB2_DB_CTRL__EN_MASK 0x40000000L 5752 #define VCN_RB2_DB_CTRL__HIT_MASK 0x80000000L 5753 //VCN_RB3_DB_CTRL 5754 #define VCN_RB3_DB_CTRL__OFFSET__SHIFT 0x2 5755 #define VCN_RB3_DB_CTRL__EN__SHIFT 0x1e 5756 #define VCN_RB3_DB_CTRL__HIT__SHIFT 0x1f 5757 #define VCN_RB3_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 5758 #define VCN_RB3_DB_CTRL__EN_MASK 0x40000000L 5759 #define VCN_RB3_DB_CTRL__HIT_MASK 0x80000000L 5760 //VCN_RB4_DB_CTRL 5761 #define VCN_RB4_DB_CTRL__OFFSET__SHIFT 0x2 5762 #define VCN_RB4_DB_CTRL__EN__SHIFT 0x1e 5763 #define VCN_RB4_DB_CTRL__HIT__SHIFT 0x1f 5764 #define VCN_RB4_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 5765 #define VCN_RB4_DB_CTRL__EN_MASK 0x40000000L 5766 #define VCN_RB4_DB_CTRL__HIT_MASK 0x80000000L 5767 //VCN_UMSCH_RB_DB_CTRL 5768 #define VCN_UMSCH_RB_DB_CTRL__OFFSET__SHIFT 0x2 5769 #define VCN_UMSCH_RB_DB_CTRL__EN__SHIFT 0x1e 5770 #define VCN_UMSCH_RB_DB_CTRL__HIT__SHIFT 0x1f 5771 #define VCN_UMSCH_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 5772 #define VCN_UMSCH_RB_DB_CTRL__EN_MASK 0x40000000L 5773 #define VCN_UMSCH_RB_DB_CTRL__HIT_MASK 0x80000000L 5774 //VCN_RB_DB_CTRL 5775 #define VCN_RB_DB_CTRL__OFFSET__SHIFT 0x2 5776 #define VCN_RB_DB_CTRL__EN__SHIFT 0x1e 5777 #define VCN_RB_DB_CTRL__HIT__SHIFT 0x1f 5778 #define VCN_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 5779 #define VCN_RB_DB_CTRL__EN_MASK 0x40000000L 5780 #define VCN_RB_DB_CTRL__HIT_MASK 0x80000000L 5781 //VCN_AGDB_CTRL0 5782 #define VCN_AGDB_CTRL0__OFFSET__SHIFT 0x2 5783 #define VCN_AGDB_CTRL0__EN__SHIFT 0x1e 5784 #define VCN_AGDB_CTRL0__HIT__SHIFT 0x1f 5785 #define VCN_AGDB_CTRL0__OFFSET_MASK 0x0FFFFFFCL 5786 #define VCN_AGDB_CTRL0__EN_MASK 0x40000000L 5787 #define VCN_AGDB_CTRL0__HIT_MASK 0x80000000L 5788 //VCN_AGDB_CTRL1 5789 #define VCN_AGDB_CTRL1__OFFSET__SHIFT 0x2 5790 #define VCN_AGDB_CTRL1__EN__SHIFT 0x1e 5791 #define VCN_AGDB_CTRL1__HIT__SHIFT 0x1f 5792 #define VCN_AGDB_CTRL1__OFFSET_MASK 0x0FFFFFFCL 5793 #define VCN_AGDB_CTRL1__EN_MASK 0x40000000L 5794 #define VCN_AGDB_CTRL1__HIT_MASK 0x80000000L 5795 //VCN_AGDB_CTRL2 5796 #define VCN_AGDB_CTRL2__OFFSET__SHIFT 0x2 5797 #define VCN_AGDB_CTRL2__EN__SHIFT 0x1e 5798 #define VCN_AGDB_CTRL2__HIT__SHIFT 0x1f 5799 #define VCN_AGDB_CTRL2__OFFSET_MASK 0x0FFFFFFCL 5800 #define VCN_AGDB_CTRL2__EN_MASK 0x40000000L 5801 #define VCN_AGDB_CTRL2__HIT_MASK 0x80000000L 5802 //VCN_AGDB_CTRL3 5803 #define VCN_AGDB_CTRL3__OFFSET__SHIFT 0x2 5804 #define VCN_AGDB_CTRL3__EN__SHIFT 0x1e 5805 #define VCN_AGDB_CTRL3__HIT__SHIFT 0x1f 5806 #define VCN_AGDB_CTRL3__OFFSET_MASK 0x0FFFFFFCL 5807 #define VCN_AGDB_CTRL3__EN_MASK 0x40000000L 5808 #define VCN_AGDB_CTRL3__HIT_MASK 0x80000000L 5809 //VCN_AGDB_CTRL4 5810 #define VCN_AGDB_CTRL4__OFFSET__SHIFT 0x2 5811 #define VCN_AGDB_CTRL4__EN__SHIFT 0x1e 5812 #define VCN_AGDB_CTRL4__HIT__SHIFT 0x1f 5813 #define VCN_AGDB_CTRL4__OFFSET_MASK 0x0FFFFFFCL 5814 #define VCN_AGDB_CTRL4__EN_MASK 0x40000000L 5815 #define VCN_AGDB_CTRL4__HIT_MASK 0x80000000L 5816 //VCN_AGDB_CTRL5 5817 #define VCN_AGDB_CTRL5__OFFSET__SHIFT 0x2 5818 #define VCN_AGDB_CTRL5__EN__SHIFT 0x1e 5819 #define VCN_AGDB_CTRL5__HIT__SHIFT 0x1f 5820 #define VCN_AGDB_CTRL5__OFFSET_MASK 0x0FFFFFFCL 5821 #define VCN_AGDB_CTRL5__EN_MASK 0x40000000L 5822 #define VCN_AGDB_CTRL5__HIT_MASK 0x80000000L 5823 //VCN_AGDB_MASK0 5824 #define VCN_AGDB_MASK0__MASK__SHIFT 0x2 5825 #define VCN_AGDB_MASK0__MASK_MASK 0x0FFFFFFCL 5826 //VCN_AGDB_MASK1 5827 #define VCN_AGDB_MASK1__MASK__SHIFT 0x2 5828 #define VCN_AGDB_MASK1__MASK_MASK 0x0FFFFFFCL 5829 //VCN_AGDB_MASK2 5830 #define VCN_AGDB_MASK2__MASK__SHIFT 0x2 5831 #define VCN_AGDB_MASK2__MASK_MASK 0x0FFFFFFCL 5832 //VCN_AGDB_MASK3 5833 #define VCN_AGDB_MASK3__MASK__SHIFT 0x2 5834 #define VCN_AGDB_MASK3__MASK_MASK 0x0FFFFFFCL 5835 //VCN_AGDB_MASK4 5836 #define VCN_AGDB_MASK4__MASK__SHIFT 0x2 5837 #define VCN_AGDB_MASK4__MASK_MASK 0x0FFFFFFCL 5838 //VCN_AGDB_MASK5 5839 #define VCN_AGDB_MASK5__MASK__SHIFT 0x2 5840 #define VCN_AGDB_MASK5__MASK_MASK 0x0FFFFFFCL 5841 //VCN_RB_ENABLE 5842 #define VCN_RB_ENABLE__RB_EN__SHIFT 0x0 5843 #define VCN_RB_ENABLE__JPEG_RB_EN__SHIFT 0x1 5844 #define VCN_RB_ENABLE__RB1_EN__SHIFT 0x2 5845 #define VCN_RB_ENABLE__RB2_EN__SHIFT 0x3 5846 #define VCN_RB_ENABLE__RB3_EN__SHIFT 0x4 5847 #define VCN_RB_ENABLE__RB4_EN__SHIFT 0x5 5848 #define VCN_RB_ENABLE__UMSCH_RB_EN__SHIFT 0x6 5849 #define VCN_RB_ENABLE__EJPEG_RB_EN__SHIFT 0x7 5850 #define VCN_RB_ENABLE__AUDIO_RB_EN__SHIFT 0x8 5851 #define VCN_RB_ENABLE__RB_EN_MASK 0x00000001L 5852 #define VCN_RB_ENABLE__JPEG_RB_EN_MASK 0x00000002L 5853 #define VCN_RB_ENABLE__RB1_EN_MASK 0x00000004L 5854 #define VCN_RB_ENABLE__RB2_EN_MASK 0x00000008L 5855 #define VCN_RB_ENABLE__RB3_EN_MASK 0x00000010L 5856 #define VCN_RB_ENABLE__RB4_EN_MASK 0x00000020L 5857 #define VCN_RB_ENABLE__UMSCH_RB_EN_MASK 0x00000040L 5858 #define VCN_RB_ENABLE__EJPEG_RB_EN_MASK 0x00000080L 5859 #define VCN_RB_ENABLE__AUDIO_RB_EN_MASK 0x00000100L 5860 //VCN_RB_WPTR_CTRL 5861 #define VCN_RB_WPTR_CTRL__RB_CS_EN__SHIFT 0x0 5862 #define VCN_RB_WPTR_CTRL__JPEG_CS_EN__SHIFT 0x1 5863 #define VCN_RB_WPTR_CTRL__RB1_CS_EN__SHIFT 0x2 5864 #define VCN_RB_WPTR_CTRL__RB2_CS_EN__SHIFT 0x3 5865 #define VCN_RB_WPTR_CTRL__RB3_CS_EN__SHIFT 0x4 5866 #define VCN_RB_WPTR_CTRL__RB4_CS_EN__SHIFT 0x5 5867 #define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN__SHIFT 0x6 5868 #define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN__SHIFT 0x7 5869 #define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN__SHIFT 0x8 5870 #define VCN_RB_WPTR_CTRL__RB_CS_EN_MASK 0x00000001L 5871 #define VCN_RB_WPTR_CTRL__JPEG_CS_EN_MASK 0x00000002L 5872 #define VCN_RB_WPTR_CTRL__RB1_CS_EN_MASK 0x00000004L 5873 #define VCN_RB_WPTR_CTRL__RB2_CS_EN_MASK 0x00000008L 5874 #define VCN_RB_WPTR_CTRL__RB3_CS_EN_MASK 0x00000010L 5875 #define VCN_RB_WPTR_CTRL__RB4_CS_EN_MASK 0x00000020L 5876 #define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN_MASK 0x00000040L 5877 #define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN_MASK 0x00000080L 5878 #define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN_MASK 0x00000100L 5879 //UVD_RB_RPTR 5880 #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 5881 #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 5882 //UVD_RB_WPTR 5883 #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 5884 #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 5885 //UVD_RB_RPTR2 5886 #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 5887 #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 5888 //UVD_RB_WPTR2 5889 #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 5890 #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 5891 //UVD_RB_RPTR3 5892 #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 5893 #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 5894 //UVD_RB_WPTR3 5895 #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 5896 #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 5897 //UVD_RB_RPTR4 5898 #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 5899 #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 5900 //UVD_RB_WPTR4 5901 #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 5902 #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 5903 //UVD_OUT_RB_RPTR 5904 #define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 5905 #define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 5906 //UVD_OUT_RB_WPTR 5907 #define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 5908 #define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 5909 //UVD_AUDIO_RB_RPTR 5910 #define UVD_AUDIO_RB_RPTR__RB_RPTR__SHIFT 0x4 5911 #define UVD_AUDIO_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 5912 //UVD_AUDIO_RB_WPTR 5913 #define UVD_AUDIO_RB_WPTR__RB_WPTR__SHIFT 0x4 5914 #define UVD_AUDIO_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 5915 //UVD_RBC_RB_RPTR 5916 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 5917 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 5918 //UVD_RBC_RB_WPTR 5919 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 5920 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 5921 //UVD_DPG_LMA_CTL2 5922 #define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL__SHIFT 0x0 5923 #define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN__SHIFT 0x1 5924 #define UVD_DPG_LMA_CTL2__VID_WRITE_PTR__SHIFT 0x2 5925 #define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR__SHIFT 0x9 5926 #define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL_MASK 0x00000001L 5927 #define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN_MASK 0x00000002L 5928 #define UVD_DPG_LMA_CTL2__VID_WRITE_PTR_MASK 0x000001FCL 5929 #define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR_MASK 0x0000FE00L 5930 5931 5932 // addressBlock: uvd_vcn_umsch_dec 5933 //VCN_UMSCH_MES_CNTL 5934 #define VCN_UMSCH_MES_CNTL__PIPE_ID__SHIFT 0x0 5935 #define VCN_UMSCH_MES_CNTL__PerfPipeSel__SHIFT 0x2 5936 #define VCN_UMSCH_MES_CNTL__RamClkGatingDisable__SHIFT 0x4 5937 #define VCN_UMSCH_MES_CNTL__InterruptChickenBit__SHIFT 0x5 5938 #define VCN_UMSCH_MES_CNTL__CpTcOneCycleWrDis__SHIFT 0x6 5939 #define VCN_UMSCH_MES_CNTL__PIPE_ID_MASK 0x00000003L 5940 #define VCN_UMSCH_MES_CNTL__PerfPipeSel_MASK 0x0000000CL 5941 #define VCN_UMSCH_MES_CNTL__RamClkGatingDisable_MASK 0x00000010L 5942 #define VCN_UMSCH_MES_CNTL__InterruptChickenBit_MASK 0x00000020L 5943 #define VCN_UMSCH_MES_CNTL__CpTcOneCycleWrDis_MASK 0x00000040L 5944 //UMSCH_CTL 5945 #define UMSCH_CTL__P_RESET__SHIFT 0x0 5946 #define UMSCH_CTL__UTCL2_CLIENT_ID__SHIFT 0x1 5947 #define UMSCH_CTL__UMSCH_BUSY__SHIFT 0xa 5948 #define UMSCH_CTL__IllegalRegReadAckLatency__SHIFT 0xd 5949 #define UMSCH_CTL__P_RESET_MASK 0x00000001L 5950 #define UMSCH_CTL__UTCL2_CLIENT_ID_MASK 0x000003FEL 5951 #define UMSCH_CTL__UMSCH_BUSY_MASK 0x00000400L 5952 #define UMSCH_CTL__IllegalRegReadAckLatency_MASK 0x0000E000L 5953 //UMSCH_CTL2 5954 #define UMSCH_CTL2__Spare__SHIFT 0x0 5955 #define UMSCH_CTL2__Spare_MASK 0xFFFFFFFFL 5956 //VCN_UMSCH_AGDB_WPTR0 5957 #define VCN_UMSCH_AGDB_WPTR0__WPTR__SHIFT 0x4 5958 #define VCN_UMSCH_AGDB_WPTR0__WPTR_MASK 0x007FFFF0L 5959 //VCN_UMSCH_AGDB_WPTR1 5960 #define VCN_UMSCH_AGDB_WPTR1__WPTR__SHIFT 0x4 5961 #define VCN_UMSCH_AGDB_WPTR1__WPTR_MASK 0x007FFFF0L 5962 //VCN_UMSCH_AGDB_WPTR2 5963 #define VCN_UMSCH_AGDB_WPTR2__WPTR__SHIFT 0x4 5964 #define VCN_UMSCH_AGDB_WPTR2__WPTR_MASK 0x007FFFF0L 5965 //VCN_UMSCH_AGDB_WPTR3 5966 #define VCN_UMSCH_AGDB_WPTR3__WPTR__SHIFT 0x4 5967 #define VCN_UMSCH_AGDB_WPTR3__WPTR_MASK 0x007FFFF0L 5968 //VCN_UMSCH_AGDB_WPTR4 5969 #define VCN_UMSCH_AGDB_WPTR4__WPTR__SHIFT 0x4 5970 #define VCN_UMSCH_AGDB_WPTR4__WPTR_MASK 0x007FFFF0L 5971 //VCN_UMSCH_AGDB_WPTR5 5972 #define VCN_UMSCH_AGDB_WPTR5__WPTR__SHIFT 0x4 5973 #define VCN_UMSCH_AGDB_WPTR5__WPTR_MASK 0x007FFFF0L 5974 //VCN_UMSCH_MAILBOX0 5975 #define VCN_UMSCH_MAILBOX0__DATA__SHIFT 0x0 5976 #define VCN_UMSCH_MAILBOX0__DATA_MASK 0xFFFFFFFFL 5977 //VCN_UMSCH_MAILBOX_RESP0 5978 #define VCN_UMSCH_MAILBOX_RESP0__DATA__SHIFT 0x0 5979 #define VCN_UMSCH_MAILBOX_RESP0__DATA_MASK 0xFFFFFFFFL 5980 //VCN_UMSCH_MAILBOX1 5981 #define VCN_UMSCH_MAILBOX1__DATA__SHIFT 0x0 5982 #define VCN_UMSCH_MAILBOX1__DATA_MASK 0xFFFFFFFFL 5983 //VCN_UMSCH_MAILBOX_RESP1 5984 #define VCN_UMSCH_MAILBOX_RESP1__DATA__SHIFT 0x0 5985 #define VCN_UMSCH_MAILBOX_RESP1__DATA_MASK 0xFFFFFFFFL 5986 //VCN_UMSCH_MAILBOX2 5987 #define VCN_UMSCH_MAILBOX2__DATA__SHIFT 0x0 5988 #define VCN_UMSCH_MAILBOX2__DATA_MASK 0xFFFFFFFFL 5989 //VCN_UMSCH_MAILBOX_RESP2 5990 #define VCN_UMSCH_MAILBOX_RESP2__DATA__SHIFT 0x0 5991 #define VCN_UMSCH_MAILBOX_RESP2__DATA_MASK 0xFFFFFFFFL 5992 //VCN_UMSCH_MAILBOX3 5993 #define VCN_UMSCH_MAILBOX3__DATA__SHIFT 0x0 5994 #define VCN_UMSCH_MAILBOX3__DATA_MASK 0xFFFFFFFFL 5995 //VCN_UMSCH_MAILBOX_RESP3 5996 #define VCN_UMSCH_MAILBOX_RESP3__DATA__SHIFT 0x0 5997 #define VCN_UMSCH_MAILBOX_RESP3__DATA_MASK 0xFFFFFFFFL 5998 //VCN_UMSCH_SPARE_REGISTER0 5999 #define VCN_UMSCH_SPARE_REGISTER0__DATA__SHIFT 0x0 6000 #define VCN_UMSCH_SPARE_REGISTER0__DATA_MASK 0xFFFFFFFFL 6001 //VCN_UMSCH_SPARE_REGISTER1 6002 #define VCN_UMSCH_SPARE_REGISTER1__DATA__SHIFT 0x0 6003 #define VCN_UMSCH_SPARE_REGISTER1__DATA_MASK 0xFFFFFFFFL 6004 //VCN_UMSCH_SPARE_REGISTER2 6005 #define VCN_UMSCH_SPARE_REGISTER2__DATA__SHIFT 0x0 6006 #define VCN_UMSCH_SPARE_REGISTER2__DATA_MASK 0xFFFFFFFFL 6007 //VCN_UMSCH_SPARE_REGISTER3 6008 #define VCN_UMSCH_SPARE_REGISTER3__DATA__SHIFT 0x0 6009 #define VCN_UMSCH_SPARE_REGISTER3__DATA_MASK 0xFFFFFFFFL 6010 //VCN_UMSCH_SPARE_REGISTER4 6011 #define VCN_UMSCH_SPARE_REGISTER4__DATA__SHIFT 0x0 6012 #define VCN_UMSCH_SPARE_REGISTER4__DATA_MASK 0xFFFFFFFFL 6013 //VCN_UMSCH_SPARE_REGISTER5 6014 #define VCN_UMSCH_SPARE_REGISTER5__DATA__SHIFT 0x0 6015 #define VCN_UMSCH_SPARE_REGISTER5__DATA_MASK 0xFFFFFFFFL 6016 //VCN_UMSCH_SPARE_REGISTER6 6017 #define VCN_UMSCH_SPARE_REGISTER6__DATA__SHIFT 0x0 6018 #define VCN_UMSCH_SPARE_REGISTER6__DATA_MASK 0xFFFFFFFFL 6019 //VCN_UMSCH_SPARE_REGISTER7 6020 #define VCN_UMSCH_SPARE_REGISTER7__DATA__SHIFT 0x0 6021 #define VCN_UMSCH_SPARE_REGISTER7__DATA_MASK 0xFFFFFFFFL 6022 //VCN_UMSCH_MES_UTCL1_CNTL 6023 #define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY__SHIFT 0x0 6024 #define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop__SHIFT 0x14 6025 #define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode__SHIFT 0x15 6026 #define VCN_UMSCH_MES_UTCL1_CNTL__DropMode__SHIFT 0x16 6027 #define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate__SHIFT 0x17 6028 #define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY_MASK 0x000FFFFFL 6029 #define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop_MASK 0x00100000L 6030 #define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode_MASK 0x00200000L 6031 #define VCN_UMSCH_MES_UTCL1_CNTL__DropMode_MASK 0x00400000L 6032 #define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate_MASK 0x00800000L 6033 //VCN_UMSCH_MES_BUSY 6034 #define VCN_UMSCH_MES_BUSY__MesScratchRamBusy__SHIFT 0x0 6035 #define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy__SHIFT 0x1 6036 #define VCN_UMSCH_MES_BUSY__MesDataCacheBusy__SHIFT 0x2 6037 #define VCN_UMSCH_MES_BUSY__MesBusy__SHIFT 0x3 6038 #define VCN_UMSCH_MES_BUSY__MesLoadBusy__SHIFT 0x4 6039 #define VCN_UMSCH_MES_BUSY__MesMutexBusy__SHIFT 0x5 6040 #define VCN_UMSCH_MES_BUSY__MesThreadBusy__SHIFT 0x6 6041 #define VCN_UMSCH_MES_BUSY__MesMessageBusy__SHIFT 0x8 6042 #define VCN_UMSCH_MES_BUSY__MesTcBusy__SHIFT 0xa 6043 #define VCN_UMSCH_MES_BUSY__MesDmaPending__SHIFT 0xc 6044 #define VCN_UMSCH_MES_BUSY__MesScratchRamBusy_MASK 0x00000001L 6045 #define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy_MASK 0x00000002L 6046 #define VCN_UMSCH_MES_BUSY__MesDataCacheBusy_MASK 0x00000004L 6047 #define VCN_UMSCH_MES_BUSY__MesBusy_MASK 0x00000008L 6048 #define VCN_UMSCH_MES_BUSY__MesLoadBusy_MASK 0x00000010L 6049 #define VCN_UMSCH_MES_BUSY__MesMutexBusy_MASK 0x00000020L 6050 #define VCN_UMSCH_MES_BUSY__MesThreadBusy_MASK 0x000000C0L 6051 #define VCN_UMSCH_MES_BUSY__MesMessageBusy_MASK 0x00000300L 6052 #define VCN_UMSCH_MES_BUSY__MesTcBusy_MASK 0x00000C00L 6053 #define VCN_UMSCH_MES_BUSY__MesDmaPending_MASK 0x00003000L 6054 //VCN_UMSCH_RB_BASE_LO 6055 #define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 6056 #define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 6057 //VCN_UMSCH_RB_BASE_HI 6058 #define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 6059 #define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 6060 //VCN_UMSCH_RB_SIZE 6061 #define VCN_UMSCH_RB_SIZE__WPTR__SHIFT 0x4 6062 #define VCN_UMSCH_RB_SIZE__WPTR_MASK 0x007FFFF0L 6063 //VCN_UMSCH_RB_RPTR 6064 #define VCN_UMSCH_RB_RPTR__WPTR__SHIFT 0x4 6065 #define VCN_UMSCH_RB_RPTR__WPTR_MASK 0x007FFFF0L 6066 //VCN_UMSCH_RB_WPTR 6067 #define VCN_UMSCH_RB_WPTR__WPTR__SHIFT 0x4 6068 #define VCN_UMSCH_RB_WPTR__WPTR_MASK 0x007FFFF0L 6069 //VCN_UMSCH_MASTINT_EN 6070 #define VCN_UMSCH_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 6071 #define VCN_UMSCH_MASTINT_EN__SYS_EN__SHIFT 0x2 6072 #define VCN_UMSCH_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 6073 #define VCN_UMSCH_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 6074 #define VCN_UMSCH_MASTINT_EN__SYS_EN_MASK 0x00000004L 6075 #define VCN_UMSCH_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 6076 //VCN_UMSCH_IH_CTRL 6077 #define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 6078 #define VCN_UMSCH_IH_CTRL__IH_STALL_EN__SHIFT 0x1 6079 #define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 6080 #define VCN_UMSCH_IH_CTRL__IH_VMID__SHIFT 0x3 6081 #define VCN_UMSCH_IH_CTRL__IH_USER_DATA__SHIFT 0x7 6082 #define VCN_UMSCH_IH_CTRL__IH_RINGID__SHIFT 0x13 6083 #define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 6084 #define VCN_UMSCH_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 6085 #define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 6086 #define VCN_UMSCH_IH_CTRL__IH_VMID_MASK 0x00000078L 6087 #define VCN_UMSCH_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 6088 #define VCN_UMSCH_IH_CTRL__IH_RINGID_MASK 0x07F80000L 6089 //VCN_UMSCH_SYS_INT_EN 6090 #define VCN_UMSCH_SYS_INT_EN__INT0__SHIFT 0x0 6091 #define VCN_UMSCH_SYS_INT_EN__INT1__SHIFT 0x1 6092 #define VCN_UMSCH_SYS_INT_EN__INT2__SHIFT 0x2 6093 #define VCN_UMSCH_SYS_INT_EN__INT3__SHIFT 0x3 6094 #define VCN_UMSCH_SYS_INT_EN__INT4__SHIFT 0x4 6095 #define VCN_UMSCH_SYS_INT_EN__INT5__SHIFT 0x5 6096 #define VCN_UMSCH_SYS_INT_EN__INT6__SHIFT 0x6 6097 #define VCN_UMSCH_SYS_INT_EN__INT7__SHIFT 0x7 6098 #define VCN_UMSCH_SYS_INT_EN__INT0_MASK 0x00000001L 6099 #define VCN_UMSCH_SYS_INT_EN__INT1_MASK 0x00000002L 6100 #define VCN_UMSCH_SYS_INT_EN__INT2_MASK 0x00000004L 6101 #define VCN_UMSCH_SYS_INT_EN__INT3_MASK 0x00000008L 6102 #define VCN_UMSCH_SYS_INT_EN__INT4_MASK 0x00000010L 6103 #define VCN_UMSCH_SYS_INT_EN__INT5_MASK 0x00000020L 6104 #define VCN_UMSCH_SYS_INT_EN__INT6_MASK 0x00000040L 6105 #define VCN_UMSCH_SYS_INT_EN__INT7_MASK 0x00000080L 6106 //VCN_UMSCH_SYS_INT_STATUS 6107 #define VCN_UMSCH_SYS_INT_STATUS__INT0__SHIFT 0x0 6108 #define VCN_UMSCH_SYS_INT_STATUS__INT1__SHIFT 0x1 6109 #define VCN_UMSCH_SYS_INT_STATUS__INT2__SHIFT 0x2 6110 #define VCN_UMSCH_SYS_INT_STATUS__INT3__SHIFT 0x3 6111 #define VCN_UMSCH_SYS_INT_STATUS__INT4__SHIFT 0x4 6112 #define VCN_UMSCH_SYS_INT_STATUS__INT5__SHIFT 0x5 6113 #define VCN_UMSCH_SYS_INT_STATUS__INT6__SHIFT 0x6 6114 #define VCN_UMSCH_SYS_INT_STATUS__INT7__SHIFT 0x7 6115 #define VCN_UMSCH_SYS_INT_STATUS__INT0_MASK 0x00000001L 6116 #define VCN_UMSCH_SYS_INT_STATUS__INT1_MASK 0x00000002L 6117 #define VCN_UMSCH_SYS_INT_STATUS__INT2_MASK 0x00000004L 6118 #define VCN_UMSCH_SYS_INT_STATUS__INT3_MASK 0x00000008L 6119 #define VCN_UMSCH_SYS_INT_STATUS__INT4_MASK 0x00000010L 6120 #define VCN_UMSCH_SYS_INT_STATUS__INT5_MASK 0x00000020L 6121 #define VCN_UMSCH_SYS_INT_STATUS__INT6_MASK 0x00000040L 6122 #define VCN_UMSCH_SYS_INT_STATUS__INT7_MASK 0x00000080L 6123 //VCN_UMSCH_SYS_INT_ACK 6124 #define VCN_UMSCH_SYS_INT_ACK__INT0__SHIFT 0x0 6125 #define VCN_UMSCH_SYS_INT_ACK__INT1__SHIFT 0x1 6126 #define VCN_UMSCH_SYS_INT_ACK__INT2__SHIFT 0x2 6127 #define VCN_UMSCH_SYS_INT_ACK__INT3__SHIFT 0x3 6128 #define VCN_UMSCH_SYS_INT_ACK__INT4__SHIFT 0x4 6129 #define VCN_UMSCH_SYS_INT_ACK__INT5__SHIFT 0x5 6130 #define VCN_UMSCH_SYS_INT_ACK__INT6__SHIFT 0x6 6131 #define VCN_UMSCH_SYS_INT_ACK__INT7__SHIFT 0x7 6132 #define VCN_UMSCH_SYS_INT_ACK__INT0_MASK 0x00000001L 6133 #define VCN_UMSCH_SYS_INT_ACK__INT1_MASK 0x00000002L 6134 #define VCN_UMSCH_SYS_INT_ACK__INT2_MASK 0x00000004L 6135 #define VCN_UMSCH_SYS_INT_ACK__INT3_MASK 0x00000008L 6136 #define VCN_UMSCH_SYS_INT_ACK__INT4_MASK 0x00000010L 6137 #define VCN_UMSCH_SYS_INT_ACK__INT5_MASK 0x00000020L 6138 #define VCN_UMSCH_SYS_INT_ACK__INT6_MASK 0x00000040L 6139 #define VCN_UMSCH_SYS_INT_ACK__INT7_MASK 0x00000080L 6140 //VCN_UMSCH_SYS_INT_SRC 6141 #define VCN_UMSCH_SYS_INT_SRC__INT0__SHIFT 0x0 6142 #define VCN_UMSCH_SYS_INT_SRC__INT1__SHIFT 0x1 6143 #define VCN_UMSCH_SYS_INT_SRC__INT2__SHIFT 0x2 6144 #define VCN_UMSCH_SYS_INT_SRC__INT3__SHIFT 0x3 6145 #define VCN_UMSCH_SYS_INT_SRC__INT4__SHIFT 0x4 6146 #define VCN_UMSCH_SYS_INT_SRC__INT5__SHIFT 0x5 6147 #define VCN_UMSCH_SYS_INT_SRC__INT6__SHIFT 0x6 6148 #define VCN_UMSCH_SYS_INT_SRC__INT7__SHIFT 0x7 6149 #define VCN_UMSCH_SYS_INT_SRC__INT0_MASK 0x00000001L 6150 #define VCN_UMSCH_SYS_INT_SRC__INT1_MASK 0x00000002L 6151 #define VCN_UMSCH_SYS_INT_SRC__INT2_MASK 0x00000004L 6152 #define VCN_UMSCH_SYS_INT_SRC__INT3_MASK 0x00000008L 6153 #define VCN_UMSCH_SYS_INT_SRC__INT4_MASK 0x00000010L 6154 #define VCN_UMSCH_SYS_INT_SRC__INT5_MASK 0x00000020L 6155 #define VCN_UMSCH_SYS_INT_SRC__INT6_MASK 0x00000040L 6156 #define VCN_UMSCH_SYS_INT_SRC__INT7_MASK 0x00000080L 6157 //VCN_UMSCH_IH_CTX_CTRL 6158 #define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID__SHIFT 0x0 6159 #define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID_MASK 0x0FFFFFFFL 6160 //UVD_UMSCH_FORCE 6161 #define UVD_UMSCH_FORCE__IC_FORCE_GPUVM__SHIFT 0x0 6162 #define UVD_UMSCH_FORCE__DC_FORCE_GPUVM__SHIFT 0x1 6163 #define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE__SHIFT 0x2 6164 #define UVD_UMSCH_FORCE__FORCE_DROP_INT_DISABLE__SHIFT 0x3 6165 #define UVD_UMSCH_FORCE__BYPASS_UTCL2_ATC_AUTO_RESP__SHIFT 0x4 6166 #define UVD_UMSCH_FORCE__IC_FORCE_GPUVM_MASK 0x00000001L 6167 #define UVD_UMSCH_FORCE__DC_FORCE_GPUVM_MASK 0x00000002L 6168 #define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE_MASK 0x00000004L 6169 #define UVD_UMSCH_FORCE__FORCE_DROP_INT_DISABLE_MASK 0x00000008L 6170 #define UVD_UMSCH_FORCE__BYPASS_UTCL2_ATC_AUTO_RESP_MASK 0x00000010L 6171 //UMSCH_MES_RESET_CTRL 6172 #define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET__SHIFT 0x0 6173 #define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET_MASK 0x00000001L 6174 6175 6176 // addressBlock: uvd_vcn_cprs64dec 6177 //VCN_MES_PRGRM_CNTR_START 6178 #define VCN_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 6179 #define VCN_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL 6180 //VCN_MES_INTR_ROUTINE_START 6181 #define VCN_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 6182 #define VCN_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL 6183 //VCN_MES_MTVEC_LO 6184 #define VCN_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 6185 #define VCN_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL 6186 //VCN_MES_INTR_ROUTINE_START_HI 6187 #define VCN_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 6188 #define VCN_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL 6189 //VCN_MES_MTVEC_HI 6190 #define VCN_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 6191 #define VCN_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL 6192 //VCN_MES_CNTL 6193 #define VCN_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 6194 #define VCN_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 6195 #define VCN_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 6196 #define VCN_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 6197 #define VCN_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 6198 #define VCN_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a 6199 #define VCN_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b 6200 #define VCN_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c 6201 #define VCN_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d 6202 #define VCN_MES_CNTL__MES_HALT__SHIFT 0x1e 6203 #define VCN_MES_CNTL__MES_STEP__SHIFT 0x1f 6204 #define VCN_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L 6205 #define VCN_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L 6206 #define VCN_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L 6207 #define VCN_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L 6208 #define VCN_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L 6209 #define VCN_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L 6210 #define VCN_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L 6211 #define VCN_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L 6212 #define VCN_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L 6213 #define VCN_MES_CNTL__MES_HALT_MASK 0x40000000L 6214 #define VCN_MES_CNTL__MES_STEP_MASK 0x80000000L 6215 //VCN_MES_PIPE_PRIORITY_CNTS 6216 #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 6217 #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 6218 #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 6219 #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 6220 #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL 6221 #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L 6222 #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L 6223 #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L 6224 //VCN_MES_PIPE0_PRIORITY 6225 #define VCN_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 6226 #define VCN_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L 6227 //VCN_MES_PIPE1_PRIORITY 6228 #define VCN_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 6229 #define VCN_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L 6230 //VCN_MES_PIPE2_PRIORITY 6231 #define VCN_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 6232 #define VCN_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L 6233 //VCN_MES_PIPE3_PRIORITY 6234 #define VCN_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 6235 #define VCN_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L 6236 //VCN_MES_HEADER_DUMP 6237 #define VCN_MES_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 6238 #define VCN_MES_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL 6239 //VCN_MES_MIE_LO 6240 #define VCN_MES_MIE_LO__MES_INT__SHIFT 0x0 6241 #define VCN_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL 6242 //VCN_MES_MIE_HI 6243 #define VCN_MES_MIE_HI__MES_INT__SHIFT 0x0 6244 #define VCN_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL 6245 //VCN_MES_INTERRUPT 6246 #define VCN_MES_INTERRUPT__MES_INT__SHIFT 0x0 6247 #define VCN_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL 6248 //VCN_MES_SCRATCH_INDEX 6249 #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 6250 #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f 6251 #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL 6252 #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L 6253 //VCN_MES_SCRATCH_DATA 6254 #define VCN_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 6255 #define VCN_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL 6256 //VCN_MES_INSTR_PNTR 6257 #define VCN_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 6258 #define VCN_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL 6259 //VCN_MES_MSCRATCH_HI 6260 #define VCN_MES_MSCRATCH_HI__DATA__SHIFT 0x0 6261 #define VCN_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL 6262 //VCN_MES_MSCRATCH_LO 6263 #define VCN_MES_MSCRATCH_LO__DATA__SHIFT 0x0 6264 #define VCN_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL 6265 //VCN_MES_MSTATUS_LO 6266 #define VCN_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 6267 #define VCN_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL 6268 //VCN_MES_MSTATUS_HI 6269 #define VCN_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 6270 #define VCN_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL 6271 //VCN_MES_MEPC_LO 6272 #define VCN_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 6273 #define VCN_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL 6274 //VCN_MES_MEPC_HI 6275 #define VCN_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 6276 #define VCN_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL 6277 //VCN_MES_MCAUSE_LO 6278 #define VCN_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 6279 #define VCN_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL 6280 //VCN_MES_MCAUSE_HI 6281 #define VCN_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 6282 #define VCN_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL 6283 //VCN_MES_MBADADDR_LO 6284 #define VCN_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 6285 #define VCN_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL 6286 //VCN_MES_MBADADDR_HI 6287 #define VCN_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 6288 #define VCN_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL 6289 //VCN_MES_MIP_LO 6290 #define VCN_MES_MIP_LO__MIP_LO__SHIFT 0x0 6291 #define VCN_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL 6292 //VCN_MES_MIP_HI 6293 #define VCN_MES_MIP_HI__MIP_HI__SHIFT 0x0 6294 #define VCN_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL 6295 //VCN_MES_IC_OP_CNTL 6296 #define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 6297 #define VCN_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 6298 #define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 6299 #define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L 6300 #define VCN_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L 6301 #define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L 6302 //VCN_MES_MCYCLE_LO 6303 #define VCN_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 6304 #define VCN_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL 6305 //VCN_MES_MCYCLE_HI 6306 #define VCN_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 6307 #define VCN_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL 6308 //VCN_MES_MTIME_LO 6309 #define VCN_MES_MTIME_LO__TIME_LO__SHIFT 0x0 6310 #define VCN_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL 6311 //VCN_MES_MTIME_HI 6312 #define VCN_MES_MTIME_HI__TIME_HI__SHIFT 0x0 6313 #define VCN_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL 6314 //VCN_MES_MINSTRET_LO 6315 #define VCN_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 6316 #define VCN_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL 6317 //VCN_MES_MINSTRET_HI 6318 #define VCN_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 6319 #define VCN_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL 6320 //VCN_MES_MISA_LO 6321 #define VCN_MES_MISA_LO__MISA_LO__SHIFT 0x0 6322 #define VCN_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL 6323 //VCN_MES_MISA_HI 6324 #define VCN_MES_MISA_HI__MISA_HI__SHIFT 0x0 6325 #define VCN_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL 6326 //VCN_MES_MVENDORID_LO 6327 #define VCN_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 6328 #define VCN_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL 6329 //VCN_MES_MVENDORID_HI 6330 #define VCN_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 6331 #define VCN_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL 6332 //VCN_MES_MARCHID_LO 6333 #define VCN_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 6334 #define VCN_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL 6335 //VCN_MES_MARCHID_HI 6336 #define VCN_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 6337 #define VCN_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL 6338 //VCN_MES_MIMPID_LO 6339 #define VCN_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 6340 #define VCN_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL 6341 //VCN_MES_MIMPID_HI 6342 #define VCN_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 6343 #define VCN_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL 6344 //VCN_MES_MHARTID_LO 6345 #define VCN_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 6346 #define VCN_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL 6347 //VCN_MES_MHARTID_HI 6348 #define VCN_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 6349 #define VCN_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL 6350 //VCN_MES_DC_BASE_CNTL 6351 #define VCN_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 6352 #define VCN_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 6353 #define VCN_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL 6354 #define VCN_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L 6355 //VCN_MES_DC_OP_CNTL 6356 #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 6357 #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 6358 #define VCN_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 6359 #define VCN_MES_DC_OP_CNTL__DEPRECATED__SHIFT 0x3 6360 #define VCN_MES_DC_OP_CNTL__DEPRACATED__SHIFT 0x4 6361 #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L 6362 #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L 6363 #define VCN_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L 6364 #define VCN_MES_DC_OP_CNTL__DEPRECATED_MASK 0x00000008L 6365 #define VCN_MES_DC_OP_CNTL__DEPRACATED_MASK 0x00000010L 6366 //VCN_MES_MTIMECMP_LO 6367 #define VCN_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 6368 #define VCN_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL 6369 //VCN_MES_MTIMECMP_HI 6370 #define VCN_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 6371 #define VCN_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL 6372 //VCN_MES_GP0_LO 6373 #define VCN_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 6374 #define VCN_MES_GP0_LO__DATA__SHIFT 0x1 6375 #define VCN_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L 6376 #define VCN_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL 6377 //VCN_MES_GP0_HI 6378 #define VCN_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 6379 #define VCN_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL 6380 //VCN_MES_GP1_LO 6381 #define VCN_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 6382 #define VCN_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL 6383 //VCN_MES_GP1_HI 6384 #define VCN_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 6385 #define VCN_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL 6386 //VCN_MES_GP2_LO 6387 #define VCN_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 6388 #define VCN_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL 6389 //VCN_MES_GP2_HI 6390 #define VCN_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 6391 #define VCN_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL 6392 //VCN_MES_GP3_LO 6393 #define VCN_MES_GP3_LO__DATA__SHIFT 0x0 6394 #define VCN_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL 6395 //VCN_MES_GP3_HI 6396 #define VCN_MES_GP3_HI__DATA__SHIFT 0x0 6397 #define VCN_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL 6398 //VCN_MES_GP4_LO 6399 #define VCN_MES_GP4_LO__DATA__SHIFT 0x0 6400 #define VCN_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL 6401 //VCN_MES_GP4_HI 6402 #define VCN_MES_GP4_HI__DATA__SHIFT 0x0 6403 #define VCN_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL 6404 //VCN_MES_GP5_LO 6405 #define VCN_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 6406 #define VCN_MES_GP5_LO__DATA__SHIFT 0x1 6407 #define VCN_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L 6408 #define VCN_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL 6409 //VCN_MES_GP5_HI 6410 #define VCN_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 6411 #define VCN_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL 6412 //VCN_MES_GP6_LO 6413 #define VCN_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 6414 #define VCN_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL 6415 //VCN_MES_GP6_HI 6416 #define VCN_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 6417 #define VCN_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL 6418 //VCN_MES_GP7_LO 6419 #define VCN_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 6420 #define VCN_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL 6421 //VCN_MES_GP7_HI 6422 #define VCN_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 6423 #define VCN_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL 6424 //VCN_MES_GP8_LO 6425 #define VCN_MES_GP8_LO__DATA__SHIFT 0x0 6426 #define VCN_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL 6427 //VCN_MES_GP8_HI 6428 #define VCN_MES_GP8_HI__DATA__SHIFT 0x0 6429 #define VCN_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL 6430 //VCN_MES_GP9_LO 6431 #define VCN_MES_GP9_LO__DATA__SHIFT 0x0 6432 #define VCN_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL 6433 //VCN_MES_GP9_HI 6434 #define VCN_MES_GP9_HI__DATA__SHIFT 0x0 6435 #define VCN_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL 6436 //VCN_MES_DM_INDEX_ADDR 6437 #define VCN_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 6438 #define VCN_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL 6439 //VCN_MES_DM_INDEX_DATA 6440 #define VCN_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 6441 #define VCN_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL 6442 //VCN_MES_LOCAL_BASE0_LO 6443 #define VCN_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 6444 #define VCN_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L 6445 //VCN_MES_LOCAL_BASE0_HI 6446 #define VCN_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 6447 #define VCN_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL 6448 //VCN_MES_LOCAL_MASK0_LO 6449 #define VCN_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 6450 #define VCN_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L 6451 //VCN_MES_LOCAL_MASK0_HI 6452 #define VCN_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 6453 #define VCN_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL 6454 //VCN_MES_LOCAL_APERTURE 6455 #define VCN_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 6456 #define VCN_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L 6457 //VCN_MES_LOCAL_INSTR_BASE_LO 6458 #define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 6459 #define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L 6460 //VCN_MES_LOCAL_INSTR_BASE_HI 6461 #define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 6462 #define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL 6463 //VCN_MES_LOCAL_INSTR_MASK_LO 6464 #define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 6465 #define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L 6466 //VCN_MES_LOCAL_INSTR_MASK_HI 6467 #define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 6468 #define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL 6469 //VCN_MES_LOCAL_INSTR_APERTURE 6470 #define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 6471 #define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L 6472 //VCN_MES_LOCAL_SCRATCH_APERTURE 6473 #define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 6474 #define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L 6475 //VCN_MES_LOCAL_SCRATCH_BASE_LO 6476 #define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 6477 #define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L 6478 //VCN_MES_LOCAL_SCRATCH_BASE_HI 6479 #define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 6480 #define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL 6481 //VCN_MES_PERFCOUNT_CNTL 6482 #define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 6483 #define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL 6484 //VCN_MES_PENDING_INTERRUPT 6485 #define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 6486 #define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL 6487 //VCN_MES_PRGRM_CNTR_START_HI 6488 #define VCN_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 6489 #define VCN_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL 6490 //VCN_MES_INTERRUPT_DATA_16 6491 #define VCN_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0 6492 #define VCN_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL 6493 //VCN_MES_INTERRUPT_DATA_17 6494 #define VCN_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0 6495 #define VCN_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL 6496 //VCN_MES_INTERRUPT_DATA_18 6497 #define VCN_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0 6498 #define VCN_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL 6499 //VCN_MES_INTERRUPT_DATA_19 6500 #define VCN_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0 6501 #define VCN_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL 6502 //VCN_MES_INTERRUPT_DATA_20 6503 #define VCN_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0 6504 #define VCN_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL 6505 //VCN_MES_INTERRUPT_DATA_21 6506 #define VCN_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0 6507 #define VCN_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL 6508 //VCN_MES_INTERRUPT_DATA_22 6509 #define VCN_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0 6510 #define VCN_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL 6511 //VCN_MES_INTERRUPT_DATA_23 6512 #define VCN_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0 6513 #define VCN_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL 6514 //VCN_MES_INTERRUPT_DATA_24 6515 #define VCN_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0 6516 #define VCN_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL 6517 //VCN_MES_INTERRUPT_DATA_25 6518 #define VCN_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0 6519 #define VCN_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL 6520 //VCN_MES_INTERRUPT_DATA_26 6521 #define VCN_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0 6522 #define VCN_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL 6523 //VCN_MES_INTERRUPT_DATA_27 6524 #define VCN_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0 6525 #define VCN_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL 6526 //VCN_MES_INTERRUPT_DATA_28 6527 #define VCN_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0 6528 #define VCN_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL 6529 //VCN_MES_INTERRUPT_DATA_29 6530 #define VCN_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0 6531 #define VCN_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL 6532 //VCN_MES_INTERRUPT_DATA_30 6533 #define VCN_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0 6534 #define VCN_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL 6535 //VCN_MES_INTERRUPT_DATA_31 6536 #define VCN_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0 6537 #define VCN_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL 6538 //VCN_MES_DC_APERTURE0_BASE 6539 #define VCN_MES_DC_APERTURE0_BASE__BASE__SHIFT 0x0 6540 #define VCN_MES_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL 6541 //VCN_MES_DC_APERTURE0_MASK 6542 #define VCN_MES_DC_APERTURE0_MASK__MASK__SHIFT 0x0 6543 #define VCN_MES_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL 6544 //VCN_MES_DC_APERTURE0_CNTL 6545 #define VCN_MES_DC_APERTURE0_CNTL__VMID__SHIFT 0x0 6546 #define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4 6547 #define VCN_MES_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL 6548 #define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L 6549 //VCN_MES_DC_APERTURE1_BASE 6550 #define VCN_MES_DC_APERTURE1_BASE__BASE__SHIFT 0x0 6551 #define VCN_MES_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL 6552 //VCN_MES_DC_APERTURE1_MASK 6553 #define VCN_MES_DC_APERTURE1_MASK__MASK__SHIFT 0x0 6554 #define VCN_MES_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL 6555 //VCN_MES_DC_APERTURE1_CNTL 6556 #define VCN_MES_DC_APERTURE1_CNTL__VMID__SHIFT 0x0 6557 #define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4 6558 #define VCN_MES_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL 6559 #define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L 6560 //VCN_MES_DC_APERTURE2_BASE 6561 #define VCN_MES_DC_APERTURE2_BASE__BASE__SHIFT 0x0 6562 #define VCN_MES_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL 6563 //VCN_MES_DC_APERTURE2_MASK 6564 #define VCN_MES_DC_APERTURE2_MASK__MASK__SHIFT 0x0 6565 #define VCN_MES_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL 6566 //VCN_MES_DC_APERTURE2_CNTL 6567 #define VCN_MES_DC_APERTURE2_CNTL__VMID__SHIFT 0x0 6568 #define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4 6569 #define VCN_MES_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL 6570 #define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L 6571 //VCN_MES_DC_APERTURE3_BASE 6572 #define VCN_MES_DC_APERTURE3_BASE__BASE__SHIFT 0x0 6573 #define VCN_MES_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL 6574 //VCN_MES_DC_APERTURE3_MASK 6575 #define VCN_MES_DC_APERTURE3_MASK__MASK__SHIFT 0x0 6576 #define VCN_MES_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL 6577 //VCN_MES_DC_APERTURE3_CNTL 6578 #define VCN_MES_DC_APERTURE3_CNTL__VMID__SHIFT 0x0 6579 #define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4 6580 #define VCN_MES_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL 6581 #define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L 6582 //VCN_MES_DC_APERTURE4_BASE 6583 #define VCN_MES_DC_APERTURE4_BASE__BASE__SHIFT 0x0 6584 #define VCN_MES_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL 6585 //VCN_MES_DC_APERTURE4_MASK 6586 #define VCN_MES_DC_APERTURE4_MASK__MASK__SHIFT 0x0 6587 #define VCN_MES_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL 6588 //VCN_MES_DC_APERTURE4_CNTL 6589 #define VCN_MES_DC_APERTURE4_CNTL__VMID__SHIFT 0x0 6590 #define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4 6591 #define VCN_MES_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL 6592 #define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L 6593 //VCN_MES_DC_APERTURE5_BASE 6594 #define VCN_MES_DC_APERTURE5_BASE__BASE__SHIFT 0x0 6595 #define VCN_MES_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL 6596 //VCN_MES_DC_APERTURE5_MASK 6597 #define VCN_MES_DC_APERTURE5_MASK__MASK__SHIFT 0x0 6598 #define VCN_MES_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL 6599 //VCN_MES_DC_APERTURE5_CNTL 6600 #define VCN_MES_DC_APERTURE5_CNTL__VMID__SHIFT 0x0 6601 #define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4 6602 #define VCN_MES_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL 6603 #define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L 6604 //VCN_MES_DC_APERTURE6_BASE 6605 #define VCN_MES_DC_APERTURE6_BASE__BASE__SHIFT 0x0 6606 #define VCN_MES_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL 6607 //VCN_MES_DC_APERTURE6_MASK 6608 #define VCN_MES_DC_APERTURE6_MASK__MASK__SHIFT 0x0 6609 #define VCN_MES_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL 6610 //VCN_MES_DC_APERTURE6_CNTL 6611 #define VCN_MES_DC_APERTURE6_CNTL__VMID__SHIFT 0x0 6612 #define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4 6613 #define VCN_MES_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL 6614 #define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L 6615 //VCN_MES_DC_APERTURE7_BASE 6616 #define VCN_MES_DC_APERTURE7_BASE__BASE__SHIFT 0x0 6617 #define VCN_MES_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL 6618 //VCN_MES_DC_APERTURE7_MASK 6619 #define VCN_MES_DC_APERTURE7_MASK__MASK__SHIFT 0x0 6620 #define VCN_MES_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL 6621 //VCN_MES_DC_APERTURE7_CNTL 6622 #define VCN_MES_DC_APERTURE7_CNTL__VMID__SHIFT 0x0 6623 #define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4 6624 #define VCN_MES_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL 6625 #define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L 6626 //VCN_MES_DC_APERTURE8_BASE 6627 #define VCN_MES_DC_APERTURE8_BASE__BASE__SHIFT 0x0 6628 #define VCN_MES_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL 6629 //VCN_MES_DC_APERTURE8_MASK 6630 #define VCN_MES_DC_APERTURE8_MASK__MASK__SHIFT 0x0 6631 #define VCN_MES_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL 6632 //VCN_MES_DC_APERTURE8_CNTL 6633 #define VCN_MES_DC_APERTURE8_CNTL__VMID__SHIFT 0x0 6634 #define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4 6635 #define VCN_MES_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL 6636 #define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L 6637 //VCN_MES_DC_APERTURE9_BASE 6638 #define VCN_MES_DC_APERTURE9_BASE__BASE__SHIFT 0x0 6639 #define VCN_MES_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL 6640 //VCN_MES_DC_APERTURE9_MASK 6641 #define VCN_MES_DC_APERTURE9_MASK__MASK__SHIFT 0x0 6642 #define VCN_MES_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL 6643 //VCN_MES_DC_APERTURE9_CNTL 6644 #define VCN_MES_DC_APERTURE9_CNTL__VMID__SHIFT 0x0 6645 #define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4 6646 #define VCN_MES_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL 6647 #define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L 6648 //VCN_MES_DC_APERTURE10_BASE 6649 #define VCN_MES_DC_APERTURE10_BASE__BASE__SHIFT 0x0 6650 #define VCN_MES_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL 6651 //VCN_MES_DC_APERTURE10_MASK 6652 #define VCN_MES_DC_APERTURE10_MASK__MASK__SHIFT 0x0 6653 #define VCN_MES_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL 6654 //VCN_MES_DC_APERTURE10_CNTL 6655 #define VCN_MES_DC_APERTURE10_CNTL__VMID__SHIFT 0x0 6656 #define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4 6657 #define VCN_MES_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL 6658 #define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L 6659 //VCN_MES_DC_APERTURE11_BASE 6660 #define VCN_MES_DC_APERTURE11_BASE__BASE__SHIFT 0x0 6661 #define VCN_MES_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL 6662 //VCN_MES_DC_APERTURE11_MASK 6663 #define VCN_MES_DC_APERTURE11_MASK__MASK__SHIFT 0x0 6664 #define VCN_MES_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL 6665 //VCN_MES_DC_APERTURE11_CNTL 6666 #define VCN_MES_DC_APERTURE11_CNTL__VMID__SHIFT 0x0 6667 #define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4 6668 #define VCN_MES_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL 6669 #define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L 6670 //VCN_MES_DC_APERTURE12_BASE 6671 #define VCN_MES_DC_APERTURE12_BASE__BASE__SHIFT 0x0 6672 #define VCN_MES_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL 6673 //VCN_MES_DC_APERTURE12_MASK 6674 #define VCN_MES_DC_APERTURE12_MASK__MASK__SHIFT 0x0 6675 #define VCN_MES_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL 6676 //VCN_MES_DC_APERTURE12_CNTL 6677 #define VCN_MES_DC_APERTURE12_CNTL__VMID__SHIFT 0x0 6678 #define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4 6679 #define VCN_MES_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL 6680 #define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L 6681 //VCN_MES_DC_APERTURE13_BASE 6682 #define VCN_MES_DC_APERTURE13_BASE__BASE__SHIFT 0x0 6683 #define VCN_MES_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL 6684 //VCN_MES_DC_APERTURE13_MASK 6685 #define VCN_MES_DC_APERTURE13_MASK__MASK__SHIFT 0x0 6686 #define VCN_MES_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL 6687 //VCN_MES_DC_APERTURE13_CNTL 6688 #define VCN_MES_DC_APERTURE13_CNTL__VMID__SHIFT 0x0 6689 #define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4 6690 #define VCN_MES_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL 6691 #define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L 6692 //VCN_MES_DC_APERTURE14_BASE 6693 #define VCN_MES_DC_APERTURE14_BASE__BASE__SHIFT 0x0 6694 #define VCN_MES_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL 6695 //VCN_MES_DC_APERTURE14_MASK 6696 #define VCN_MES_DC_APERTURE14_MASK__MASK__SHIFT 0x0 6697 #define VCN_MES_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL 6698 //VCN_MES_DC_APERTURE14_CNTL 6699 #define VCN_MES_DC_APERTURE14_CNTL__VMID__SHIFT 0x0 6700 #define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4 6701 #define VCN_MES_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL 6702 #define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L 6703 //VCN_MES_DC_APERTURE15_BASE 6704 #define VCN_MES_DC_APERTURE15_BASE__BASE__SHIFT 0x0 6705 #define VCN_MES_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL 6706 //VCN_MES_DC_APERTURE15_MASK 6707 #define VCN_MES_DC_APERTURE15_MASK__MASK__SHIFT 0x0 6708 #define VCN_MES_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL 6709 //VCN_MES_DC_APERTURE15_CNTL 6710 #define VCN_MES_DC_APERTURE15_CNTL__VMID__SHIFT 0x0 6711 #define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4 6712 #define VCN_MES_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL 6713 #define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L 6714 6715 6716 // addressBlock: uvd_vcn_hypdec 6717 //VCN_MES_IC_BASE_LO 6718 #define VCN_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc 6719 #define VCN_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L 6720 //VCN_MES_MIBASE_LO 6721 #define VCN_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc 6722 #define VCN_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L 6723 //VCN_MES_IC_BASE_HI 6724 #define VCN_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 6725 #define VCN_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL 6726 //VCN_MES_MIBASE_HI 6727 #define VCN_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 6728 #define VCN_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL 6729 //VCN_MES_IC_BASE_CNTL 6730 #define VCN_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 6731 #define VCN_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 6732 #define VCN_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 6733 #define VCN_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL 6734 #define VCN_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L 6735 #define VCN_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L 6736 //VCN_MES_DC_BASE_LO 6737 #define VCN_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 6738 #define VCN_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L 6739 //VCN_MES_MDBASE_LO 6740 #define VCN_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 6741 #define VCN_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L 6742 //VCN_MES_DC_BASE_HI 6743 #define VCN_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 6744 #define VCN_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL 6745 //VCN_MES_MDBASE_HI 6746 #define VCN_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 6747 #define VCN_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL 6748 //VCN_MES_MIBOUND_LO 6749 #define VCN_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 6750 #define VCN_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL 6751 //VCN_MES_MIBOUND_HI 6752 #define VCN_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 6753 #define VCN_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL 6754 //VCN_MES_MDBOUND_LO 6755 #define VCN_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 6756 #define VCN_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL 6757 //VCN_MES_MDBOUND_HI 6758 #define VCN_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 6759 #define VCN_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL 6760 6761 6762 // addressBlock: uvd_slmi_adpdec 6763 //UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 6764 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6765 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6766 //UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 6767 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6768 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6769 //UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 6770 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6771 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6772 //UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 6773 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6774 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6775 //UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 6776 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6777 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6778 //UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 6779 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6780 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6781 //UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 6782 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6783 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6784 //UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 6785 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6786 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6787 //UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 6788 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6789 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6790 //UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 6791 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6792 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6793 //UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 6794 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6795 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6796 //UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 6797 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6798 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6799 //UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 6800 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6801 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6802 //UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 6803 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6804 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6805 //UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 6806 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6807 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6808 //UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 6809 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6810 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6811 //UVD_LMI_MMSCH_NC_VMID 6812 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 6813 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 6814 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 6815 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 6816 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 6817 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 6818 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 6819 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 6820 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 6821 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 6822 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 6823 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 6824 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 6825 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 6826 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 6827 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 6828 //UVD_LMI_MMSCH_CTRL 6829 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 6830 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 6831 #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 6832 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 6833 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 6834 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 6835 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 6836 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 6837 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 6838 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 6839 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 6840 #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L 6841 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 6842 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 6843 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 6844 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 6845 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 6846 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 6847 //UVD_MMSCH_LMI_STATUS 6848 #define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_LEN_INT__SHIFT 0x0 6849 #define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0x1 6850 #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 6851 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_LEN__SHIFT 0x4 6852 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_ADDR_LSBS__SHIFT 0x8 6853 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_AWRITE__SHIFT 0xc 6854 #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd 6855 #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe 6856 #define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_LEN_INT_MASK 0x00000001L 6857 #define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00000002L 6858 #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L 6859 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_LEN_MASK 0x000000F0L 6860 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_ADDR_LSBS_MASK 0x00000700L 6861 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_AWRITE_MASK 0x00001000L 6862 #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L 6863 #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L 6864 //UMSCH_IOV_ACTIVE_FCN_ID 6865 #define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 6866 #define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f 6867 #define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000003FL 6868 #define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L 6869 //UVD_UMSCH_LMI_STATUS 6870 #define UVD_UMSCH_LMI_STATUS__UMSCHIC_RD_CLEAN__SHIFT 0x0 6871 #define UVD_UMSCH_LMI_STATUS__UMSCHDC_RD_CLEAN__SHIFT 0x1 6872 #define UVD_UMSCH_LMI_STATUS__UMSCHDC_WR_CLEAN__SHIFT 0x2 6873 #define UVD_UMSCH_LMI_STATUS__UMSCHIC_RD_CLEAN_MASK 0x00000001L 6874 #define UVD_UMSCH_LMI_STATUS__UMSCHDC_RD_CLEAN_MASK 0x00000002L 6875 #define UVD_UMSCH_LMI_STATUS__UMSCHDC_WR_CLEAN_MASK 0x00000004L 6876 6877 6878 // addressBlock: uvdctxind 6879 //UVD_CGC_MEM_CTRL 6880 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 6881 #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 6882 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 6883 #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 6884 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 6885 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 6886 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 6887 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 6888 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 6889 #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 6890 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 6891 #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 6892 #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 6893 #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN__SHIFT 0xe 6894 #define UVD_CGC_MEM_CTRL__MPC1_LS_EN__SHIFT 0xf 6895 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 6896 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 6897 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L 6898 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L 6899 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L 6900 #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L 6901 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L 6902 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L 6903 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L 6904 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L 6905 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L 6906 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L 6907 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L 6908 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L 6909 #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L 6910 #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN_MASK 0x00004000L 6911 #define UVD_CGC_MEM_CTRL__MPC1_LS_EN_MASK 0x00008000L 6912 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 6913 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 6914 //UVD_CGC_CTRL2 6915 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 6916 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 6917 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 6918 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L 6919 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L 6920 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001CL 6921 //UVD_CGC_MEM_DS_CTRL 6922 #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN__SHIFT 0x0 6923 #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN__SHIFT 0x1 6924 #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN__SHIFT 0x2 6925 #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN__SHIFT 0x3 6926 #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN__SHIFT 0x4 6927 #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN__SHIFT 0x5 6928 #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN__SHIFT 0x6 6929 #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN__SHIFT 0x7 6930 #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN__SHIFT 0x8 6931 #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN__SHIFT 0x9 6932 #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa 6933 #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN__SHIFT 0xc 6934 #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN__SHIFT 0xd 6935 #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN__SHIFT 0xe 6936 #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN__SHIFT 0xf 6937 #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN_MASK 0x00000001L 6938 #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN_MASK 0x00000002L 6939 #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN_MASK 0x00000004L 6940 #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN_MASK 0x00000008L 6941 #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN_MASK 0x00000010L 6942 #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN_MASK 0x00000020L 6943 #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN_MASK 0x00000040L 6944 #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN_MASK 0x00000080L 6945 #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN_MASK 0x00000100L 6946 #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN_MASK 0x00000200L 6947 #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN_MASK 0x00000400L 6948 #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN_MASK 0x00001000L 6949 #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN_MASK 0x00002000L 6950 #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN_MASK 0x00004000L 6951 #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN_MASK 0x00008000L 6952 //UVD_CGC_MEM_SD_CTRL 6953 #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN__SHIFT 0x0 6954 #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN__SHIFT 0x1 6955 #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN__SHIFT 0x2 6956 #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN__SHIFT 0x3 6957 #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN__SHIFT 0x4 6958 #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN__SHIFT 0x5 6959 #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN__SHIFT 0x6 6960 #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN__SHIFT 0x7 6961 #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN__SHIFT 0x8 6962 #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN__SHIFT 0x9 6963 #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xa 6964 #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN__SHIFT 0xc 6965 #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN__SHIFT 0xd 6966 #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN__SHIFT 0xe 6967 #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN__SHIFT 0xf 6968 #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN_MASK 0x00000001L 6969 #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN_MASK 0x00000002L 6970 #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN_MASK 0x00000004L 6971 #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN_MASK 0x00000008L 6972 #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN_MASK 0x00000010L 6973 #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN_MASK 0x00000020L 6974 #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN_MASK 0x00000040L 6975 #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN_MASK 0x00000080L 6976 #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN_MASK 0x00000100L 6977 #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN_MASK 0x00000200L 6978 #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN_MASK 0x00000400L 6979 #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN_MASK 0x00001000L 6980 #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN_MASK 0x00002000L 6981 #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN_MASK 0x00004000L 6982 #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN_MASK 0x00008000L 6983 //UVD_SW_SCRATCH_00 6984 #define UVD_SW_SCRATCH_00__DATA__SHIFT 0x0 6985 #define UVD_SW_SCRATCH_00__DATA_MASK 0xFFFFFFFFL 6986 //UVD_SW_SCRATCH_01 6987 #define UVD_SW_SCRATCH_01__DATA__SHIFT 0x0 6988 #define UVD_SW_SCRATCH_01__DATA_MASK 0xFFFFFFFFL 6989 //UVD_SW_SCRATCH_02 6990 #define UVD_SW_SCRATCH_02__DATA__SHIFT 0x0 6991 #define UVD_SW_SCRATCH_02__DATA_MASK 0xFFFFFFFFL 6992 //UVD_SW_SCRATCH_03 6993 #define UVD_SW_SCRATCH_03__DATA__SHIFT 0x0 6994 #define UVD_SW_SCRATCH_03__DATA_MASK 0xFFFFFFFFL 6995 //UVD_SW_SCRATCH_04 6996 #define UVD_SW_SCRATCH_04__DATA__SHIFT 0x0 6997 #define UVD_SW_SCRATCH_04__DATA_MASK 0xFFFFFFFFL 6998 //UVD_SW_SCRATCH_05 6999 #define UVD_SW_SCRATCH_05__DATA__SHIFT 0x0 7000 #define UVD_SW_SCRATCH_05__DATA_MASK 0xFFFFFFFFL 7001 //UVD_SW_SCRATCH_06 7002 #define UVD_SW_SCRATCH_06__DATA__SHIFT 0x0 7003 #define UVD_SW_SCRATCH_06__DATA_MASK 0xFFFFFFFFL 7004 //UVD_SW_SCRATCH_07 7005 #define UVD_SW_SCRATCH_07__DATA__SHIFT 0x0 7006 #define UVD_SW_SCRATCH_07__DATA_MASK 0xFFFFFFFFL 7007 //UVD_SW_SCRATCH_08 7008 #define UVD_SW_SCRATCH_08__DATA__SHIFT 0x0 7009 #define UVD_SW_SCRATCH_08__DATA_MASK 0xFFFFFFFFL 7010 //UVD_SW_SCRATCH_09 7011 #define UVD_SW_SCRATCH_09__DATA__SHIFT 0x0 7012 #define UVD_SW_SCRATCH_09__DATA_MASK 0xFFFFFFFFL 7013 //UVD_SW_SCRATCH_10 7014 #define UVD_SW_SCRATCH_10__DATA__SHIFT 0x0 7015 #define UVD_SW_SCRATCH_10__DATA_MASK 0xFFFFFFFFL 7016 //UVD_SW_SCRATCH_11 7017 #define UVD_SW_SCRATCH_11__DATA__SHIFT 0x0 7018 #define UVD_SW_SCRATCH_11__DATA_MASK 0xFFFFFFFFL 7019 //UVD_SW_SCRATCH_12 7020 #define UVD_SW_SCRATCH_12__DATA__SHIFT 0x0 7021 #define UVD_SW_SCRATCH_12__DATA_MASK 0xFFFFFFFFL 7022 //UVD_SW_SCRATCH_13 7023 #define UVD_SW_SCRATCH_13__DATA__SHIFT 0x0 7024 #define UVD_SW_SCRATCH_13__DATA_MASK 0xFFFFFFFFL 7025 //UVD_SW_SCRATCH_14 7026 #define UVD_SW_SCRATCH_14__DATA__SHIFT 0x0 7027 #define UVD_SW_SCRATCH_14__DATA_MASK 0xFFFFFFFFL 7028 //UVD_SW_SCRATCH_15 7029 #define UVD_SW_SCRATCH_15__DATA__SHIFT 0x0 7030 #define UVD_SW_SCRATCH_15__DATA_MASK 0xFFFFFFFFL 7031 //UVD_IH_SEM_CTRL 7032 #define UVD_IH_SEM_CTRL__IH_STALL_EN__SHIFT 0x0 7033 #define UVD_IH_SEM_CTRL__SEM_STALL_EN__SHIFT 0x1 7034 #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 7035 #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN__SHIFT 0x3 7036 #define UVD_IH_SEM_CTRL__IH_VMID__SHIFT 0x4 7037 #define UVD_IH_SEM_CTRL__IH_USER_DATA__SHIFT 0x8 7038 #define UVD_IH_SEM_CTRL__IH_RINGID__SHIFT 0x14 7039 #define UVD_IH_SEM_CTRL__IH_STALL_EN_MASK 0x00000001L 7040 #define UVD_IH_SEM_CTRL__SEM_STALL_EN_MASK 0x00000002L 7041 #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 7042 #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN_MASK 0x00000008L 7043 #define UVD_IH_SEM_CTRL__IH_VMID_MASK 0x000000F0L 7044 #define UVD_IH_SEM_CTRL__IH_USER_DATA_MASK 0x000FFF00L 7045 #define UVD_IH_SEM_CTRL__IH_RINGID_MASK 0x0FF00000L 7046 //UVD_MISC_FEATURE_CTL 7047 #define UVD_MISC_FEATURE_CTL__ROW_PREEMPT_EN__SHIFT 0x0 7048 #define UVD_MISC_FEATURE_CTL__PREEMPT_BLOCKIF_DIS_EN__SHIFT 0x1 7049 #define UVD_MISC_FEATURE_CTL__ROW_PREEMPT_EN_MASK 0x00000001L 7050 #define UVD_MISC_FEATURE_CTL__PREEMPT_BLOCKIF_DIS_EN_MASK 0x00000002L 7051 7052 7053 // addressBlock: lmi_adp_indirect 7054 //UVD_LMI_CRC0 7055 #define UVD_LMI_CRC0__CRC32__SHIFT 0x0 7056 #define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL 7057 //UVD_LMI_CRC1 7058 #define UVD_LMI_CRC1__CRC32__SHIFT 0x0 7059 #define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL 7060 //UVD_LMI_CRC2 7061 #define UVD_LMI_CRC2__CRC32__SHIFT 0x0 7062 #define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL 7063 //UVD_LMI_CRC3 7064 #define UVD_LMI_CRC3__CRC32__SHIFT 0x0 7065 #define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL 7066 //UVD_LMI_CRC10 7067 #define UVD_LMI_CRC10__CRC32__SHIFT 0x0 7068 #define UVD_LMI_CRC10__CRC32_MASK 0xFFFFFFFFL 7069 //UVD_LMI_CRC11 7070 #define UVD_LMI_CRC11__CRC32__SHIFT 0x0 7071 #define UVD_LMI_CRC11__CRC32_MASK 0xFFFFFFFFL 7072 //UVD_LMI_CRC12 7073 #define UVD_LMI_CRC12__CRC32__SHIFT 0x0 7074 #define UVD_LMI_CRC12__CRC32_MASK 0xFFFFFFFFL 7075 //UVD_LMI_CRC13 7076 #define UVD_LMI_CRC13__CRC32__SHIFT 0x0 7077 #define UVD_LMI_CRC13__CRC32_MASK 0xFFFFFFFFL 7078 //UVD_LMI_CRC14 7079 #define UVD_LMI_CRC14__CRC32__SHIFT 0x0 7080 #define UVD_LMI_CRC14__CRC32_MASK 0xFFFFFFFFL 7081 //UVD_LMI_CRC15 7082 #define UVD_LMI_CRC15__CRC32__SHIFT 0x0 7083 #define UVD_LMI_CRC15__CRC32_MASK 0xFFFFFFFFL 7084 //UVD_LMI_SWAP_CNTL2 7085 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 7086 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 7087 #define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x4 7088 #define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP__SHIFT 0xc 7089 #define UVD_LMI_SWAP_CNTL2__FBC_KEY_MC_SWAP__SHIFT 0xe 7090 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L 7091 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000CL 7092 #define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP_MASK 0x00000FF0L 7093 #define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP_MASK 0x00003000L 7094 #define UVD_LMI_SWAP_CNTL2__FBC_KEY_MC_SWAP_MASK 0x0000C000L 7095 //UVD_MEMCHECK_SYS_INT_EN 7096 #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN__SHIFT 0x0 7097 #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN__SHIFT 0x1 7098 #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN__SHIFT 0x2 7099 #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN__SHIFT 0x3 7100 #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN__SHIFT 0x4 7101 #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN__SHIFT 0x5 7102 #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 7103 #define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN__SHIFT 0x7 7104 #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 7105 #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 7106 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa 7107 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb 7108 #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN__SHIFT 0xc 7109 #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN__SHIFT 0xf 7110 #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 7111 #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 7112 #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 7113 #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 7114 #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 7115 #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 7116 #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 7117 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x1b 7118 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1c 7119 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1d 7120 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1e 7121 #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN__SHIFT 0x1f 7122 #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN_MASK 0x00000001L 7123 #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN_MASK 0x00000002L 7124 #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN_MASK 0x00000004L 7125 #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN_MASK 0x00000008L 7126 #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN_MASK 0x00000010L 7127 #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN_MASK 0x00000020L 7128 #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L 7129 #define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN_MASK 0x00000080L 7130 #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L 7131 #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L 7132 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L 7133 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L 7134 #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN_MASK 0x00001000L 7135 #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L 7136 #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L 7137 #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L 7138 #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L 7139 #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L 7140 #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L 7141 #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L 7142 #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L 7143 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN_MASK 0x08000000L 7144 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN_MASK 0x10000000L 7145 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN_MASK 0x20000000L 7146 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x40000000L 7147 #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN_MASK 0x80000000L 7148 //UVD_MEMCHECK_SYS_INT_STAT 7149 #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR__SHIFT 0x0 7150 #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR__SHIFT 0x1 7151 #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR__SHIFT 0x2 7152 #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR__SHIFT 0x3 7153 #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR__SHIFT 0x4 7154 #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR__SHIFT 0x5 7155 #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR__SHIFT 0x6 7156 #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR__SHIFT 0x7 7157 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR__SHIFT 0x8 7158 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR__SHIFT 0x9 7159 #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR__SHIFT 0xa 7160 #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR__SHIFT 0xb 7161 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc 7162 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd 7163 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR__SHIFT 0xe 7164 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR__SHIFT 0xf 7165 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 7166 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 7167 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 7168 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 7169 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 7170 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 7171 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 7172 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 7173 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR__SHIFT 0x18 7174 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR__SHIFT 0x19 7175 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e 7176 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f 7177 #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR_MASK 0x00000001L 7178 #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR_MASK 0x00000002L 7179 #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR_MASK 0x00000004L 7180 #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR_MASK 0x00000008L 7181 #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR_MASK 0x00000010L 7182 #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR_MASK 0x00000020L 7183 #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR_MASK 0x00000040L 7184 #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR_MASK 0x00000080L 7185 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR_MASK 0x00000100L 7186 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR_MASK 0x00000200L 7187 #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR_MASK 0x00000400L 7188 #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR_MASK 0x00000800L 7189 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L 7190 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L 7191 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L 7192 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L 7193 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L 7194 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L 7195 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L 7196 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L 7197 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L 7198 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L 7199 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L 7200 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L 7201 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR_MASK 0x01000000L 7202 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR_MASK 0x02000000L 7203 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L 7204 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L 7205 //UVD_MEMCHECK_SYS_INT_ACK 7206 #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK__SHIFT 0x0 7207 #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK__SHIFT 0x1 7208 #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK__SHIFT 0x2 7209 #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK__SHIFT 0x3 7210 #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK__SHIFT 0x4 7211 #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK__SHIFT 0x5 7212 #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK__SHIFT 0x6 7213 #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK__SHIFT 0x7 7214 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK__SHIFT 0x8 7215 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK__SHIFT 0x9 7216 #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK__SHIFT 0xa 7217 #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK__SHIFT 0xb 7218 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc 7219 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd 7220 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK__SHIFT 0xe 7221 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK__SHIFT 0xf 7222 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 7223 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 7224 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 7225 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 7226 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 7227 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 7228 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 7229 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 7230 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK__SHIFT 0x18 7231 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK__SHIFT 0x19 7232 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e 7233 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f 7234 #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK_MASK 0x00000001L 7235 #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK_MASK 0x00000002L 7236 #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK_MASK 0x00000004L 7237 #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK_MASK 0x00000008L 7238 #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK_MASK 0x00000010L 7239 #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK_MASK 0x00000020L 7240 #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK_MASK 0x00000040L 7241 #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK_MASK 0x00000080L 7242 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK_MASK 0x00000100L 7243 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK_MASK 0x00000200L 7244 #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK_MASK 0x00000400L 7245 #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK_MASK 0x00000800L 7246 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L 7247 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L 7248 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L 7249 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L 7250 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L 7251 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L 7252 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L 7253 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L 7254 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L 7255 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L 7256 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L 7257 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L 7258 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK_MASK 0x01000000L 7259 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK_MASK 0x02000000L 7260 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L 7261 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L 7262 //UVD_MEMCHECK_VCPU_INT_EN 7263 #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN__SHIFT 0x0 7264 #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN__SHIFT 0x1 7265 #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN__SHIFT 0x2 7266 #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN__SHIFT 0x3 7267 #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN__SHIFT 0x4 7268 #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN__SHIFT 0x5 7269 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 7270 #define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN__SHIFT 0x7 7271 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 7272 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 7273 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa 7274 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb 7275 #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN__SHIFT 0xc 7276 #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN__SHIFT 0xf 7277 #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 7278 #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 7279 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 7280 #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 7281 #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 7282 #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 7283 #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 7284 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x19 7285 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1a 7286 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1b 7287 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1c 7288 #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN__SHIFT 0x1d 7289 #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN_MASK 0x00000001L 7290 #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN_MASK 0x00000002L 7291 #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN_MASK 0x00000004L 7292 #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN_MASK 0x00000008L 7293 #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN_MASK 0x00000010L 7294 #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN_MASK 0x00000020L 7295 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L 7296 #define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN_MASK 0x00000080L 7297 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L 7298 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L 7299 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L 7300 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L 7301 #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN_MASK 0x00001000L 7302 #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L 7303 #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L 7304 #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L 7305 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L 7306 #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L 7307 #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L 7308 #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L 7309 #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L 7310 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN_MASK 0x02000000L 7311 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN_MASK 0x04000000L 7312 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN_MASK 0x08000000L 7313 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x10000000L 7314 #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN_MASK 0x20000000L 7315 //UVD_MEMCHECK_VCPU_INT_STAT 7316 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR__SHIFT 0x0 7317 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR__SHIFT 0x1 7318 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR__SHIFT 0x2 7319 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR__SHIFT 0x3 7320 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR__SHIFT 0x4 7321 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR__SHIFT 0x5 7322 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR__SHIFT 0x6 7323 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR__SHIFT 0x7 7324 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR__SHIFT 0x8 7325 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR__SHIFT 0x9 7326 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR__SHIFT 0xa 7327 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR__SHIFT 0xb 7328 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc 7329 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd 7330 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR__SHIFT 0xe 7331 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR__SHIFT 0xf 7332 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 7333 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 7334 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 7335 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 7336 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 7337 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 7338 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 7339 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 7340 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR__SHIFT 0x18 7341 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR__SHIFT 0x19 7342 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e 7343 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f 7344 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR_MASK 0x00000001L 7345 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR_MASK 0x00000002L 7346 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR_MASK 0x00000004L 7347 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR_MASK 0x00000008L 7348 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR_MASK 0x00000010L 7349 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR_MASK 0x00000020L 7350 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR_MASK 0x00000040L 7351 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR_MASK 0x00000080L 7352 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR_MASK 0x00000100L 7353 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR_MASK 0x00000200L 7354 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR_MASK 0x00000400L 7355 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR_MASK 0x00000800L 7356 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L 7357 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L 7358 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L 7359 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L 7360 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L 7361 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L 7362 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L 7363 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L 7364 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L 7365 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L 7366 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L 7367 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L 7368 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR_MASK 0x01000000L 7369 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR_MASK 0x02000000L 7370 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L 7371 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L 7372 //UVD_MEMCHECK_VCPU_INT_ACK 7373 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK__SHIFT 0x0 7374 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK__SHIFT 0x1 7375 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK__SHIFT 0x2 7376 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK__SHIFT 0x3 7377 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK__SHIFT 0x4 7378 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK__SHIFT 0x5 7379 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK__SHIFT 0x6 7380 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK__SHIFT 0x7 7381 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK__SHIFT 0x8 7382 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK__SHIFT 0x9 7383 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK__SHIFT 0xa 7384 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK__SHIFT 0xb 7385 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc 7386 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd 7387 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK__SHIFT 0xe 7388 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK__SHIFT 0xf 7389 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 7390 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 7391 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 7392 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 7393 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 7394 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 7395 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 7396 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 7397 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK__SHIFT 0x18 7398 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK__SHIFT 0x19 7399 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e 7400 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f 7401 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK_MASK 0x00000001L 7402 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK_MASK 0x00000002L 7403 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK_MASK 0x00000004L 7404 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK_MASK 0x00000008L 7405 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK_MASK 0x00000010L 7406 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK_MASK 0x00000020L 7407 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK_MASK 0x00000040L 7408 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK_MASK 0x00000080L 7409 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK_MASK 0x00000100L 7410 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK_MASK 0x00000200L 7411 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK_MASK 0x00000400L 7412 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK_MASK 0x00000800L 7413 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L 7414 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L 7415 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L 7416 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L 7417 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L 7418 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L 7419 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L 7420 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L 7421 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L 7422 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L 7423 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L 7424 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L 7425 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK_MASK 0x01000000L 7426 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK_MASK 0x02000000L 7427 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L 7428 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L 7429 //UVD_MEMCHECK2_SYS_INT_STAT 7430 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 7431 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 7432 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 7433 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 7434 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 7435 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 7436 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 7437 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 7438 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 7439 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 7440 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 7441 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 7442 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 7443 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 7444 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x16 7445 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x17 7446 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x18 7447 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x19 7448 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x1a 7449 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x1b 7450 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x1c 7451 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x1d 7452 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR__SHIFT 0x1e 7453 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR__SHIFT 0x1f 7454 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 7455 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 7456 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 7457 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 7458 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 7459 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 7460 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 7461 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 7462 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 7463 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 7464 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 7465 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 7466 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 7467 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 7468 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00400000L 7469 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00800000L 7470 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x01000000L 7471 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x02000000L 7472 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x04000000L 7473 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x08000000L 7474 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x10000000L 7475 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x20000000L 7476 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR_MASK 0x40000000L 7477 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR_MASK 0x80000000L 7478 //UVD_MEMCHECK2_SYS_INT_ACK 7479 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 7480 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 7481 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 7482 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 7483 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 7484 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 7485 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 7486 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 7487 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 7488 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 7489 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 7490 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 7491 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 7492 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 7493 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x16 7494 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x17 7495 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x18 7496 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x19 7497 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x1a 7498 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x1b 7499 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x1c 7500 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x1d 7501 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK__SHIFT 0x1e 7502 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK__SHIFT 0x1f 7503 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 7504 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 7505 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 7506 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 7507 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 7508 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 7509 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 7510 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 7511 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 7512 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 7513 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 7514 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 7515 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 7516 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 7517 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00400000L 7518 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00800000L 7519 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x01000000L 7520 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x02000000L 7521 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x04000000L 7522 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x08000000L 7523 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x10000000L 7524 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x20000000L 7525 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK_MASK 0x40000000L 7526 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK_MASK 0x80000000L 7527 //UVD_MEMCHECK2_VCPU_INT_STAT 7528 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 7529 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 7530 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 7531 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 7532 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 7533 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 7534 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 7535 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 7536 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 7537 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 7538 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 7539 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 7540 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 7541 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 7542 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x12 7543 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x13 7544 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x14 7545 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x15 7546 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x16 7547 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x17 7548 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x18 7549 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x19 7550 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR__SHIFT 0x1a 7551 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR__SHIFT 0x1b 7552 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 7553 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 7554 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 7555 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 7556 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 7557 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 7558 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 7559 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 7560 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 7561 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 7562 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 7563 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 7564 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 7565 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 7566 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00040000L 7567 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00080000L 7568 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x00100000L 7569 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x00200000L 7570 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x00400000L 7571 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x00800000L 7572 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x01000000L 7573 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x02000000L 7574 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR_MASK 0x04000000L 7575 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR_MASK 0x08000000L 7576 //UVD_MEMCHECK2_VCPU_INT_ACK 7577 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 7578 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 7579 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 7580 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 7581 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 7582 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 7583 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 7584 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 7585 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 7586 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 7587 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 7588 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 7589 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 7590 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 7591 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x12 7592 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x13 7593 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x14 7594 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x15 7595 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x16 7596 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x17 7597 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x18 7598 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x19 7599 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK__SHIFT 0x1a 7600 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK__SHIFT 0x1b 7601 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 7602 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 7603 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 7604 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 7605 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 7606 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 7607 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 7608 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 7609 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 7610 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 7611 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 7612 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 7613 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 7614 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 7615 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00040000L 7616 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00080000L 7617 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x00100000L 7618 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x00200000L 7619 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x00400000L 7620 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x00800000L 7621 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x01000000L 7622 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x02000000L 7623 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK_MASK 0x04000000L 7624 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK_MASK 0x08000000L 7625 7626 7627 #endif 7628