1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _vcn_5_0_0_OFFSET_HEADER 24 #define _vcn_5_0_0_OFFSET_HEADER 25 26 27 28 // addressBlock: uvd_uvddec 29 // base address: 0x1fc00 30 #define regUVD_TOP_CTRL 0x0100 31 #define regUVD_TOP_CTRL_BASE_IDX 1 32 #define regUVD_CGC_GATE 0x0101 33 #define regUVD_CGC_GATE_BASE_IDX 1 34 #define regUVD_CGC_CTRL 0x0102 35 #define regUVD_CGC_CTRL_BASE_IDX 1 36 #define regAVM_SUVD_CGC_GATE 0x0104 37 #define regAVM_SUVD_CGC_GATE_BASE_IDX 1 38 #define regEFC_SUVD_CGC_GATE 0x0104 39 #define regEFC_SUVD_CGC_GATE_BASE_IDX 1 40 #define regENT_SUVD_CGC_GATE 0x0104 41 #define regENT_SUVD_CGC_GATE_BASE_IDX 1 42 #define regIME_SUVD_CGC_GATE 0x0104 43 #define regIME_SUVD_CGC_GATE_BASE_IDX 1 44 #define regPPU_SUVD_CGC_GATE 0x0104 45 #define regPPU_SUVD_CGC_GATE_BASE_IDX 1 46 #define regSAOE_SUVD_CGC_GATE 0x0104 47 #define regSAOE_SUVD_CGC_GATE_BASE_IDX 1 48 #define regSCM_SUVD_CGC_GATE 0x0104 49 #define regSCM_SUVD_CGC_GATE_BASE_IDX 1 50 #define regSDB_SUVD_CGC_GATE 0x0104 51 #define regSDB_SUVD_CGC_GATE_BASE_IDX 1 52 #define regSIT0_NXT_SUVD_CGC_GATE 0x0104 53 #define regSIT0_NXT_SUVD_CGC_GATE_BASE_IDX 1 54 #define regSIT1_NXT_SUVD_CGC_GATE 0x0104 55 #define regSIT1_NXT_SUVD_CGC_GATE_BASE_IDX 1 56 #define regSIT2_NXT_SUVD_CGC_GATE 0x0104 57 #define regSIT2_NXT_SUVD_CGC_GATE_BASE_IDX 1 58 #define regSIT_SUVD_CGC_GATE 0x0104 59 #define regSIT_SUVD_CGC_GATE_BASE_IDX 1 60 #define regSMPA_SUVD_CGC_GATE 0x0104 61 #define regSMPA_SUVD_CGC_GATE_BASE_IDX 1 62 #define regSMP_SUVD_CGC_GATE 0x0104 63 #define regSMP_SUVD_CGC_GATE_BASE_IDX 1 64 #define regSRE_SUVD_CGC_GATE 0x0104 65 #define regSRE_SUVD_CGC_GATE_BASE_IDX 1 66 #define regUVD_SUVD_CGC_GATE 0x0104 67 #define regUVD_SUVD_CGC_GATE_BASE_IDX 1 68 #define regAVM_SUVD_CGC_GATE2 0x0105 69 #define regAVM_SUVD_CGC_GATE2_BASE_IDX 1 70 #define regDBR_SUVD_CGC_GATE2 0x0105 71 #define regDBR_SUVD_CGC_GATE2_BASE_IDX 1 72 #define regENT_SUVD_CGC_GATE2 0x0105 73 #define regENT_SUVD_CGC_GATE2_BASE_IDX 1 74 #define regIME_SUVD_CGC_GATE2 0x0105 75 #define regIME_SUVD_CGC_GATE2_BASE_IDX 1 76 #define regSAOE_SUVD_CGC_GATE2 0x0105 77 #define regSAOE_SUVD_CGC_GATE2_BASE_IDX 1 78 #define regSDB_SUVD_CGC_GATE2 0x0105 79 #define regSDB_SUVD_CGC_GATE2_BASE_IDX 1 80 #define regSIT0_NXT_SUVD_CGC_GATE2 0x0105 81 #define regSIT0_NXT_SUVD_CGC_GATE2_BASE_IDX 1 82 #define regSIT1_NXT_SUVD_CGC_GATE2 0x0105 83 #define regSIT1_NXT_SUVD_CGC_GATE2_BASE_IDX 1 84 #define regSIT2_NXT_SUVD_CGC_GATE2 0x0105 85 #define regSIT2_NXT_SUVD_CGC_GATE2_BASE_IDX 1 86 #define regSIT_SUVD_CGC_GATE2 0x0105 87 #define regSIT_SUVD_CGC_GATE2_BASE_IDX 1 88 #define regSMPA_SUVD_CGC_GATE2 0x0105 89 #define regSMPA_SUVD_CGC_GATE2_BASE_IDX 1 90 #define regSMP_SUVD_CGC_GATE2 0x0105 91 #define regSMP_SUVD_CGC_GATE2_BASE_IDX 1 92 #define regSRE_SUVD_CGC_GATE2 0x0105 93 #define regSRE_SUVD_CGC_GATE2_BASE_IDX 1 94 #define regUVD_SUVD_CGC_GATE2 0x0105 95 #define regUVD_SUVD_CGC_GATE2_BASE_IDX 1 96 #define regAVM_SUVD_CGC_CTRL 0x0106 97 #define regAVM_SUVD_CGC_CTRL_BASE_IDX 1 98 #define regDBR_SUVD_CGC_CTRL 0x0106 99 #define regDBR_SUVD_CGC_CTRL_BASE_IDX 1 100 #define regEFC_SUVD_CGC_CTRL 0x0106 101 #define regEFC_SUVD_CGC_CTRL_BASE_IDX 1 102 #define regENT_SUVD_CGC_CTRL 0x0106 103 #define regENT_SUVD_CGC_CTRL_BASE_IDX 1 104 #define regIME_SUVD_CGC_CTRL 0x0106 105 #define regIME_SUVD_CGC_CTRL_BASE_IDX 1 106 #define regPPU_SUVD_CGC_CTRL 0x0106 107 #define regPPU_SUVD_CGC_CTRL_BASE_IDX 1 108 #define regSAOE_SUVD_CGC_CTRL 0x0106 109 #define regSAOE_SUVD_CGC_CTRL_BASE_IDX 1 110 #define regSCM_SUVD_CGC_CTRL 0x0106 111 #define regSCM_SUVD_CGC_CTRL_BASE_IDX 1 112 #define regSDB_SUVD_CGC_CTRL 0x0106 113 #define regSDB_SUVD_CGC_CTRL_BASE_IDX 1 114 #define regSIT0_NXT_SUVD_CGC_CTRL 0x0106 115 #define regSIT0_NXT_SUVD_CGC_CTRL_BASE_IDX 1 116 #define regSIT1_NXT_SUVD_CGC_CTRL 0x0106 117 #define regSIT1_NXT_SUVD_CGC_CTRL_BASE_IDX 1 118 #define regSIT2_NXT_SUVD_CGC_CTRL 0x0106 119 #define regSIT2_NXT_SUVD_CGC_CTRL_BASE_IDX 1 120 #define regSIT_SUVD_CGC_CTRL 0x0106 121 #define regSIT_SUVD_CGC_CTRL_BASE_IDX 1 122 #define regSMPA_SUVD_CGC_CTRL 0x0106 123 #define regSMPA_SUVD_CGC_CTRL_BASE_IDX 1 124 #define regSMP_SUVD_CGC_CTRL 0x0106 125 #define regSMP_SUVD_CGC_CTRL_BASE_IDX 1 126 #define regSRE_SUVD_CGC_CTRL 0x0106 127 #define regSRE_SUVD_CGC_CTRL_BASE_IDX 1 128 #define regUVD_SUVD_CGC_CTRL 0x0106 129 #define regUVD_SUVD_CGC_CTRL_BASE_IDX 1 130 #define regUVD_CGC_CTRL3 0x010a 131 #define regUVD_CGC_CTRL3_BASE_IDX 1 132 #define regUVD_GPCOM_VCPU_DATA0 0x0110 133 #define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 134 #define regUVD_GPCOM_VCPU_DATA1 0x0111 135 #define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 136 #define regUVD_GPCOM_SYS_CMD 0x0112 137 #define regUVD_GPCOM_SYS_CMD_BASE_IDX 1 138 #define regUVD_GPCOM_SYS_DATA0 0x0113 139 #define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1 140 #define regUVD_GPCOM_SYS_DATA1 0x0114 141 #define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1 142 #define regUVD_VCPU_INT_EN 0x0115 143 #define regUVD_VCPU_INT_EN_BASE_IDX 1 144 #define regUVD_VCPU_INT_STATUS 0x0116 145 #define regUVD_VCPU_INT_STATUS_BASE_IDX 1 146 #define regUVD_VCPU_INT_ACK 0x0117 147 #define regUVD_VCPU_INT_ACK_BASE_IDX 1 148 #define regUVD_VCPU_INT_ROUTE 0x0118 149 #define regUVD_VCPU_INT_ROUTE_BASE_IDX 1 150 #define regUVD_DRV_FW_MSG 0x0119 151 #define regUVD_DRV_FW_MSG_BASE_IDX 1 152 #define regUVD_FW_DRV_MSG_ACK 0x011a 153 #define regUVD_FW_DRV_MSG_ACK_BASE_IDX 1 154 #define regUVD_SUVD_INT_EN 0x011b 155 #define regUVD_SUVD_INT_EN_BASE_IDX 1 156 #define regUVD_SUVD_INT_STATUS 0x011c 157 #define regUVD_SUVD_INT_STATUS_BASE_IDX 1 158 #define regUVD_SUVD_INT_ACK 0x011d 159 #define regUVD_SUVD_INT_ACK_BASE_IDX 1 160 #define regUVD_ENC_VCPU_INT_EN 0x011e 161 #define regUVD_ENC_VCPU_INT_EN_BASE_IDX 1 162 #define regUVD_ENC_VCPU_INT_STATUS 0x011f 163 #define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX 1 164 #define regUVD_ENC_VCPU_INT_ACK 0x0120 165 #define regUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 166 #define regUVD_MASTINT_EN 0x0121 167 #define regUVD_MASTINT_EN_BASE_IDX 1 168 #define regUVD_SYS_INT_EN 0x0122 169 #define regUVD_SYS_INT_EN_BASE_IDX 1 170 #define regUVD_SYS_INT_STATUS 0x0123 171 #define regUVD_SYS_INT_STATUS_BASE_IDX 1 172 #define regUVD_SYS_INT_ACK 0x0124 173 #define regUVD_SYS_INT_ACK_BASE_IDX 1 174 #define regUVD_JOB_DONE 0x0125 175 #define regUVD_JOB_DONE_BASE_IDX 1 176 #define regUVD_CBUF_ID 0x0126 177 #define regUVD_CBUF_ID_BASE_IDX 1 178 #define regUVD_CONTEXT_ID 0x0127 179 #define regUVD_CONTEXT_ID_BASE_IDX 1 180 #define regUVD_CONTEXT_ID2 0x0128 181 #define regUVD_CONTEXT_ID2_BASE_IDX 1 182 #define regUVD_NO_OP 0x0129 183 #define regUVD_NO_OP_BASE_IDX 1 184 #define regUVD_RB_BASE_LO 0x012a 185 #define regUVD_RB_BASE_LO_BASE_IDX 1 186 #define regUVD_RB_BASE_HI 0x012b 187 #define regUVD_RB_BASE_HI_BASE_IDX 1 188 #define regUVD_RB_SIZE 0x012c 189 #define regUVD_RB_SIZE_BASE_IDX 1 190 #define regUVD_RB_BASE_LO2 0x012f 191 #define regUVD_RB_BASE_LO2_BASE_IDX 1 192 #define regUVD_RB_BASE_HI2 0x0130 193 #define regUVD_RB_BASE_HI2_BASE_IDX 1 194 #define regUVD_RB_SIZE2 0x0131 195 #define regUVD_RB_SIZE2_BASE_IDX 1 196 #define regUVD_RB_BASE_LO3 0x0134 197 #define regUVD_RB_BASE_LO3_BASE_IDX 1 198 #define regUVD_RB_BASE_HI3 0x0135 199 #define regUVD_RB_BASE_HI3_BASE_IDX 1 200 #define regUVD_RB_SIZE3 0x0136 201 #define regUVD_RB_SIZE3_BASE_IDX 1 202 #define regUVD_RB_BASE_LO4 0x0139 203 #define regUVD_RB_BASE_LO4_BASE_IDX 1 204 #define regUVD_RB_BASE_HI4 0x013a 205 #define regUVD_RB_BASE_HI4_BASE_IDX 1 206 #define regUVD_RB_SIZE4 0x013b 207 #define regUVD_RB_SIZE4_BASE_IDX 1 208 #define regUVD_OUT_RB_BASE_LO 0x013e 209 #define regUVD_OUT_RB_BASE_LO_BASE_IDX 1 210 #define regUVD_OUT_RB_BASE_HI 0x013f 211 #define regUVD_OUT_RB_BASE_HI_BASE_IDX 1 212 #define regUVD_OUT_RB_SIZE 0x0140 213 #define regUVD_OUT_RB_SIZE_BASE_IDX 1 214 #define regUVD_IOV_ACTIVE_FCN_ID 0x0143 215 #define regUVD_IOV_ACTIVE_FCN_ID_BASE_IDX 1 216 #define regUVD_IOV_MAILBOX 0x0144 217 #define regUVD_IOV_MAILBOX_BASE_IDX 1 218 #define regUVD_IOV_MAILBOX_RESP 0x0145 219 #define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1 220 #define regUVD_RB_ARB_CTRL 0x0146 221 #define regUVD_RB_ARB_CTRL_BASE_IDX 1 222 #define regUVD_CTX_INDEX 0x0147 223 #define regUVD_CTX_INDEX_BASE_IDX 1 224 #define regUVD_CTX_DATA 0x0148 225 #define regUVD_CTX_DATA_BASE_IDX 1 226 #define regUVD_CXW_WR 0x0149 227 #define regUVD_CXW_WR_BASE_IDX 1 228 #define regUVD_CXW_WR_INT_ID 0x014a 229 #define regUVD_CXW_WR_INT_ID_BASE_IDX 1 230 #define regUVD_CXW_WR_INT_CTX_ID 0x014b 231 #define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 232 #define regUVD_CXW_INT_ID 0x014c 233 #define regUVD_CXW_INT_ID_BASE_IDX 1 234 #define regUVD_MPEG2_ERROR 0x014d 235 #define regUVD_MPEG2_ERROR_BASE_IDX 1 236 #define regUVD_YBASE 0x0150 237 #define regUVD_YBASE_BASE_IDX 1 238 #define regUVD_UVBASE 0x0151 239 #define regUVD_UVBASE_BASE_IDX 1 240 #define regUVD_PITCH 0x0152 241 #define regUVD_PITCH_BASE_IDX 1 242 #define regUVD_WIDTH 0x0153 243 #define regUVD_WIDTH_BASE_IDX 1 244 #define regUVD_HEIGHT 0x0154 245 #define regUVD_HEIGHT_BASE_IDX 1 246 #define regUVD_PICCOUNT 0x0155 247 #define regUVD_PICCOUNT_BASE_IDX 1 248 #define regUVD_MPRD_INITIAL_XY 0x0156 249 #define regUVD_MPRD_INITIAL_XY_BASE_IDX 1 250 #define regUVD_MPEG2_CTRL 0x0157 251 #define regUVD_MPEG2_CTRL_BASE_IDX 1 252 #define regUVD_MB_CTL_BUF_BASE 0x0158 253 #define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1 254 #define regUVD_PIC_CTL_BUF_BASE 0x0159 255 #define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1 256 #define regUVD_DXVA_BUF_SIZE 0x015a 257 #define regUVD_DXVA_BUF_SIZE_BASE_IDX 1 258 #define regUVD_SCRATCH_NP 0x015b 259 #define regUVD_SCRATCH_NP_BASE_IDX 1 260 #define regUVD_CLK_SWT_HANDSHAKE 0x015c 261 #define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1 262 #define regUVD_GP_SCRATCH0 0x015e 263 #define regUVD_GP_SCRATCH0_BASE_IDX 1 264 #define regUVD_GP_SCRATCH1 0x015f 265 #define regUVD_GP_SCRATCH1_BASE_IDX 1 266 #define regUVD_GP_SCRATCH2 0x0160 267 #define regUVD_GP_SCRATCH2_BASE_IDX 1 268 #define regUVD_GP_SCRATCH3 0x0161 269 #define regUVD_GP_SCRATCH3_BASE_IDX 1 270 #define regUVD_GP_SCRATCH4 0x0162 271 #define regUVD_GP_SCRATCH4_BASE_IDX 1 272 #define regUVD_GP_SCRATCH5 0x0163 273 #define regUVD_GP_SCRATCH5_BASE_IDX 1 274 #define regUVD_GP_SCRATCH6 0x0164 275 #define regUVD_GP_SCRATCH6_BASE_IDX 1 276 #define regUVD_GP_SCRATCH7 0x0165 277 #define regUVD_GP_SCRATCH7_BASE_IDX 1 278 #define regUVD_GP_SCRATCH8 0x0166 279 #define regUVD_GP_SCRATCH8_BASE_IDX 1 280 #define regUVD_GP_SCRATCH9 0x0167 281 #define regUVD_GP_SCRATCH9_BASE_IDX 1 282 #define regUVD_GP_SCRATCH10 0x0168 283 #define regUVD_GP_SCRATCH10_BASE_IDX 1 284 #define regUVD_GP_SCRATCH11 0x0169 285 #define regUVD_GP_SCRATCH11_BASE_IDX 1 286 #define regUVD_GP_SCRATCH12 0x016a 287 #define regUVD_GP_SCRATCH12_BASE_IDX 1 288 #define regUVD_GP_SCRATCH13 0x016b 289 #define regUVD_GP_SCRATCH13_BASE_IDX 1 290 #define regUVD_GP_SCRATCH14 0x016c 291 #define regUVD_GP_SCRATCH14_BASE_IDX 1 292 #define regUVD_GP_SCRATCH15 0x016d 293 #define regUVD_GP_SCRATCH15_BASE_IDX 1 294 #define regUVD_GP_SCRATCH16 0x016e 295 #define regUVD_GP_SCRATCH16_BASE_IDX 1 296 #define regUVD_GP_SCRATCH17 0x016f 297 #define regUVD_GP_SCRATCH17_BASE_IDX 1 298 #define regUVD_GP_SCRATCH18 0x0170 299 #define regUVD_GP_SCRATCH18_BASE_IDX 1 300 #define regUVD_GP_SCRATCH19 0x0171 301 #define regUVD_GP_SCRATCH19_BASE_IDX 1 302 #define regUVD_GP_SCRATCH20 0x0172 303 #define regUVD_GP_SCRATCH20_BASE_IDX 1 304 #define regUVD_GP_SCRATCH21 0x0173 305 #define regUVD_GP_SCRATCH21_BASE_IDX 1 306 #define regUVD_GP_SCRATCH22 0x0174 307 #define regUVD_GP_SCRATCH22_BASE_IDX 1 308 #define regUVD_GP_SCRATCH23 0x0175 309 #define regUVD_GP_SCRATCH23_BASE_IDX 1 310 #define regUVD_AUDIO_RB_BASE_LO 0x0176 311 #define regUVD_AUDIO_RB_BASE_LO_BASE_IDX 1 312 #define regUVD_AUDIO_RB_BASE_HI 0x0177 313 #define regUVD_AUDIO_RB_BASE_HI_BASE_IDX 1 314 #define regUVD_AUDIO_RB_SIZE 0x0178 315 #define regUVD_AUDIO_RB_SIZE_BASE_IDX 1 316 #define regUVD_VCPU_INT_STATUS2 0x017b 317 #define regUVD_VCPU_INT_STATUS2_BASE_IDX 1 318 #define regUVD_VCPU_INT_ACK2 0x017c 319 #define regUVD_VCPU_INT_ACK2_BASE_IDX 1 320 #define regUVD_VCPU_INT_EN2 0x017d 321 #define regUVD_VCPU_INT_EN2_BASE_IDX 1 322 #define regUVD_SUVD_CGC_STATUS2 0x017e 323 #define regUVD_SUVD_CGC_STATUS2_BASE_IDX 1 324 #define regUVD_SUVD_INT_STATUS2 0x0180 325 #define regUVD_SUVD_INT_STATUS2_BASE_IDX 1 326 #define regUVD_SUVD_INT_EN2 0x0181 327 #define regUVD_SUVD_INT_EN2_BASE_IDX 1 328 #define regUVD_SUVD_INT_ACK2 0x0182 329 #define regUVD_SUVD_INT_ACK2_BASE_IDX 1 330 #define regUVD_STATUS 0x0183 331 #define regUVD_STATUS_BASE_IDX 1 332 #define regUVD_ENC_PIPE_BUSY 0x0184 333 #define regUVD_ENC_PIPE_BUSY_BASE_IDX 1 334 #define regUVD_FW_POWER_STATUS 0x0185 335 #define regUVD_FW_POWER_STATUS_BASE_IDX 1 336 #define regUVD_CNTL 0x0186 337 #define regUVD_CNTL_BASE_IDX 1 338 #define regUVD_SOFT_RESET 0x0187 339 #define regUVD_SOFT_RESET_BASE_IDX 1 340 #define regUVD_SOFT_RESET2 0x0188 341 #define regUVD_SOFT_RESET2_BASE_IDX 1 342 #define regUVD_MMSCH_SOFT_RESET 0x0189 343 #define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1 344 #define regUVD_WIG_CTRL 0x018a 345 #define regUVD_WIG_CTRL_BASE_IDX 1 346 #define regUVD_CGC_STATUS 0x018c 347 #define regUVD_CGC_STATUS_BASE_IDX 1 348 #define regUVD_CGC_UDEC_STATUS 0x018e 349 #define regUVD_CGC_UDEC_STATUS_BASE_IDX 1 350 #define regUVD_SUVD_CGC_STATUS 0x0190 351 #define regUVD_SUVD_CGC_STATUS_BASE_IDX 1 352 #define regUVD_GPCOM_VCPU_CMD 0x0192 353 #define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1 354 355 356 // addressBlock: uvd_vcn_cdefe_cdefe_broadcast_dec0 357 // base address: 0x1fc00 358 #define regCDEFE_SUVD_CGC_GATE 0x0104 359 #define regCDEFE_SUVD_CGC_GATE_BASE_IDX 1 360 #define regCDEFE_SUVD_CGC_GATE2 0x0105 361 #define regCDEFE_SUVD_CGC_GATE2_BASE_IDX 1 362 #define regCDEFE_SUVD_CGC_CTRL 0x0106 363 #define regCDEFE_SUVD_CGC_CTRL_BASE_IDX 1 364 365 366 // addressBlock: uvd_ecpudec 367 // base address: 0x1ff00 368 #define regUVD_VCPU_CACHE_OFFSET0 0x01c0 369 #define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 370 #define regUVD_VCPU_CACHE_SIZE0 0x01c1 371 #define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 372 #define regUVD_VCPU_CACHE_OFFSET1 0x01c2 373 #define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 374 #define regUVD_VCPU_CACHE_SIZE1 0x01c3 375 #define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 376 #define regUVD_VCPU_CACHE_OFFSET2 0x01c4 377 #define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 378 #define regUVD_VCPU_CACHE_SIZE2 0x01c5 379 #define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 380 #define regUVD_VCPU_CACHE_OFFSET3 0x01c6 381 #define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 382 #define regUVD_VCPU_CACHE_SIZE3 0x01c7 383 #define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 384 #define regUVD_VCPU_CACHE_OFFSET4 0x01c8 385 #define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 386 #define regUVD_VCPU_CACHE_SIZE4 0x01c9 387 #define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 388 #define regUVD_VCPU_CACHE_OFFSET5 0x01ca 389 #define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 390 #define regUVD_VCPU_CACHE_SIZE5 0x01cb 391 #define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 392 #define regUVD_VCPU_CACHE_OFFSET6 0x01cc 393 #define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 394 #define regUVD_VCPU_CACHE_SIZE6 0x01cd 395 #define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 396 #define regUVD_VCPU_CACHE_OFFSET7 0x01ce 397 #define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 398 #define regUVD_VCPU_CACHE_SIZE7 0x01cf 399 #define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 400 #define regUVD_VCPU_CACHE_OFFSET8 0x01d0 401 #define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 402 #define regUVD_VCPU_CACHE_SIZE8 0x01d1 403 #define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 404 #define regUVD_VCPU_NONCACHE_OFFSET0 0x01d2 405 #define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 406 #define regUVD_VCPU_NONCACHE_SIZE0 0x01d3 407 #define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 408 #define regUVD_VCPU_NONCACHE_OFFSET1 0x01d4 409 #define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 410 #define regUVD_VCPU_NONCACHE_SIZE1 0x01d5 411 #define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 412 #define regUVD_VCPU_CNTL 0x01d6 413 #define regUVD_VCPU_CNTL_BASE_IDX 1 414 #define regUVD_VCPU_PRID 0x01d7 415 #define regUVD_VCPU_PRID_BASE_IDX 1 416 #define regUVD_VCPU_TRCE 0x01d8 417 #define regUVD_VCPU_TRCE_BASE_IDX 1 418 #define regUVD_VCPU_TRCE_RD 0x01d9 419 #define regUVD_VCPU_TRCE_RD_BASE_IDX 1 420 #define regUVD_VCPU_IND_INDEX 0x01db 421 #define regUVD_VCPU_IND_INDEX_BASE_IDX 1 422 #define regUVD_VCPU_IND_DATA 0x01dc 423 #define regUVD_VCPU_IND_DATA_BASE_IDX 1 424 425 426 // addressBlock: uvd_lmi_adpdec 427 // base address: 0x20290 428 #define regUVD_LMI_RE_64BIT_BAR_LOW 0x02af 429 #define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1 430 #define regUVD_LMI_RE_64BIT_BAR_HIGH 0x02b0 431 #define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1 432 #define regUVD_LMI_IT_64BIT_BAR_LOW 0x02b1 433 #define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1 434 #define regUVD_LMI_IT_64BIT_BAR_HIGH 0x02b2 435 #define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1 436 #define regUVD_LMI_MP_64BIT_BAR_LOW 0x02b3 437 #define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1 438 #define regUVD_LMI_MP_64BIT_BAR_HIGH 0x02b4 439 #define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1 440 #define regUVD_LMI_CM_64BIT_BAR_LOW 0x02b5 441 #define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1 442 #define regUVD_LMI_CM_64BIT_BAR_HIGH 0x02b6 443 #define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1 444 #define regUVD_LMI_DB_64BIT_BAR_LOW 0x02b7 445 #define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1 446 #define regUVD_LMI_DB_64BIT_BAR_HIGH 0x02b8 447 #define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1 448 #define regUVD_LMI_DBW_64BIT_BAR_LOW 0x02b9 449 #define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1 450 #define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x02ba 451 #define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1 452 #define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x02bb 453 #define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1 454 #define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x02bc 455 #define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1 456 #define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x02bd 457 #define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1 458 #define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x02be 459 #define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1 460 #define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x02bf 461 #define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1 462 #define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x02c0 463 #define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1 464 #define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0x02c1 465 #define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX 1 466 #define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0x02c2 467 #define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX 1 468 #define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x02c5 469 #define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 470 #define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x02c6 471 #define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 472 #define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x02c7 473 #define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 474 #define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x02c8 475 #define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 476 #define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x02c9 477 #define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1 478 #define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x02ca 479 #define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1 480 #define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x02cb 481 #define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 482 #define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x02cc 483 #define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 484 #define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x02cd 485 #define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 486 #define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x02ce 487 #define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 488 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x02cf 489 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 490 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x02d0 491 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 492 #define regUVD_LMI_CENC_64BIT_BAR_LOW 0x02d1 493 #define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1 494 #define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x02d2 495 #define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1 496 #define regUVD_LMI_SRE_64BIT_BAR_LOW 0x02d3 497 #define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1 498 #define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x02d4 499 #define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1 500 #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x02d5 501 #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1 502 #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x02d6 503 #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1 504 #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x02d7 505 #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1 506 #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x02d8 507 #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 508 #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x02d9 509 #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 510 #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x02da 511 #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 512 #define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x02dd 513 #define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1 514 #define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x02de 515 #define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1 516 #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x02df 517 #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1 518 #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x02e0 519 #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1 520 #define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x02e1 521 #define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1 522 #define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x02e2 523 #define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1 524 #define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x02e3 525 #define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1 526 #define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x02e4 527 #define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1 528 #define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x02e5 529 #define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1 530 #define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x02e6 531 #define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1 532 #define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x02e7 533 #define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1 534 #define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x02e8 535 #define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1 536 #define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x02e9 537 #define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1 538 #define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x02ea 539 #define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1 540 #define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x02eb 541 #define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1 542 #define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x02ec 543 #define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1 544 #define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x02ed 545 #define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1 546 #define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x02ee 547 #define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1 548 #define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x02ef 549 #define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1 550 #define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x02f0 551 #define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1 552 #define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x02f1 553 #define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1 554 #define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x02f2 555 #define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1 556 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x02fb 557 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 558 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x02fc 559 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 560 #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x02fd 561 #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 562 #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x02fe 563 #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 564 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x02ff 565 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 566 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x0300 567 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 568 #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x0301 569 #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 570 #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x0302 571 #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 572 #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0303 573 #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 574 #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0304 575 #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 576 #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0305 577 #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 578 #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0306 579 #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 580 #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0307 581 #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 582 #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0308 583 #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 584 #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0309 585 #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 586 #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x030a 587 #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 588 #define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x030b 589 #define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1 590 #define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x030c 591 #define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1 592 #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x030d 593 #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1 594 #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x030e 595 #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1 596 #define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x030f 597 #define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 598 #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0318 599 #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1 600 #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0319 601 #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 602 #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x031a 603 #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 604 #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x031b 605 #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 606 #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x031c 607 #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1 608 #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x031d 609 #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 610 #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x031e 611 #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 612 #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x031f 613 #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 614 #define regUVD_ADP_ATOMIC_CONFIG 0x0321 615 #define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX 1 616 #define regUVD_LMI_ARB_CTRL2 0x0322 617 #define regUVD_LMI_ARB_CTRL2_BASE_IDX 1 618 #define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x0327 619 #define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 620 #define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x0328 621 #define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 622 #define regUVD_LMI_LAT_CTRL 0x0329 623 #define regUVD_LMI_LAT_CTRL_BASE_IDX 1 624 #define regUVD_LMI_LAT_CNTR 0x032a 625 #define regUVD_LMI_LAT_CNTR_BASE_IDX 1 626 #define regUVD_LMI_AVG_LAT_CNTR 0x032b 627 #define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 628 #define regUVD_LMI_SPH 0x032c 629 #define regUVD_LMI_SPH_BASE_IDX 1 630 #define regUVD_LMI_VCPU_CACHE_VMID 0x032d 631 #define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 632 #define regUVD_LMI_CTRL2 0x032e 633 #define regUVD_LMI_CTRL2_BASE_IDX 1 634 #define regUVD_LMI_URGENT_CTRL 0x032f 635 #define regUVD_LMI_URGENT_CTRL_BASE_IDX 1 636 #define regUVD_LMI_CTRL 0x0330 637 #define regUVD_LMI_CTRL_BASE_IDX 1 638 #define regUVD_LMI_STATUS 0x0331 639 #define regUVD_LMI_STATUS_BASE_IDX 1 640 #define regUVD_LMI_PERFMON_CTRL 0x0334 641 #define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1 642 #define regUVD_LMI_PERFMON_COUNT_LO 0x0335 643 #define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 644 #define regUVD_LMI_PERFMON_COUNT_HI 0x0336 645 #define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 646 #define regUVD_LMI_ADP_SWAP_CNTL 0x0337 647 #define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1 648 #define regUVD_LMI_RBC_RB_VMID 0x0338 649 #define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1 650 #define regUVD_LMI_RBC_IB_VMID 0x0339 651 #define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1 652 #define regUVD_LMI_MC_CREDITS 0x033a 653 #define regUVD_LMI_MC_CREDITS_BASE_IDX 1 654 #define regUVD_LMI_ADP_IND_INDEX 0x033e 655 #define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1 656 #define regUVD_LMI_ADP_IND_DATA 0x033f 657 #define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1 658 #define regUVD_LMI_ADP_PF_EN 0x0340 659 #define regUVD_LMI_ADP_PF_EN_BASE_IDX 1 660 #define regUVD_LMI_PREF_CTRL 0x0342 661 #define regUVD_LMI_PREF_CTRL_BASE_IDX 1 662 663 664 // addressBlock: uvd_uvd_jpeg0_jpegnpdec 665 // base address: 0x20f00 666 #define regUVD_JPEG_CNTL 0x05c0 667 #define regUVD_JPEG_CNTL_BASE_IDX 1 668 #define regUVD_JPEG_RB_BASE 0x05c1 669 #define regUVD_JPEG_RB_BASE_BASE_IDX 1 670 #define regUVD_JPEG_RB_WPTR 0x05c2 671 #define regUVD_JPEG_RB_WPTR_BASE_IDX 1 672 #define regUVD_JPEG_RB_RPTR 0x05c3 673 #define regUVD_JPEG_RB_RPTR_BASE_IDX 1 674 #define regUVD_JPEG_RB_SIZE 0x05c4 675 #define regUVD_JPEG_RB_SIZE_BASE_IDX 1 676 #define regUVD_JPEG_DEC_CNT 0x05c5 677 #define regUVD_JPEG_DEC_CNT_BASE_IDX 1 678 #define regUVD_JPEG_SPS_INFO 0x05c6 679 #define regUVD_JPEG_SPS_INFO_BASE_IDX 1 680 #define regUVD_JPEG_SPS1_INFO 0x05c7 681 #define regUVD_JPEG_SPS1_INFO_BASE_IDX 1 682 #define regUVD_JPEG_RE_TIMER 0x05c8 683 #define regUVD_JPEG_RE_TIMER_BASE_IDX 1 684 #define regUVD_JPEG_DEC_SCRATCH0 0x05c9 685 #define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 1 686 #define regUVD_JPEG_INT_EN 0x05ca 687 #define regUVD_JPEG_INT_EN_BASE_IDX 1 688 #define regUVD_JPEG_INT_STAT 0x05cb 689 #define regUVD_JPEG_INT_STAT_BASE_IDX 1 690 #define regUVD_JPEG_TIER_CNTL0 0x05cc 691 #define regUVD_JPEG_TIER_CNTL0_BASE_IDX 1 692 #define regUVD_JPEG_TIER_CNTL1 0x05cd 693 #define regUVD_JPEG_TIER_CNTL1_BASE_IDX 1 694 #define regUVD_JPEG_TIER_CNTL2 0x05ce 695 #define regUVD_JPEG_TIER_CNTL2_BASE_IDX 1 696 #define regUVD_JPEG_TIER_STATUS 0x05cf 697 #define regUVD_JPEG_TIER_STATUS_BASE_IDX 1 698 699 700 // addressBlock: uvd_uvd_jpeg_sclk0_jpegnpsclkdec 701 // base address: 0x21000 702 #define regUVD_JPEG_OUTBUF_CNTL 0x0600 703 #define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 1 704 #define regUVD_JPEG_OUTBUF_WPTR 0x0601 705 #define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 1 706 #define regUVD_JPEG_OUTBUF_RPTR 0x0602 707 #define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 1 708 #define regUVD_JPEG_PITCH 0x0603 709 #define regUVD_JPEG_PITCH_BASE_IDX 1 710 #define regUVD_JPEG_UV_PITCH 0x0604 711 #define regUVD_JPEG_UV_PITCH_BASE_IDX 1 712 #define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x0605 713 #define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 1 714 #define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x0606 715 #define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 1 716 #define regJPEG_DEC_GFX8_ADDR_CONFIG 0x0607 717 #define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 1 718 #define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x0608 719 #define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 1 720 #define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x0609 721 #define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 1 722 #define regJPEG_DEC_GFX10_ADDR_CONFIG 0x060a 723 #define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 1 724 #define regJPEG_DEC_ADDR_MODE 0x060b 725 #define regJPEG_DEC_ADDR_MODE_BASE_IDX 1 726 #define regUVD_JPEG_OUTPUT_XY 0x060c 727 #define regUVD_JPEG_OUTPUT_XY_BASE_IDX 1 728 #define regUVD_JPEG_GPCOM_CMD 0x060d 729 #define regUVD_JPEG_GPCOM_CMD_BASE_IDX 1 730 #define regUVD_JPEG_GPCOM_DATA0 0x060e 731 #define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 1 732 #define regUVD_JPEG_GPCOM_DATA1 0x060f 733 #define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 1 734 #define regUVD_JPEG_SCRATCH1 0x0610 735 #define regUVD_JPEG_SCRATCH1_BASE_IDX 1 736 #define regUVD_JPEG_DEC_SOFT_RST 0x0611 737 #define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX 1 738 739 740 // addressBlock: uvd_uvd_jrbc0_uvd_jrbc_dec 741 // base address: 0x21100 742 #define regUVD_JRBC_RB_WPTR 0x0640 743 #define regUVD_JRBC_RB_WPTR_BASE_IDX 1 744 #define regUVD_JRBC_RB_CNTL 0x0641 745 #define regUVD_JRBC_RB_CNTL_BASE_IDX 1 746 #define regUVD_JRBC_IB_SIZE 0x0642 747 #define regUVD_JRBC_IB_SIZE_BASE_IDX 1 748 #define regUVD_JRBC_URGENT_CNTL 0x0643 749 #define regUVD_JRBC_URGENT_CNTL_BASE_IDX 1 750 #define regUVD_JRBC_RB_REF_DATA 0x0644 751 #define regUVD_JRBC_RB_REF_DATA_BASE_IDX 1 752 #define regUVD_JRBC_RB_COND_RD_TIMER 0x0645 753 #define regUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 754 #define regUVD_JRBC_SOFT_RESET 0x0648 755 #define regUVD_JRBC_SOFT_RESET_BASE_IDX 1 756 #define regUVD_JRBC_STATUS 0x0649 757 #define regUVD_JRBC_STATUS_BASE_IDX 1 758 #define regUVD_JRBC_RB_RPTR 0x064a 759 #define regUVD_JRBC_RB_RPTR_BASE_IDX 1 760 #define regUVD_JRBC_RB_BUF_STATUS 0x064b 761 #define regUVD_JRBC_RB_BUF_STATUS_BASE_IDX 1 762 #define regUVD_JRBC_IB_BUF_STATUS 0x064c 763 #define regUVD_JRBC_IB_BUF_STATUS_BASE_IDX 1 764 #define regUVD_JRBC_IB_SIZE_UPDATE 0x064d 765 #define regUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 1 766 #define regUVD_JRBC_IB_COND_RD_TIMER 0x064e 767 #define regUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 1 768 #define regUVD_JRBC_IB_REF_DATA 0x064f 769 #define regUVD_JRBC_IB_REF_DATA_BASE_IDX 1 770 #define regUVD_JPEG_PREEMPT_CMD 0x0650 771 #define regUVD_JPEG_PREEMPT_CMD_BASE_IDX 1 772 #define regUVD_JPEG_PREEMPT_FENCE_DATA0 0x0651 773 #define regUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 1 774 #define regUVD_JPEG_PREEMPT_FENCE_DATA1 0x0652 775 #define regUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 1 776 #define regUVD_JRBC_RB_SIZE 0x0653 777 #define regUVD_JRBC_RB_SIZE_BASE_IDX 1 778 #define regUVD_JRBC_SCRATCH0 0x0654 779 #define regUVD_JRBC_SCRATCH0_BASE_IDX 1 780 781 782 // addressBlock: uvd_uvd_jmi0_uvd_jmi_dec 783 // base address: 0x21180 784 #define regUVD_JPEG_DEC_PF_CTRL 0x0660 785 #define regUVD_JPEG_DEC_PF_CTRL_BASE_IDX 1 786 #define regUVD_LMI_JRBC_CTRL 0x0661 787 #define regUVD_LMI_JRBC_CTRL_BASE_IDX 1 788 #define regUVD_LMI_JPEG_CTRL 0x0662 789 #define regUVD_LMI_JPEG_CTRL_BASE_IDX 1 790 #define regJPEG_LMI_DROP 0x0663 791 #define regJPEG_LMI_DROP_BASE_IDX 1 792 #define regUVD_LMI_JRBC_IB_VMID 0x0664 793 #define regUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 794 #define regUVD_LMI_JRBC_RB_VMID 0x0665 795 #define regUVD_LMI_JRBC_RB_VMID_BASE_IDX 1 796 #define regUVD_LMI_JPEG_VMID 0x0666 797 #define regUVD_LMI_JPEG_VMID_BASE_IDX 1 798 #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0667 799 #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 1 800 #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0668 801 #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 802 #define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0669 803 #define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 804 #define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x066a 805 #define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 806 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x066b 807 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 808 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x066c 809 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 810 #define regUVD_LMI_JPEG_PREEMPT_VMID 0x066d 811 #define regUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 1 812 #define regUVD_JMI_DEC_SWAP_CNTL 0x066e 813 #define regUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 1 814 #define regUVD_JMI_ATOMIC_CNTL 0x066f 815 #define regUVD_JMI_ATOMIC_CNTL_BASE_IDX 1 816 #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0670 817 #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 1 818 #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0671 819 #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 820 #define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0672 821 #define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1 822 #define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0673 823 #define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 1 824 #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0674 825 #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 1 826 #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0675 827 #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 828 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0676 829 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 830 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0677 831 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 832 #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0678 833 #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 834 #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0679 835 #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 836 #define regUVD_JMI_ATOMIC_CNTL2 0x067d 837 #define regUVD_JMI_ATOMIC_CNTL2_BASE_IDX 1 838 839 840 // addressBlock: uvd_uvd_jmi_common_dec 841 // base address: 0x21300 842 #define regUVD_JADP_MCIF_URGENT_CTRL 0x06c1 843 #define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 1 844 #define regUVD_JMI_URGENT_CTRL 0x06c2 845 #define regUVD_JMI_URGENT_CTRL_BASE_IDX 1 846 #define regUVD_JMI_CTRL 0x06c3 847 #define regUVD_JMI_CTRL_BASE_IDX 1 848 #define regJPEG_MEMCHECK_CLAMPING_CNTL 0x06c4 849 #define regJPEG_MEMCHECK_CLAMPING_CNTL_BASE_IDX 1 850 #define regJPEG_MEMCHECK_SAFE_ADDR 0x06c5 851 #define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 1 852 #define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x06c6 853 #define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 1 854 #define regUVD_JMI_LAT_CTRL 0x06c7 855 #define regUVD_JMI_LAT_CTRL_BASE_IDX 1 856 #define regUVD_JMI_LAT_CNTR 0x06c8 857 #define regUVD_JMI_LAT_CNTR_BASE_IDX 1 858 #define regUVD_JMI_AVG_LAT_CNTR 0x06c9 859 #define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 1 860 #define regUVD_JMI_PERFMON_CTRL 0x06ca 861 #define regUVD_JMI_PERFMON_CTRL_BASE_IDX 1 862 #define regUVD_JMI_PERFMON_COUNT_LO 0x06cb 863 #define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 1 864 #define regUVD_JMI_PERFMON_COUNT_HI 0x06cc 865 #define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 1 866 #define regUVD_JMI_CLEAN_STATUS 0x06cd 867 #define regUVD_JMI_CLEAN_STATUS_BASE_IDX 1 868 #define regUVD_JMI_CNTL 0x06ce 869 #define regUVD_JMI_CNTL_BASE_IDX 1 870 871 872 // addressBlock: uvd_uvd_jpeg_common_dec 873 // base address: 0x21400 874 #define regJPEG_SOFT_RESET_STATUS 0x0700 875 #define regJPEG_SOFT_RESET_STATUS_BASE_IDX 1 876 #define regJPEG_SYS_INT_EN 0x0701 877 #define regJPEG_SYS_INT_EN_BASE_IDX 1 878 #define regJPEG_SYS_INT_EN1 0x0702 879 #define regJPEG_SYS_INT_EN1_BASE_IDX 1 880 #define regJPEG_SYS_INT_STATUS 0x0703 881 #define regJPEG_SYS_INT_STATUS_BASE_IDX 1 882 #define regJPEG_SYS_INT_STATUS1 0x0704 883 #define regJPEG_SYS_INT_STATUS1_BASE_IDX 1 884 #define regJPEG_SYS_INT_ACK 0x0705 885 #define regJPEG_SYS_INT_ACK_BASE_IDX 1 886 #define regJPEG_SYS_INT_ACK1 0x0706 887 #define regJPEG_SYS_INT_ACK1_BASE_IDX 1 888 #define regJPEG_MEMCHECK_SYS_INT_EN 0x0707 889 #define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 1 890 #define regJPEG_MEMCHECK_SYS_INT_EN1 0x0708 891 #define regJPEG_MEMCHECK_SYS_INT_EN1_BASE_IDX 1 892 #define regJPEG_MEMCHECK_SYS_INT_STAT 0x0709 893 #define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 1 894 #define regJPEG_MEMCHECK_SYS_INT_STAT1 0x070a 895 #define regJPEG_MEMCHECK_SYS_INT_STAT1_BASE_IDX 1 896 #define regJPEG_MEMCHECK_SYS_INT_STAT2 0x070b 897 #define regJPEG_MEMCHECK_SYS_INT_STAT2_BASE_IDX 1 898 #define regJPEG_MEMCHECK_SYS_INT_ACK 0x070c 899 #define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 1 900 #define regJPEG_MEMCHECK_SYS_INT_ACK1 0x070d 901 #define regJPEG_MEMCHECK_SYS_INT_ACK1_BASE_IDX 1 902 #define regJPEG_MEMCHECK_SYS_INT_ACK2 0x070e 903 #define regJPEG_MEMCHECK_SYS_INT_ACK2_BASE_IDX 1 904 #define regJPEG_MASTINT_EN 0x070f 905 #define regJPEG_MASTINT_EN_BASE_IDX 1 906 #define regJPEG_IH_CTRL 0x0710 907 #define regJPEG_IH_CTRL_BASE_IDX 1 908 #define regJRBBM_ARB_CTRL 0x0712 909 #define regJRBBM_ARB_CTRL_BASE_IDX 1 910 911 912 // addressBlock: uvd_uvd_jpeg_common_sclk_dec 913 // base address: 0x21480 914 #define regJPEG_CGC_GATE 0x0720 915 #define regJPEG_CGC_GATE_BASE_IDX 1 916 #define regJPEG_CGC_CTRL 0x0721 917 #define regJPEG_CGC_CTRL_BASE_IDX 1 918 #define regJPEG_CGC_STATUS 0x0722 919 #define regJPEG_CGC_STATUS_BASE_IDX 1 920 #define regJPEG_COMN_CGC_MEM_CTRL 0x0723 921 #define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 1 922 #define regJPEG_DEC_CGC_MEM_CTRL 0x0724 923 #define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 1 924 #define regJPEG_ENC_CGC_MEM_CTRL 0x0726 925 #define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 1 926 #define regJPEG_PERF_BANK_CONF 0x0727 927 #define regJPEG_PERF_BANK_CONF_BASE_IDX 1 928 #define regJPEG_PERF_BANK_EVENT_SEL 0x0728 929 #define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 1 930 #define regJPEG_PERF_BANK_COUNT0 0x0729 931 #define regJPEG_PERF_BANK_COUNT0_BASE_IDX 1 932 #define regJPEG_PERF_BANK_COUNT1 0x072a 933 #define regJPEG_PERF_BANK_COUNT1_BASE_IDX 1 934 #define regJPEG_PERF_BANK_COUNT2 0x072b 935 #define regJPEG_PERF_BANK_COUNT2_BASE_IDX 1 936 #define regJPEG_PERF_BANK_COUNT3 0x072c 937 #define regJPEG_PERF_BANK_COUNT3_BASE_IDX 1 938 939 940 // addressBlock: uvd_uvd_pg_dec 941 // base address: 0x1f800 942 #define regUVD_IPX_DLDO_CONFIG 0x0000 943 #define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1 944 #define regUVD_IPX_DLDO_STATUS 0x0001 945 #define regUVD_IPX_DLDO_STATUS_BASE_IDX 1 946 #define regUVD_POWER_STATUS 0x0002 947 #define regUVD_POWER_STATUS_BASE_IDX 1 948 #define regUVD_JPEG_POWER_STATUS 0x0003 949 #define regUVD_JPEG_POWER_STATUS_BASE_IDX 1 950 #define regUVD_MC_DJPEG_RD_SPACE 0x0007 951 #define regUVD_MC_DJPEG_RD_SPACE_BASE_IDX 1 952 #define regUVD_MC_DJPEG_WR_SPACE 0x0008 953 #define regUVD_MC_DJPEG_WR_SPACE_BASE_IDX 1 954 #define regUVD_PG_IND_INDEX 0x000c 955 #define regUVD_PG_IND_INDEX_BASE_IDX 1 956 #define regUVD_PG_IND_DATA 0x000e 957 #define regUVD_PG_IND_DATA_BASE_IDX 1 958 #define regCC_UVD_HARVESTING 0x000f 959 #define regCC_UVD_HARVESTING_BASE_IDX 1 960 #define regUVD_DPG_LMA_CTL 0x0011 961 #define regUVD_DPG_LMA_CTL_BASE_IDX 1 962 #define regUVD_DPG_LMA_DATA 0x0012 963 #define regUVD_DPG_LMA_DATA_BASE_IDX 1 964 #define regUVD_DPG_LMA_MASK 0x0013 965 #define regUVD_DPG_LMA_MASK_BASE_IDX 1 966 #define regUVD_DPG_PAUSE 0x0014 967 #define regUVD_DPG_PAUSE_BASE_IDX 1 968 #define regUVD_SCRATCH1 0x0015 969 #define regUVD_SCRATCH1_BASE_IDX 1 970 #define regUVD_SCRATCH2 0x0016 971 #define regUVD_SCRATCH2_BASE_IDX 1 972 #define regUVD_SCRATCH3 0x0017 973 #define regUVD_SCRATCH3_BASE_IDX 1 974 #define regUVD_SCRATCH4 0x0018 975 #define regUVD_SCRATCH4_BASE_IDX 1 976 #define regUVD_SCRATCH5 0x0019 977 #define regUVD_SCRATCH5_BASE_IDX 1 978 #define regUVD_SCRATCH6 0x001a 979 #define regUVD_SCRATCH6_BASE_IDX 1 980 #define regUVD_SCRATCH7 0x001b 981 #define regUVD_SCRATCH7_BASE_IDX 1 982 #define regUVD_SCRATCH8 0x001c 983 #define regUVD_SCRATCH8_BASE_IDX 1 984 #define regUVD_SCRATCH9 0x001d 985 #define regUVD_SCRATCH9_BASE_IDX 1 986 #define regUVD_SCRATCH10 0x001e 987 #define regUVD_SCRATCH10_BASE_IDX 1 988 #define regUVD_SCRATCH11 0x001f 989 #define regUVD_SCRATCH11_BASE_IDX 1 990 #define regUVD_SCRATCH12 0x0020 991 #define regUVD_SCRATCH12_BASE_IDX 1 992 #define regUVD_SCRATCH13 0x0021 993 #define regUVD_SCRATCH13_BASE_IDX 1 994 #define regUVD_SCRATCH14 0x0022 995 #define regUVD_SCRATCH14_BASE_IDX 1 996 #define regUVD_FREE_COUNTER_REG 0x0023 997 #define regUVD_FREE_COUNTER_REG_BASE_IDX 1 998 #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0024 999 #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 1000 #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0025 1001 #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 1002 #define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0026 1003 #define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 1004 #define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0027 1005 #define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 1006 #define regUVD_REG_FILTER_EN 0x0028 1007 #define regUVD_REG_FILTER_EN_BASE_IDX 1 1008 #define regUVD_SECURITY_REG_VIO_REPORT 0x0029 1009 #define regUVD_SECURITY_REG_VIO_REPORT_BASE_IDX 1 1010 #define regUVD_FW_VERSION 0x002a 1011 #define regUVD_FW_VERSION_BASE_IDX 1 1012 #define regUVD_PF_STATUS 0x002c 1013 #define regUVD_PF_STATUS_BASE_IDX 1 1014 #define regUVD_DPG_CLK_EN_VCPU_REPORT 0x002e 1015 #define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 1016 #define regCC_UVD_VCPU_ERR_DETECT_BOT_LO 0x002f 1017 #define regCC_UVD_VCPU_ERR_DETECT_BOT_LO_BASE_IDX 1 1018 #define regCC_UVD_VCPU_ERR_DETECT_BOT_HI 0x0030 1019 #define regCC_UVD_VCPU_ERR_DETECT_BOT_HI_BASE_IDX 1 1020 #define regCC_UVD_VCPU_ERR_DETECT_TOP_LO 0x0031 1021 #define regCC_UVD_VCPU_ERR_DETECT_TOP_LO_BASE_IDX 1 1022 #define regCC_UVD_VCPU_ERR_DETECT_TOP_HI 0x0032 1023 #define regCC_UVD_VCPU_ERR_DETECT_TOP_HI_BASE_IDX 1 1024 #define regCC_UVD_VCPU_ERR 0x0033 1025 #define regCC_UVD_VCPU_ERR_BASE_IDX 1 1026 #define regCC_UVD_VCPU_ERR_INST_ADDR_LO 0x0034 1027 #define regCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX 1 1028 #define regCC_UVD_VCPU_ERR_INST_ADDR_HI 0x0035 1029 #define regCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX 1 1030 #define regUVD_LMI_MMSCH_NC_SPACE 0x003d 1031 #define regUVD_LMI_MMSCH_NC_SPACE_BASE_IDX 1 1032 #define regUVD_LMI_ATOMIC_SPACE 0x003e 1033 #define regUVD_LMI_ATOMIC_SPACE_BASE_IDX 1 1034 #define regUVD_GFX8_ADDR_CONFIG 0x0041 1035 #define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 1036 #define regUVD_GFX10_ADDR_CONFIG 0x0042 1037 #define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 1038 #define regUVD_GPCNT2_CNTL 0x0043 1039 #define regUVD_GPCNT2_CNTL_BASE_IDX 1 1040 #define regUVD_GPCNT2_TARGET_LOWER 0x0044 1041 #define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 1042 #define regUVD_GPCNT2_STATUS_LOWER 0x0045 1043 #define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 1044 #define regUVD_GPCNT2_TARGET_UPPER 0x0046 1045 #define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 1046 #define regUVD_GPCNT2_STATUS_UPPER 0x0047 1047 #define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 1048 #define regUVD_GPCNT3_CNTL 0x0048 1049 #define regUVD_GPCNT3_CNTL_BASE_IDX 1 1050 #define regUVD_GPCNT3_TARGET_LOWER 0x0049 1051 #define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 1052 #define regUVD_GPCNT3_STATUS_LOWER 0x004a 1053 #define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 1054 #define regUVD_GPCNT3_TARGET_UPPER 0x004b 1055 #define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 1056 #define regUVD_GPCNT3_STATUS_UPPER 0x004c 1057 #define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 1058 #define regUVD_VCLK_DS_CNTL 0x004d 1059 #define regUVD_VCLK_DS_CNTL_BASE_IDX 1 1060 #define regUVD_DCLK_DS_CNTL 0x004e 1061 #define regUVD_DCLK_DS_CNTL_BASE_IDX 1 1062 #define regUVD_TSC_LOWER 0x004f 1063 #define regUVD_TSC_LOWER_BASE_IDX 1 1064 #define regUVD_TSC_UPPER 0x0050 1065 #define regUVD_TSC_UPPER_BASE_IDX 1 1066 #define regVCN_FEATURES 0x0051 1067 #define regVCN_FEATURES_BASE_IDX 1 1068 #define regUVD_GPUIOV_STATUS 0x0055 1069 #define regUVD_GPUIOV_STATUS_BASE_IDX 1 1070 #define regUVD_SCRATCH15 0x005c 1071 #define regUVD_SCRATCH15_BASE_IDX 1 1072 #define regUVD_VERSION 0x005d 1073 #define regUVD_VERSION_BASE_IDX 1 1074 #define regVCN_UMSCH_CNTL 0x005e 1075 #define regVCN_UMSCH_CNTL_BASE_IDX 1 1076 #define regVCN_JPEG_DB_CTRL 0x0068 1077 #define regVCN_JPEG_DB_CTRL_BASE_IDX 1 1078 #define regVCN_RB1_DB_CTRL 0x0072 1079 #define regVCN_RB1_DB_CTRL_BASE_IDX 1 1080 #define regVCN_RB2_DB_CTRL 0x0073 1081 #define regVCN_RB2_DB_CTRL_BASE_IDX 1 1082 #define regVCN_RB3_DB_CTRL 0x0074 1083 #define regVCN_RB3_DB_CTRL_BASE_IDX 1 1084 #define regVCN_RB4_DB_CTRL 0x0075 1085 #define regVCN_RB4_DB_CTRL_BASE_IDX 1 1086 #define regVCN_UMSCH_RB_DB_CTRL 0x0076 1087 #define regVCN_UMSCH_RB_DB_CTRL_BASE_IDX 1 1088 #define regVCN_RB_DB_CTRL 0x0077 1089 #define regVCN_RB_DB_CTRL_BASE_IDX 1 1090 #define regVCN_AGDB_CTRL0 0x0079 1091 #define regVCN_AGDB_CTRL0_BASE_IDX 1 1092 #define regVCN_AGDB_CTRL1 0x007a 1093 #define regVCN_AGDB_CTRL1_BASE_IDX 1 1094 #define regVCN_AGDB_CTRL2 0x007b 1095 #define regVCN_AGDB_CTRL2_BASE_IDX 1 1096 #define regVCN_AGDB_CTRL3 0x007c 1097 #define regVCN_AGDB_CTRL3_BASE_IDX 1 1098 #define regVCN_AGDB_CTRL4 0x007d 1099 #define regVCN_AGDB_CTRL4_BASE_IDX 1 1100 #define regVCN_AGDB_CTRL5 0x007e 1101 #define regVCN_AGDB_CTRL5_BASE_IDX 1 1102 #define regVCN_AGDB_MASK0 0x007f 1103 #define regVCN_AGDB_MASK0_BASE_IDX 1 1104 #define regVCN_AGDB_MASK1 0x0080 1105 #define regVCN_AGDB_MASK1_BASE_IDX 1 1106 #define regVCN_AGDB_MASK2 0x0081 1107 #define regVCN_AGDB_MASK2_BASE_IDX 1 1108 #define regVCN_AGDB_MASK3 0x0082 1109 #define regVCN_AGDB_MASK3_BASE_IDX 1 1110 #define regVCN_AGDB_MASK4 0x0083 1111 #define regVCN_AGDB_MASK4_BASE_IDX 1 1112 #define regVCN_AGDB_MASK5 0x0084 1113 #define regVCN_AGDB_MASK5_BASE_IDX 1 1114 #define regVCN_RB_ENABLE 0x0085 1115 #define regVCN_RB_ENABLE_BASE_IDX 1 1116 #define regVCN_RB_WPTR_CTRL 0x0086 1117 #define regVCN_RB_WPTR_CTRL_BASE_IDX 1 1118 #define regUVD_RB_RPTR 0x00ac 1119 #define regUVD_RB_RPTR_BASE_IDX 1 1120 #define regUVD_RB_WPTR 0x00ad 1121 #define regUVD_RB_WPTR_BASE_IDX 1 1122 #define regUVD_RB_RPTR2 0x00ae 1123 #define regUVD_RB_RPTR2_BASE_IDX 1 1124 #define regUVD_RB_WPTR2 0x00af 1125 #define regUVD_RB_WPTR2_BASE_IDX 1 1126 #define regUVD_RB_RPTR3 0x00b0 1127 #define regUVD_RB_RPTR3_BASE_IDX 1 1128 #define regUVD_RB_WPTR3 0x00b1 1129 #define regUVD_RB_WPTR3_BASE_IDX 1 1130 #define regUVD_RB_RPTR4 0x00b2 1131 #define regUVD_RB_RPTR4_BASE_IDX 1 1132 #define regUVD_RB_WPTR4 0x00b3 1133 #define regUVD_RB_WPTR4_BASE_IDX 1 1134 #define regUVD_OUT_RB_RPTR 0x00b4 1135 #define regUVD_OUT_RB_RPTR_BASE_IDX 1 1136 #define regUVD_OUT_RB_WPTR 0x00b5 1137 #define regUVD_OUT_RB_WPTR_BASE_IDX 1 1138 #define regUVD_AUDIO_RB_RPTR 0x00b6 1139 #define regUVD_AUDIO_RB_RPTR_BASE_IDX 1 1140 #define regUVD_AUDIO_RB_WPTR 0x00b7 1141 #define regUVD_AUDIO_RB_WPTR_BASE_IDX 1 1142 #define regUVD_RBC_RB_RPTR 0x00b8 1143 #define regUVD_RBC_RB_RPTR_BASE_IDX 1 1144 #define regUVD_RBC_RB_WPTR 0x00b9 1145 #define regUVD_RBC_RB_WPTR_BASE_IDX 1 1146 #define regUVD_DPG_LMA_CTL2 0x00bb 1147 #define regUVD_DPG_LMA_CTL2_BASE_IDX 1 1148 1149 1150 // addressBlock: uvd_vcn_umsch_dec 1151 // base address: 0x21500 1152 #define regVCN_UMSCH_MES_CNTL 0x0740 1153 #define regVCN_UMSCH_MES_CNTL_BASE_IDX 1 1154 #define regUMSCH_CTL 0x0741 1155 #define regUMSCH_CTL_BASE_IDX 1 1156 #define regUMSCH_CTL2 0x0742 1157 #define regUMSCH_CTL2_BASE_IDX 1 1158 #define regVCN_UMSCH_AGDB_WPTR0 0x0743 1159 #define regVCN_UMSCH_AGDB_WPTR0_BASE_IDX 1 1160 #define regVCN_UMSCH_AGDB_WPTR1 0x0744 1161 #define regVCN_UMSCH_AGDB_WPTR1_BASE_IDX 1 1162 #define regVCN_UMSCH_AGDB_WPTR2 0x0745 1163 #define regVCN_UMSCH_AGDB_WPTR2_BASE_IDX 1 1164 #define regVCN_UMSCH_AGDB_WPTR3 0x0746 1165 #define regVCN_UMSCH_AGDB_WPTR3_BASE_IDX 1 1166 #define regVCN_UMSCH_AGDB_WPTR4 0x0747 1167 #define regVCN_UMSCH_AGDB_WPTR4_BASE_IDX 1 1168 #define regVCN_UMSCH_AGDB_WPTR5 0x0748 1169 #define regVCN_UMSCH_AGDB_WPTR5_BASE_IDX 1 1170 #define regVCN_UMSCH_MAILBOX0 0x0749 1171 #define regVCN_UMSCH_MAILBOX0_BASE_IDX 1 1172 #define regVCN_UMSCH_MAILBOX_RESP0 0x074a 1173 #define regVCN_UMSCH_MAILBOX_RESP0_BASE_IDX 1 1174 #define regVCN_UMSCH_MAILBOX1 0x074b 1175 #define regVCN_UMSCH_MAILBOX1_BASE_IDX 1 1176 #define regVCN_UMSCH_MAILBOX_RESP1 0x074c 1177 #define regVCN_UMSCH_MAILBOX_RESP1_BASE_IDX 1 1178 #define regVCN_UMSCH_MAILBOX2 0x074d 1179 #define regVCN_UMSCH_MAILBOX2_BASE_IDX 1 1180 #define regVCN_UMSCH_MAILBOX_RESP2 0x074e 1181 #define regVCN_UMSCH_MAILBOX_RESP2_BASE_IDX 1 1182 #define regVCN_UMSCH_MAILBOX3 0x074f 1183 #define regVCN_UMSCH_MAILBOX3_BASE_IDX 1 1184 #define regVCN_UMSCH_MAILBOX_RESP3 0x0750 1185 #define regVCN_UMSCH_MAILBOX_RESP3_BASE_IDX 1 1186 #define regVCN_UMSCH_SPARE_REGISTER0 0x0751 1187 #define regVCN_UMSCH_SPARE_REGISTER0_BASE_IDX 1 1188 #define regVCN_UMSCH_SPARE_REGISTER1 0x0752 1189 #define regVCN_UMSCH_SPARE_REGISTER1_BASE_IDX 1 1190 #define regVCN_UMSCH_SPARE_REGISTER2 0x0753 1191 #define regVCN_UMSCH_SPARE_REGISTER2_BASE_IDX 1 1192 #define regVCN_UMSCH_SPARE_REGISTER3 0x0754 1193 #define regVCN_UMSCH_SPARE_REGISTER3_BASE_IDX 1 1194 #define regVCN_UMSCH_SPARE_REGISTER4 0x0755 1195 #define regVCN_UMSCH_SPARE_REGISTER4_BASE_IDX 1 1196 #define regVCN_UMSCH_SPARE_REGISTER5 0x0756 1197 #define regVCN_UMSCH_SPARE_REGISTER5_BASE_IDX 1 1198 #define regVCN_UMSCH_SPARE_REGISTER6 0x0757 1199 #define regVCN_UMSCH_SPARE_REGISTER6_BASE_IDX 1 1200 #define regVCN_UMSCH_SPARE_REGISTER7 0x0758 1201 #define regVCN_UMSCH_SPARE_REGISTER7_BASE_IDX 1 1202 #define regVCN_UMSCH_MES_UTCL1_CNTL 0x0759 1203 #define regVCN_UMSCH_MES_UTCL1_CNTL_BASE_IDX 1 1204 #define regVCN_UMSCH_MES_BUSY 0x075a 1205 #define regVCN_UMSCH_MES_BUSY_BASE_IDX 1 1206 #define regVCN_UMSCH_RB_BASE_LO 0x075b 1207 #define regVCN_UMSCH_RB_BASE_LO_BASE_IDX 1 1208 #define regVCN_UMSCH_RB_BASE_HI 0x075c 1209 #define regVCN_UMSCH_RB_BASE_HI_BASE_IDX 1 1210 #define regVCN_UMSCH_RB_SIZE 0x075d 1211 #define regVCN_UMSCH_RB_SIZE_BASE_IDX 1 1212 #define regVCN_UMSCH_RB_RPTR 0x075e 1213 #define regVCN_UMSCH_RB_RPTR_BASE_IDX 1 1214 #define regVCN_UMSCH_RB_WPTR 0x075f 1215 #define regVCN_UMSCH_RB_WPTR_BASE_IDX 1 1216 #define regVCN_UMSCH_MASTINT_EN 0x0760 1217 #define regVCN_UMSCH_MASTINT_EN_BASE_IDX 1 1218 #define regVCN_UMSCH_IH_CTRL 0x0761 1219 #define regVCN_UMSCH_IH_CTRL_BASE_IDX 1 1220 #define regVCN_UMSCH_SYS_INT_EN 0x0762 1221 #define regVCN_UMSCH_SYS_INT_EN_BASE_IDX 1 1222 #define regVCN_UMSCH_SYS_INT_STATUS 0x0763 1223 #define regVCN_UMSCH_SYS_INT_STATUS_BASE_IDX 1 1224 #define regVCN_UMSCH_SYS_INT_ACK 0x0764 1225 #define regVCN_UMSCH_SYS_INT_ACK_BASE_IDX 1 1226 #define regVCN_UMSCH_SYS_INT_SRC 0x0765 1227 #define regVCN_UMSCH_SYS_INT_SRC_BASE_IDX 1 1228 #define regVCN_UMSCH_IH_CTX_CTRL 0x0766 1229 #define regVCN_UMSCH_IH_CTX_CTRL_BASE_IDX 1 1230 #define regUVD_UMSCH_FORCE 0x076b 1231 #define regUVD_UMSCH_FORCE_BASE_IDX 1 1232 #define regUMSCH_MES_RESET_CTRL 0x0770 1233 #define regUMSCH_MES_RESET_CTRL_BASE_IDX 1 1234 1235 1236 // addressBlock: uvd_vcn_cprs64dec 1237 // base address: 0x21600 1238 #define regVCN_MES_PRGRM_CNTR_START 0x0780 1239 #define regVCN_MES_PRGRM_CNTR_START_BASE_IDX 1 1240 #define regVCN_MES_INTR_ROUTINE_START 0x0781 1241 #define regVCN_MES_INTR_ROUTINE_START_BASE_IDX 1 1242 #define regVCN_MES_MTVEC_LO 0x0781 1243 #define regVCN_MES_MTVEC_LO_BASE_IDX 1 1244 #define regVCN_MES_INTR_ROUTINE_START_HI 0x0782 1245 #define regVCN_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 1246 #define regVCN_MES_MTVEC_HI 0x0782 1247 #define regVCN_MES_MTVEC_HI_BASE_IDX 1 1248 #define regVCN_MES_CNTL 0x0787 1249 #define regVCN_MES_CNTL_BASE_IDX 1 1250 #define regVCN_MES_PIPE_PRIORITY_CNTS 0x0788 1251 #define regVCN_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 1252 #define regVCN_MES_PIPE0_PRIORITY 0x0789 1253 #define regVCN_MES_PIPE0_PRIORITY_BASE_IDX 1 1254 #define regVCN_MES_PIPE1_PRIORITY 0x078a 1255 #define regVCN_MES_PIPE1_PRIORITY_BASE_IDX 1 1256 #define regVCN_MES_PIPE2_PRIORITY 0x078b 1257 #define regVCN_MES_PIPE2_PRIORITY_BASE_IDX 1 1258 #define regVCN_MES_PIPE3_PRIORITY 0x078c 1259 #define regVCN_MES_PIPE3_PRIORITY_BASE_IDX 1 1260 #define regVCN_MES_HEADER_DUMP 0x078d 1261 #define regVCN_MES_HEADER_DUMP_BASE_IDX 1 1262 #define regVCN_MES_MIE_LO 0x078e 1263 #define regVCN_MES_MIE_LO_BASE_IDX 1 1264 #define regVCN_MES_MIE_HI 0x078f 1265 #define regVCN_MES_MIE_HI_BASE_IDX 1 1266 #define regVCN_MES_INTERRUPT 0x0790 1267 #define regVCN_MES_INTERRUPT_BASE_IDX 1 1268 #define regVCN_MES_SCRATCH_INDEX 0x0791 1269 #define regVCN_MES_SCRATCH_INDEX_BASE_IDX 1 1270 #define regVCN_MES_SCRATCH_DATA 0x0792 1271 #define regVCN_MES_SCRATCH_DATA_BASE_IDX 1 1272 #define regVCN_MES_INSTR_PNTR 0x0793 1273 #define regVCN_MES_INSTR_PNTR_BASE_IDX 1 1274 #define regVCN_MES_MSCRATCH_HI 0x0794 1275 #define regVCN_MES_MSCRATCH_HI_BASE_IDX 1 1276 #define regVCN_MES_MSCRATCH_LO 0x0795 1277 #define regVCN_MES_MSCRATCH_LO_BASE_IDX 1 1278 #define regVCN_MES_MSTATUS_LO 0x0796 1279 #define regVCN_MES_MSTATUS_LO_BASE_IDX 1 1280 #define regVCN_MES_MSTATUS_HI 0x0797 1281 #define regVCN_MES_MSTATUS_HI_BASE_IDX 1 1282 #define regVCN_MES_MEPC_LO 0x0798 1283 #define regVCN_MES_MEPC_LO_BASE_IDX 1 1284 #define regVCN_MES_MEPC_HI 0x0799 1285 #define regVCN_MES_MEPC_HI_BASE_IDX 1 1286 #define regVCN_MES_MCAUSE_LO 0x079a 1287 #define regVCN_MES_MCAUSE_LO_BASE_IDX 1 1288 #define regVCN_MES_MCAUSE_HI 0x079b 1289 #define regVCN_MES_MCAUSE_HI_BASE_IDX 1 1290 #define regVCN_MES_MBADADDR_LO 0x079c 1291 #define regVCN_MES_MBADADDR_LO_BASE_IDX 1 1292 #define regVCN_MES_MBADADDR_HI 0x079d 1293 #define regVCN_MES_MBADADDR_HI_BASE_IDX 1 1294 #define regVCN_MES_MIP_LO 0x079e 1295 #define regVCN_MES_MIP_LO_BASE_IDX 1 1296 #define regVCN_MES_MIP_HI 0x079f 1297 #define regVCN_MES_MIP_HI_BASE_IDX 1 1298 #define regVCN_MES_IC_OP_CNTL 0x07a0 1299 #define regVCN_MES_IC_OP_CNTL_BASE_IDX 1 1300 #define regVCN_MES_MCYCLE_LO 0x07a6 1301 #define regVCN_MES_MCYCLE_LO_BASE_IDX 1 1302 #define regVCN_MES_MCYCLE_HI 0x07a7 1303 #define regVCN_MES_MCYCLE_HI_BASE_IDX 1 1304 #define regVCN_MES_MTIME_LO 0x07a8 1305 #define regVCN_MES_MTIME_LO_BASE_IDX 1 1306 #define regVCN_MES_MTIME_HI 0x07a9 1307 #define regVCN_MES_MTIME_HI_BASE_IDX 1 1308 #define regVCN_MES_MINSTRET_LO 0x07aa 1309 #define regVCN_MES_MINSTRET_LO_BASE_IDX 1 1310 #define regVCN_MES_MINSTRET_HI 0x07ab 1311 #define regVCN_MES_MINSTRET_HI_BASE_IDX 1 1312 #define regVCN_MES_MISA_LO 0x07ac 1313 #define regVCN_MES_MISA_LO_BASE_IDX 1 1314 #define regVCN_MES_MISA_HI 0x07ad 1315 #define regVCN_MES_MISA_HI_BASE_IDX 1 1316 #define regVCN_MES_MVENDORID_LO 0x07ae 1317 #define regVCN_MES_MVENDORID_LO_BASE_IDX 1 1318 #define regVCN_MES_MVENDORID_HI 0x07af 1319 #define regVCN_MES_MVENDORID_HI_BASE_IDX 1 1320 #define regVCN_MES_MARCHID_LO 0x07b0 1321 #define regVCN_MES_MARCHID_LO_BASE_IDX 1 1322 #define regVCN_MES_MARCHID_HI 0x07b1 1323 #define regVCN_MES_MARCHID_HI_BASE_IDX 1 1324 #define regVCN_MES_MIMPID_LO 0x07b2 1325 #define regVCN_MES_MIMPID_LO_BASE_IDX 1 1326 #define regVCN_MES_MIMPID_HI 0x07b3 1327 #define regVCN_MES_MIMPID_HI_BASE_IDX 1 1328 #define regVCN_MES_MHARTID_LO 0x07b4 1329 #define regVCN_MES_MHARTID_LO_BASE_IDX 1 1330 #define regVCN_MES_MHARTID_HI 0x07b5 1331 #define regVCN_MES_MHARTID_HI_BASE_IDX 1 1332 #define regVCN_MES_DC_BASE_CNTL 0x07b6 1333 #define regVCN_MES_DC_BASE_CNTL_BASE_IDX 1 1334 #define regVCN_MES_DC_OP_CNTL 0x07b7 1335 #define regVCN_MES_DC_OP_CNTL_BASE_IDX 1 1336 #define regVCN_MES_MTIMECMP_LO 0x07b8 1337 #define regVCN_MES_MTIMECMP_LO_BASE_IDX 1 1338 #define regVCN_MES_MTIMECMP_HI 0x07b9 1339 #define regVCN_MES_MTIMECMP_HI_BASE_IDX 1 1340 #define regVCN_MES_GP0_LO 0x07c3 1341 #define regVCN_MES_GP0_LO_BASE_IDX 1 1342 #define regVCN_MES_GP0_HI 0x07c4 1343 #define regVCN_MES_GP0_HI_BASE_IDX 1 1344 #define regVCN_MES_GP1_LO 0x07c5 1345 #define regVCN_MES_GP1_LO_BASE_IDX 1 1346 #define regVCN_MES_GP1_HI 0x07c6 1347 #define regVCN_MES_GP1_HI_BASE_IDX 1 1348 #define regVCN_MES_GP2_LO 0x07c7 1349 #define regVCN_MES_GP2_LO_BASE_IDX 1 1350 #define regVCN_MES_GP2_HI 0x07c8 1351 #define regVCN_MES_GP2_HI_BASE_IDX 1 1352 #define regVCN_MES_GP3_LO 0x07c9 1353 #define regVCN_MES_GP3_LO_BASE_IDX 1 1354 #define regVCN_MES_GP3_HI 0x07ca 1355 #define regVCN_MES_GP3_HI_BASE_IDX 1 1356 #define regVCN_MES_GP4_LO 0x07cb 1357 #define regVCN_MES_GP4_LO_BASE_IDX 1 1358 #define regVCN_MES_GP4_HI 0x07cc 1359 #define regVCN_MES_GP4_HI_BASE_IDX 1 1360 #define regVCN_MES_GP5_LO 0x07cd 1361 #define regVCN_MES_GP5_LO_BASE_IDX 1 1362 #define regVCN_MES_GP5_HI 0x07ce 1363 #define regVCN_MES_GP5_HI_BASE_IDX 1 1364 #define regVCN_MES_GP6_LO 0x07cf 1365 #define regVCN_MES_GP6_LO_BASE_IDX 1 1366 #define regVCN_MES_GP6_HI 0x07d0 1367 #define regVCN_MES_GP6_HI_BASE_IDX 1 1368 #define regVCN_MES_GP7_LO 0x07d1 1369 #define regVCN_MES_GP7_LO_BASE_IDX 1 1370 #define regVCN_MES_GP7_HI 0x07d2 1371 #define regVCN_MES_GP7_HI_BASE_IDX 1 1372 #define regVCN_MES_GP8_LO 0x07d3 1373 #define regVCN_MES_GP8_LO_BASE_IDX 1 1374 #define regVCN_MES_GP8_HI 0x07d4 1375 #define regVCN_MES_GP8_HI_BASE_IDX 1 1376 #define regVCN_MES_GP9_LO 0x07d5 1377 #define regVCN_MES_GP9_LO_BASE_IDX 1 1378 #define regVCN_MES_GP9_HI 0x07d6 1379 #define regVCN_MES_GP9_HI_BASE_IDX 1 1380 #define regVCN_MES_DM_INDEX_ADDR 0x0800 1381 #define regVCN_MES_DM_INDEX_ADDR_BASE_IDX 1 1382 #define regVCN_MES_DM_INDEX_DATA 0x0801 1383 #define regVCN_MES_DM_INDEX_DATA_BASE_IDX 1 1384 #define regVCN_MES_LOCAL_BASE0_LO 0x0803 1385 #define regVCN_MES_LOCAL_BASE0_LO_BASE_IDX 1 1386 #define regVCN_MES_LOCAL_BASE0_HI 0x0804 1387 #define regVCN_MES_LOCAL_BASE0_HI_BASE_IDX 1 1388 #define regVCN_MES_LOCAL_MASK0_LO 0x0805 1389 #define regVCN_MES_LOCAL_MASK0_LO_BASE_IDX 1 1390 #define regVCN_MES_LOCAL_MASK0_HI 0x0806 1391 #define regVCN_MES_LOCAL_MASK0_HI_BASE_IDX 1 1392 #define regVCN_MES_LOCAL_APERTURE 0x0807 1393 #define regVCN_MES_LOCAL_APERTURE_BASE_IDX 1 1394 #define regVCN_MES_LOCAL_INSTR_BASE_LO 0x0808 1395 #define regVCN_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 1396 #define regVCN_MES_LOCAL_INSTR_BASE_HI 0x0809 1397 #define regVCN_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 1398 #define regVCN_MES_LOCAL_INSTR_MASK_LO 0x080a 1399 #define regVCN_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 1400 #define regVCN_MES_LOCAL_INSTR_MASK_HI 0x080b 1401 #define regVCN_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 1402 #define regVCN_MES_LOCAL_INSTR_APERTURE 0x080c 1403 #define regVCN_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 1404 #define regVCN_MES_LOCAL_SCRATCH_APERTURE 0x080d 1405 #define regVCN_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 1406 #define regVCN_MES_LOCAL_SCRATCH_BASE_LO 0x080e 1407 #define regVCN_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 1408 #define regVCN_MES_LOCAL_SCRATCH_BASE_HI 0x080f 1409 #define regVCN_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 1410 #define regVCN_MES_PERFCOUNT_CNTL 0x0819 1411 #define regVCN_MES_PERFCOUNT_CNTL_BASE_IDX 1 1412 #define regVCN_MES_PENDING_INTERRUPT 0x081a 1413 #define regVCN_MES_PENDING_INTERRUPT_BASE_IDX 1 1414 #define regVCN_MES_PRGRM_CNTR_START_HI 0x081d 1415 #define regVCN_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 1416 #define regVCN_MES_INTERRUPT_DATA_16 0x081f 1417 #define regVCN_MES_INTERRUPT_DATA_16_BASE_IDX 1 1418 #define regVCN_MES_INTERRUPT_DATA_17 0x0820 1419 #define regVCN_MES_INTERRUPT_DATA_17_BASE_IDX 1 1420 #define regVCN_MES_INTERRUPT_DATA_18 0x0821 1421 #define regVCN_MES_INTERRUPT_DATA_18_BASE_IDX 1 1422 #define regVCN_MES_INTERRUPT_DATA_19 0x0822 1423 #define regVCN_MES_INTERRUPT_DATA_19_BASE_IDX 1 1424 #define regVCN_MES_INTERRUPT_DATA_20 0x0823 1425 #define regVCN_MES_INTERRUPT_DATA_20_BASE_IDX 1 1426 #define regVCN_MES_INTERRUPT_DATA_21 0x0824 1427 #define regVCN_MES_INTERRUPT_DATA_21_BASE_IDX 1 1428 #define regVCN_MES_INTERRUPT_DATA_22 0x0825 1429 #define regVCN_MES_INTERRUPT_DATA_22_BASE_IDX 1 1430 #define regVCN_MES_INTERRUPT_DATA_23 0x0826 1431 #define regVCN_MES_INTERRUPT_DATA_23_BASE_IDX 1 1432 #define regVCN_MES_INTERRUPT_DATA_24 0x0827 1433 #define regVCN_MES_INTERRUPT_DATA_24_BASE_IDX 1 1434 #define regVCN_MES_INTERRUPT_DATA_25 0x0828 1435 #define regVCN_MES_INTERRUPT_DATA_25_BASE_IDX 1 1436 #define regVCN_MES_INTERRUPT_DATA_26 0x0829 1437 #define regVCN_MES_INTERRUPT_DATA_26_BASE_IDX 1 1438 #define regVCN_MES_INTERRUPT_DATA_27 0x082a 1439 #define regVCN_MES_INTERRUPT_DATA_27_BASE_IDX 1 1440 #define regVCN_MES_INTERRUPT_DATA_28 0x082b 1441 #define regVCN_MES_INTERRUPT_DATA_28_BASE_IDX 1 1442 #define regVCN_MES_INTERRUPT_DATA_29 0x082c 1443 #define regVCN_MES_INTERRUPT_DATA_29_BASE_IDX 1 1444 #define regVCN_MES_INTERRUPT_DATA_30 0x082d 1445 #define regVCN_MES_INTERRUPT_DATA_30_BASE_IDX 1 1446 #define regVCN_MES_INTERRUPT_DATA_31 0x082e 1447 #define regVCN_MES_INTERRUPT_DATA_31_BASE_IDX 1 1448 #define regVCN_MES_DC_APERTURE0_BASE 0x082f 1449 #define regVCN_MES_DC_APERTURE0_BASE_BASE_IDX 1 1450 #define regVCN_MES_DC_APERTURE0_MASK 0x0830 1451 #define regVCN_MES_DC_APERTURE0_MASK_BASE_IDX 1 1452 #define regVCN_MES_DC_APERTURE0_CNTL 0x0831 1453 #define regVCN_MES_DC_APERTURE0_CNTL_BASE_IDX 1 1454 #define regVCN_MES_DC_APERTURE1_BASE 0x0832 1455 #define regVCN_MES_DC_APERTURE1_BASE_BASE_IDX 1 1456 #define regVCN_MES_DC_APERTURE1_MASK 0x0833 1457 #define regVCN_MES_DC_APERTURE1_MASK_BASE_IDX 1 1458 #define regVCN_MES_DC_APERTURE1_CNTL 0x0834 1459 #define regVCN_MES_DC_APERTURE1_CNTL_BASE_IDX 1 1460 #define regVCN_MES_DC_APERTURE2_BASE 0x0835 1461 #define regVCN_MES_DC_APERTURE2_BASE_BASE_IDX 1 1462 #define regVCN_MES_DC_APERTURE2_MASK 0x0836 1463 #define regVCN_MES_DC_APERTURE2_MASK_BASE_IDX 1 1464 #define regVCN_MES_DC_APERTURE2_CNTL 0x0837 1465 #define regVCN_MES_DC_APERTURE2_CNTL_BASE_IDX 1 1466 #define regVCN_MES_DC_APERTURE3_BASE 0x0838 1467 #define regVCN_MES_DC_APERTURE3_BASE_BASE_IDX 1 1468 #define regVCN_MES_DC_APERTURE3_MASK 0x0839 1469 #define regVCN_MES_DC_APERTURE3_MASK_BASE_IDX 1 1470 #define regVCN_MES_DC_APERTURE3_CNTL 0x083a 1471 #define regVCN_MES_DC_APERTURE3_CNTL_BASE_IDX 1 1472 #define regVCN_MES_DC_APERTURE4_BASE 0x083b 1473 #define regVCN_MES_DC_APERTURE4_BASE_BASE_IDX 1 1474 #define regVCN_MES_DC_APERTURE4_MASK 0x083c 1475 #define regVCN_MES_DC_APERTURE4_MASK_BASE_IDX 1 1476 #define regVCN_MES_DC_APERTURE4_CNTL 0x083d 1477 #define regVCN_MES_DC_APERTURE4_CNTL_BASE_IDX 1 1478 #define regVCN_MES_DC_APERTURE5_BASE 0x083e 1479 #define regVCN_MES_DC_APERTURE5_BASE_BASE_IDX 1 1480 #define regVCN_MES_DC_APERTURE5_MASK 0x083f 1481 #define regVCN_MES_DC_APERTURE5_MASK_BASE_IDX 1 1482 #define regVCN_MES_DC_APERTURE5_CNTL 0x0840 1483 #define regVCN_MES_DC_APERTURE5_CNTL_BASE_IDX 1 1484 #define regVCN_MES_DC_APERTURE6_BASE 0x0841 1485 #define regVCN_MES_DC_APERTURE6_BASE_BASE_IDX 1 1486 #define regVCN_MES_DC_APERTURE6_MASK 0x0842 1487 #define regVCN_MES_DC_APERTURE6_MASK_BASE_IDX 1 1488 #define regVCN_MES_DC_APERTURE6_CNTL 0x0843 1489 #define regVCN_MES_DC_APERTURE6_CNTL_BASE_IDX 1 1490 #define regVCN_MES_DC_APERTURE7_BASE 0x0844 1491 #define regVCN_MES_DC_APERTURE7_BASE_BASE_IDX 1 1492 #define regVCN_MES_DC_APERTURE7_MASK 0x0845 1493 #define regVCN_MES_DC_APERTURE7_MASK_BASE_IDX 1 1494 #define regVCN_MES_DC_APERTURE7_CNTL 0x0846 1495 #define regVCN_MES_DC_APERTURE7_CNTL_BASE_IDX 1 1496 #define regVCN_MES_DC_APERTURE8_BASE 0x0847 1497 #define regVCN_MES_DC_APERTURE8_BASE_BASE_IDX 1 1498 #define regVCN_MES_DC_APERTURE8_MASK 0x0848 1499 #define regVCN_MES_DC_APERTURE8_MASK_BASE_IDX 1 1500 #define regVCN_MES_DC_APERTURE8_CNTL 0x0849 1501 #define regVCN_MES_DC_APERTURE8_CNTL_BASE_IDX 1 1502 #define regVCN_MES_DC_APERTURE9_BASE 0x084a 1503 #define regVCN_MES_DC_APERTURE9_BASE_BASE_IDX 1 1504 #define regVCN_MES_DC_APERTURE9_MASK 0x084b 1505 #define regVCN_MES_DC_APERTURE9_MASK_BASE_IDX 1 1506 #define regVCN_MES_DC_APERTURE9_CNTL 0x084c 1507 #define regVCN_MES_DC_APERTURE9_CNTL_BASE_IDX 1 1508 #define regVCN_MES_DC_APERTURE10_BASE 0x084d 1509 #define regVCN_MES_DC_APERTURE10_BASE_BASE_IDX 1 1510 #define regVCN_MES_DC_APERTURE10_MASK 0x084e 1511 #define regVCN_MES_DC_APERTURE10_MASK_BASE_IDX 1 1512 #define regVCN_MES_DC_APERTURE10_CNTL 0x084f 1513 #define regVCN_MES_DC_APERTURE10_CNTL_BASE_IDX 1 1514 #define regVCN_MES_DC_APERTURE11_BASE 0x0850 1515 #define regVCN_MES_DC_APERTURE11_BASE_BASE_IDX 1 1516 #define regVCN_MES_DC_APERTURE11_MASK 0x0851 1517 #define regVCN_MES_DC_APERTURE11_MASK_BASE_IDX 1 1518 #define regVCN_MES_DC_APERTURE11_CNTL 0x0852 1519 #define regVCN_MES_DC_APERTURE11_CNTL_BASE_IDX 1 1520 #define regVCN_MES_DC_APERTURE12_BASE 0x0853 1521 #define regVCN_MES_DC_APERTURE12_BASE_BASE_IDX 1 1522 #define regVCN_MES_DC_APERTURE12_MASK 0x0854 1523 #define regVCN_MES_DC_APERTURE12_MASK_BASE_IDX 1 1524 #define regVCN_MES_DC_APERTURE12_CNTL 0x0855 1525 #define regVCN_MES_DC_APERTURE12_CNTL_BASE_IDX 1 1526 #define regVCN_MES_DC_APERTURE13_BASE 0x0856 1527 #define regVCN_MES_DC_APERTURE13_BASE_BASE_IDX 1 1528 #define regVCN_MES_DC_APERTURE13_MASK 0x0857 1529 #define regVCN_MES_DC_APERTURE13_MASK_BASE_IDX 1 1530 #define regVCN_MES_DC_APERTURE13_CNTL 0x0858 1531 #define regVCN_MES_DC_APERTURE13_CNTL_BASE_IDX 1 1532 #define regVCN_MES_DC_APERTURE14_BASE 0x0859 1533 #define regVCN_MES_DC_APERTURE14_BASE_BASE_IDX 1 1534 #define regVCN_MES_DC_APERTURE14_MASK 0x085a 1535 #define regVCN_MES_DC_APERTURE14_MASK_BASE_IDX 1 1536 #define regVCN_MES_DC_APERTURE14_CNTL 0x085b 1537 #define regVCN_MES_DC_APERTURE14_CNTL_BASE_IDX 1 1538 #define regVCN_MES_DC_APERTURE15_BASE 0x085c 1539 #define regVCN_MES_DC_APERTURE15_BASE_BASE_IDX 1 1540 #define regVCN_MES_DC_APERTURE15_MASK 0x085d 1541 #define regVCN_MES_DC_APERTURE15_MASK_BASE_IDX 1 1542 #define regVCN_MES_DC_APERTURE15_CNTL 0x085e 1543 #define regVCN_MES_DC_APERTURE15_CNTL_BASE_IDX 1 1544 1545 1546 // addressBlock: uvd_vcn_hypdec 1547 // base address: 0x21a00 1548 #define regVCN_MES_IC_BASE_LO 0x08d0 1549 #define regVCN_MES_IC_BASE_LO_BASE_IDX 1 1550 #define regVCN_MES_MIBASE_LO 0x08d0 1551 #define regVCN_MES_MIBASE_LO_BASE_IDX 1 1552 #define regVCN_MES_IC_BASE_HI 0x08d1 1553 #define regVCN_MES_IC_BASE_HI_BASE_IDX 1 1554 #define regVCN_MES_MIBASE_HI 0x08d1 1555 #define regVCN_MES_MIBASE_HI_BASE_IDX 1 1556 #define regVCN_MES_IC_BASE_CNTL 0x08d2 1557 #define regVCN_MES_IC_BASE_CNTL_BASE_IDX 1 1558 #define regVCN_MES_DC_BASE_LO 0x08d4 1559 #define regVCN_MES_DC_BASE_LO_BASE_IDX 1 1560 #define regVCN_MES_MDBASE_LO 0x08d4 1561 #define regVCN_MES_MDBASE_LO_BASE_IDX 1 1562 #define regVCN_MES_DC_BASE_HI 0x08d5 1563 #define regVCN_MES_DC_BASE_HI_BASE_IDX 1 1564 #define regVCN_MES_MDBASE_HI 0x08d5 1565 #define regVCN_MES_MDBASE_HI_BASE_IDX 1 1566 #define regVCN_MES_MIBOUND_LO 0x08db 1567 #define regVCN_MES_MIBOUND_LO_BASE_IDX 1 1568 #define regVCN_MES_MIBOUND_HI 0x08dc 1569 #define regVCN_MES_MIBOUND_HI_BASE_IDX 1 1570 #define regVCN_MES_MDBOUND_LO 0x08dd 1571 #define regVCN_MES_MDBOUND_LO_BASE_IDX 1 1572 #define regVCN_MES_MDBOUND_HI 0x08de 1573 #define regVCN_MES_MDBOUND_HI_BASE_IDX 1 1574 1575 1576 // addressBlock: uvd_slmi_adpdec 1577 // base address: 0x21c00 1578 #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x0900 1579 #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 1580 #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x0901 1581 #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 1582 #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x0902 1583 #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 1584 #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0903 1585 #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 1586 #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0904 1587 #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 1588 #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0905 1589 #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 1590 #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0906 1591 #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 1592 #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0907 1593 #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 1594 #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0908 1595 #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 1596 #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0909 1597 #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 1598 #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x090a 1599 #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 1600 #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x090b 1601 #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 1602 #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x090c 1603 #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 1604 #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x090d 1605 #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 1606 #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x090e 1607 #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 1608 #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x090f 1609 #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 1610 #define regUVD_LMI_MMSCH_NC_VMID 0x0910 1611 #define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 1612 #define regUVD_LMI_MMSCH_CTRL 0x0911 1613 #define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1 1614 #define regUVD_MMSCH_LMI_STATUS 0x0912 1615 #define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1 1616 #define regUMSCH_IOV_ACTIVE_FCN_ID 0x0920 1617 #define regUMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX 1 1618 #define regUVD_UMSCH_LMI_STATUS 0x0923 1619 #define regUVD_UMSCH_LMI_STATUS_BASE_IDX 1 1620 1621 1622 // addressBlock: uvdctxind 1623 // base address: 0x0 1624 #define ixUVD_CGC_MEM_CTRL 0x0000 1625 #define ixUVD_CGC_CTRL2 0x0001 1626 #define ixUVD_CGC_MEM_DS_CTRL 0x0002 1627 #define ixUVD_CGC_MEM_SD_CTRL 0x0003 1628 #define ixUVD_SW_SCRATCH_00 0x0004 1629 #define ixUVD_SW_SCRATCH_01 0x0005 1630 #define ixUVD_SW_SCRATCH_02 0x0006 1631 #define ixUVD_SW_SCRATCH_03 0x0007 1632 #define ixUVD_SW_SCRATCH_04 0x0008 1633 #define ixUVD_SW_SCRATCH_05 0x0009 1634 #define ixUVD_SW_SCRATCH_06 0x000a 1635 #define ixUVD_SW_SCRATCH_07 0x000b 1636 #define ixUVD_SW_SCRATCH_08 0x000c 1637 #define ixUVD_SW_SCRATCH_09 0x000d 1638 #define ixUVD_SW_SCRATCH_10 0x000e 1639 #define ixUVD_SW_SCRATCH_11 0x000f 1640 #define ixUVD_SW_SCRATCH_12 0x0010 1641 #define ixUVD_SW_SCRATCH_13 0x0011 1642 #define ixUVD_SW_SCRATCH_14 0x0012 1643 #define ixUVD_SW_SCRATCH_15 0x0013 1644 #define ixUVD_IH_SEM_CTRL 0x001e 1645 1646 1647 // addressBlock: lmi_adp_indirect 1648 // base address: 0x0 1649 #define ixUVD_LMI_CRC0 0x0000 1650 #define ixUVD_LMI_CRC1 0x0001 1651 #define ixUVD_LMI_CRC2 0x0002 1652 #define ixUVD_LMI_CRC3 0x0003 1653 #define ixUVD_LMI_CRC10 0x000a 1654 #define ixUVD_LMI_CRC11 0x000b 1655 #define ixUVD_LMI_CRC12 0x000c 1656 #define ixUVD_LMI_CRC13 0x000d 1657 #define ixUVD_LMI_CRC14 0x000e 1658 #define ixUVD_LMI_CRC15 0x000f 1659 #define ixUVD_LMI_SWAP_CNTL2 0x0029 1660 #define ixUVD_MEMCHECK_SYS_INT_EN 0x0134 1661 #define ixUVD_MEMCHECK_SYS_INT_STAT 0x0135 1662 #define ixUVD_MEMCHECK_SYS_INT_ACK 0x0136 1663 #define ixUVD_MEMCHECK_VCPU_INT_EN 0x0137 1664 #define ixUVD_MEMCHECK_VCPU_INT_STAT 0x0138 1665 #define ixUVD_MEMCHECK_VCPU_INT_ACK 0x0139 1666 #define ixUVD_MEMCHECK2_SYS_INT_STAT 0x0140 1667 #define ixUVD_MEMCHECK2_SYS_INT_ACK 0x0141 1668 #define ixUVD_MEMCHECK2_VCPU_INT_STAT 0x0142 1669 #define ixUVD_MEMCHECK2_VCPU_INT_ACK 0x0143 1670 1671 1672 #endif 1673