1 /* 2 * UVD_5_0 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef UVD_5_0_SH_MASK_H 25 #define UVD_5_0_SH_MASK_H 26 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35 #define UVD_SEMA_CMD__MODE_MASK 0x40 36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 37 #define UVD_SEMA_CMD__VMID_EN_MASK 0x80 38 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 39 #define UVD_SEMA_CMD__VMID_MASK 0xf00 40 #define UVD_SEMA_CMD__VMID__SHIFT 0x8 41 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 42 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 43 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 44 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 45 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 46 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 47 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 48 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 49 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 50 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 51 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 52 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 53 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 54 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 55 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 56 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 57 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 58 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 59 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 60 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 61 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 62 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 63 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 64 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 65 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 66 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 67 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 68 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 69 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 70 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 71 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 72 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 73 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 74 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 75 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 76 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 77 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 78 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 79 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 80 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 81 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 82 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 83 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 84 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 85 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 86 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 87 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 88 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 89 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 90 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 91 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 92 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 93 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 94 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 95 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 96 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 97 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 98 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 99 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 100 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 101 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 102 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 103 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 104 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 105 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 106 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 107 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 108 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 109 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 110 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 111 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 112 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 113 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 114 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 115 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 116 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 117 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 118 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 119 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 120 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 121 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 122 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 123 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 124 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 125 #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 126 #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 127 #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 128 #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 129 #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 130 #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 131 #define UVD_CTX_INDEX__INDEX_MASK 0x1ff 132 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 133 #define UVD_CTX_DATA__DATA_MASK 0xffffffff 134 #define UVD_CTX_DATA__DATA__SHIFT 0x0 135 #define UVD_CGC_GATE__SYS_MASK 0x1 136 #define UVD_CGC_GATE__SYS__SHIFT 0x0 137 #define UVD_CGC_GATE__UDEC_MASK 0x2 138 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 139 #define UVD_CGC_GATE__MPEG2_MASK 0x4 140 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 141 #define UVD_CGC_GATE__REGS_MASK 0x8 142 #define UVD_CGC_GATE__REGS__SHIFT 0x3 143 #define UVD_CGC_GATE__RBC_MASK 0x10 144 #define UVD_CGC_GATE__RBC__SHIFT 0x4 145 #define UVD_CGC_GATE__LMI_MC_MASK 0x20 146 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 147 #define UVD_CGC_GATE__LMI_UMC_MASK 0x40 148 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 149 #define UVD_CGC_GATE__IDCT_MASK 0x80 150 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 151 #define UVD_CGC_GATE__MPRD_MASK 0x100 152 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 153 #define UVD_CGC_GATE__MPC_MASK 0x200 154 #define UVD_CGC_GATE__MPC__SHIFT 0x9 155 #define UVD_CGC_GATE__LBSI_MASK 0x400 156 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 157 #define UVD_CGC_GATE__LRBBM_MASK 0x800 158 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 159 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 160 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 161 #define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 162 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 163 #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 164 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 165 #define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 166 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 167 #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 168 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 169 #define UVD_CGC_GATE__WCB_MASK 0x20000 170 #define UVD_CGC_GATE__WCB__SHIFT 0x11 171 #define UVD_CGC_GATE__VCPU_MASK 0x40000 172 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 173 #define UVD_CGC_GATE__SCPU_MASK 0x80000 174 #define UVD_CGC_GATE__SCPU__SHIFT 0x13 175 #define UVD_CGC_GATE__JPEG_MASK 0x100000 176 #define UVD_CGC_GATE__JPEG__SHIFT 0x14 177 #define UVD_CGC_GATE__JPEG2_MASK 0x200000 178 #define UVD_CGC_GATE__JPEG2__SHIFT 0x15 179 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 180 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 181 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 182 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 183 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 184 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 185 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 186 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 187 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 188 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 189 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 190 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 191 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 192 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 193 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 194 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 195 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 196 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 197 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 198 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 199 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 200 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 201 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 202 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 203 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 204 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 205 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 206 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 207 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 208 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 209 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 210 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 211 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 212 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 213 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 214 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 215 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 216 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 217 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 218 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 219 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 220 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 221 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 222 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 223 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 224 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 225 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 226 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 227 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 228 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 229 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 230 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 231 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 232 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 233 #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 234 #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 235 #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 236 #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 237 #define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000 238 #define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e 239 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000 240 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 241 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 242 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 243 #define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2 244 #define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 245 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 246 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 247 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 248 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 249 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 250 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 251 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 252 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 253 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 254 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 255 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 256 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 257 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 258 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 259 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 260 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 261 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 262 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 263 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 264 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 265 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 266 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 267 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 268 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 269 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 270 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 271 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 272 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 273 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 274 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 275 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 276 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 277 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 278 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 279 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 280 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 281 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 282 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 283 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 284 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 285 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 286 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 287 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 288 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 289 #define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000 290 #define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f 291 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 292 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 293 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 294 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 295 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 296 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 297 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 298 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 299 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 300 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 301 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 302 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 303 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 304 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 305 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 306 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 307 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 308 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 309 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 310 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 311 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 312 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 313 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 314 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 315 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 316 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 317 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 318 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 319 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 320 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 321 #define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000 322 #define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf 323 #define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000 324 #define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10 325 #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000 326 #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11 327 #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000 328 #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12 329 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 330 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 331 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 332 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 333 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 334 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 335 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 336 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 337 #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 338 #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 339 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 340 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 341 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 342 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 343 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 344 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 345 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 346 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 347 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 348 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 349 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 350 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 351 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 352 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 353 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 354 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 355 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 356 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 357 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 358 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 359 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 360 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 361 #define UVD_MASTINT_EN__SYS_EN_MASK 0x4 362 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 363 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 364 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 365 #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 366 #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 367 #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 368 #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 369 #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 370 #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 371 #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 372 #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 373 #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 374 #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 375 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 376 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 377 #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 378 #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 379 #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 380 #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 381 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 382 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 383 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 384 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 385 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 386 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 387 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 388 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 389 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 390 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 391 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 392 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 393 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 394 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 395 #define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 396 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 397 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 398 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 399 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 400 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 401 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 402 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 403 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 404 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 405 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 406 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 407 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 408 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 409 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 410 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 411 #define UVD_LMI_CTRL__RFU_MASK 0xf8000000 412 #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 413 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 414 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 415 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 416 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 417 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 418 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 419 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 420 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 421 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 422 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 423 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 424 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 425 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 426 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 427 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 428 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 429 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 430 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 431 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 432 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 433 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 434 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 435 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 436 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 437 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 438 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 439 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 440 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 441 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 442 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 443 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 444 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 445 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 446 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 447 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 448 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 449 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 450 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 451 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 452 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 453 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 454 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 455 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 456 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 457 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 458 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 459 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 460 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 461 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 462 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 463 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 464 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 465 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 466 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 467 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 468 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 469 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 470 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 471 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 472 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 473 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 474 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 475 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 476 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 477 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 478 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 479 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 480 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 481 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 482 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 483 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 484 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 485 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 486 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 487 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 488 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 489 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 490 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 491 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 492 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 493 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 494 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 495 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 496 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 497 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 498 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 499 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 500 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 501 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 502 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 503 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 504 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 505 #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 506 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 507 #define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00 508 #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 509 #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 510 #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 511 #define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 512 #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 513 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 514 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 515 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 516 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 517 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 518 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 519 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 520 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 521 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 522 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 523 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 524 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 525 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 526 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 527 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 528 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 529 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 530 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 531 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 532 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 533 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 534 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 535 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 536 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 537 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 538 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 539 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 540 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 541 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 542 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 543 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 544 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 545 #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 546 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 547 #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 548 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 549 #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 550 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 551 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 552 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 553 #define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 554 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 555 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 556 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 557 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 558 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 559 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 560 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 561 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 562 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 563 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 564 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 565 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 566 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 567 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 568 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 569 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 570 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 571 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 572 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 573 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 574 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 575 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 576 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 577 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 578 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 579 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 580 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 581 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 582 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 583 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 584 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 585 #define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 586 #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 587 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 588 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 589 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000 590 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 591 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 592 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 593 #define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000 594 #define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 595 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 596 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 597 #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 598 #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 599 #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 600 #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 601 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 602 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 603 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 604 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 605 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 606 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 607 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 608 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 609 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 610 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 611 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 612 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 613 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 614 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 615 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 616 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 617 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 618 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 619 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 620 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 621 #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200 622 #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9 623 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 624 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 625 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 626 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 627 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 628 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 629 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 630 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 631 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 632 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 633 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 634 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 635 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 636 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 637 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000 638 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 639 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000 640 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 641 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000 642 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 643 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000 644 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 645 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000 646 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 647 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000 648 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 649 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000 650 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 651 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000 652 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 653 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000 654 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 655 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000 656 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 657 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000 658 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 659 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000 660 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 661 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000 662 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 663 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000 664 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 665 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000 666 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 667 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf 668 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 669 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 670 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 671 #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf 672 #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 673 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 674 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 675 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 676 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 677 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 678 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 679 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 680 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 681 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 682 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 683 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 684 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 685 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 686 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 687 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 688 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 689 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 690 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 691 #define UVD_STATUS__RBC_BUSY_MASK 0x1 692 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 693 #define UVD_STATUS__VCPU_REPORT_MASK 0xfe 694 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 695 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 696 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 697 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 698 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 699 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 700 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 701 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 702 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 703 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 704 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 705 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 706 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 707 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 708 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 709 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 710 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 711 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 712 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 713 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 714 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 715 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 716 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 717 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 718 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 719 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 720 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 721 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 722 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 723 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 724 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 725 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x2 726 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 727 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 728 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 729 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x8 730 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 731 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x10 732 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 733 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 734 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 735 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 736 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 737 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80 738 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 739 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100 740 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 741 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 742 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 743 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400 744 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 745 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800 746 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 747 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 748 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 749 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x2000 750 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 751 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x4000 752 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 753 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1 754 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 755 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 756 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 757 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4 758 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 759 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 760 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 761 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 762 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 763 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 764 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 765 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 766 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 767 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 768 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 769 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100 770 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 771 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 772 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 773 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400 774 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 775 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 776 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 777 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000 778 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 779 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000 780 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 781 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x4000 782 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 783 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x8000 784 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 785 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 786 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 787 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2 788 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 789 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4 790 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 791 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8 792 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 793 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 794 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 795 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20 796 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 797 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x40 798 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 799 #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf 800 #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0 801 #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0 802 #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4 803 #define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00 804 #define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8 805 #define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000 806 #define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc 807 #define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000 808 #define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10 809 #define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000 810 #define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14 811 #define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000 812 #define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18 813 #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000 814 #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c 815 #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf 816 #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0 817 #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0 818 #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4 819 #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00 820 #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8 821 #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000 822 #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc 823 #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000 824 #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10 825 #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000 826 #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14 827 #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000 828 #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18 829 #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000 830 #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c 831 #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 832 #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 833 #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 834 #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 835 #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 836 #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 837 #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 838 #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 839 #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 840 #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 841 #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 842 #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 843 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 844 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 845 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 846 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 847 #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 848 #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 849 #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 850 #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 851 #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 852 #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 853 #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 854 #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 855 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 856 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 857 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 858 #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 859 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 860 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 861 #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 862 #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 863 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 864 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 865 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 866 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 867 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 868 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 869 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 870 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 871 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 872 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 873 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 874 #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 875 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 876 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 877 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 878 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 879 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 880 #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 881 #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 882 #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 883 #define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000 884 #define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe 885 #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000 886 #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf 887 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 888 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 889 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 890 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 891 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 892 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 893 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 894 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 895 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 896 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 897 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf 898 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0 899 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0 900 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4 901 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00 902 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8 903 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000 904 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc 905 #define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID_MASK 0xf0000 906 #define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID__SHIFT 0x10 907 #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 908 #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 909 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 910 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 911 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 912 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 913 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 914 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 915 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 916 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 917 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 918 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 919 #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 920 #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 921 #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 922 #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 923 #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 924 #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 925 #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 926 #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 927 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 928 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 929 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 930 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 931 #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8 932 #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 933 #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10 934 #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 935 #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20 936 #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 937 #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0 938 #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 939 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 940 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 941 #define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200 942 #define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 943 #define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400 944 #define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa 945 #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff 946 #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0 947 #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff 948 #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0 949 #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff 950 #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0 951 #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff 952 #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0 953 #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff 954 #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0 955 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 956 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 957 #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 958 #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 959 #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 960 #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 961 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 962 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 963 #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 964 #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 965 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 966 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 967 #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 968 #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 969 #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 970 #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 971 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 972 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 973 #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 974 #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 975 #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 976 #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 977 #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 978 #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 979 #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 980 #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 981 #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 982 #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 983 #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 984 #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 985 #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 986 #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 987 #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 988 #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 989 #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 990 #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 991 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 992 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 993 #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 994 #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 995 #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 996 #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 997 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 998 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 999 #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1000 #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1001 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1002 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1003 #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1004 #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1005 #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1006 #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1007 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1008 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1009 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 1010 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1011 #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1012 #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1013 #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1014 #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1015 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1016 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1017 #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1018 #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1019 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1020 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1021 #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1022 #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1023 #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1024 #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1025 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1026 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1027 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7 1028 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1029 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1030 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1031 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1032 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1033 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1034 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1035 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1036 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1037 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1038 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1039 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1040 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1041 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1042 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1043 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1044 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1045 1046 #endif /* UVD_5_0_SH_MASK_H */ 1047