1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * Support for Intel Camera Imaging ISP subsystem.
4   * Copyright (c) 2015, Intel Corporation.
5   *
6   * This program is free software; you can redistribute it and/or modify it
7   * under the terms and conditions of the GNU General Public License,
8   * version 2, as published by the Free Software Foundation.
9   *
10   * This program is distributed in the hope it will be useful, but WITHOUT
11   * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   * more details.
14   */
15  
16  #ifndef __TIMED_CTRL_GLOBAL_H_INCLUDED__
17  #define __TIMED_CTRL_GLOBAL_H_INCLUDED__
18  
19  #define IS_TIMED_CTRL_VERSION_1
20  
21  #include "timed_controller_defs.h"
22  
23  /**
24   * Order of the input bits for the timed controller taken from
25   * ISP_CSS_2401 System Architecture Description valid for
26   * 2400, 2401.
27   *
28   * Check for other systems.
29   */
30  #define HIVE_TIMED_CTRL_GPIO_PIN_0_BIT_ID                       0
31  #define HIVE_TIMED_CTRL_GPIO_PIN_1_BIT_ID                       1
32  #define HIVE_TIMED_CTRL_GPIO_PIN_2_BIT_ID                       2
33  #define HIVE_TIMED_CTRL_GPIO_PIN_3_BIT_ID                       3
34  #define HIVE_TIMED_CTRL_GPIO_PIN_4_BIT_ID                       4
35  #define HIVE_TIMED_CTRL_GPIO_PIN_5_BIT_ID                       5
36  #define HIVE_TIMED_CTRL_GPIO_PIN_6_BIT_ID                       6
37  #define HIVE_TIMED_CTRL_GPIO_PIN_7_BIT_ID                       7
38  #define HIVE_TIMED_CTRL_GPIO_PIN_8_BIT_ID                       8
39  #define HIVE_TIMED_CTRL_GPIO_PIN_9_BIT_ID                       9
40  #define HIVE_TIMED_CTRL_GPIO_PIN_10_BIT_ID                      10
41  #define HIVE_TIMED_CTRL_GPIO_PIN_11_BIT_ID                      11
42  #define HIVE_TIMED_CTRL_IRQ_SP_BIT_ID                           12
43  #define HIVE_TIMED_CTRL_IRQ_ISP_BIT_ID                          13
44  #define HIVE_TIMED_CTRL_IRQ_INPUT_SYSTEM_BIT_ID                 14
45  #define HIVE_TIMED_CTRL_IRQ_INPUT_SELECTOR_BIT_ID               15
46  #define HIVE_TIMED_CTRL_IRQ_IF_BLOCK_BIT_ID                     16
47  #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_0_BIT_ID                   17
48  #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_1_BIT_ID                   18
49  #define HIVE_TIMED_CTRL_CSI_SOL_BIT_ID                          19
50  #define HIVE_TIMED_CTRL_CSI_EOL_BIT_ID                          20
51  #define HIVE_TIMED_CTRL_CSI_SOF_BIT_ID                          21
52  #define HIVE_TIMED_CTRL_CSI_EOF_BIT_ID                          22
53  #define HIVE_TIMED_CTRL_IRQ_IS_STREAMING_MONITOR_BIT_ID         23
54  
55  #endif /* __TIMED_CTRL_GLOBAL_H_INCLUDED__ */
56