1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 STMicroelectronics Limited.
4 * Author: Peter Griffin <peter.griffin@linaro.org>
5 */
6#include "stih418-clock.dtsi"
7#include "stih407-family.dtsi"
8#include "stih410-pinctrl.dtsi"
9#include <dt-bindings/thermal/thermal.h>
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14		cpu2: cpu@2 {
15			device_type = "cpu";
16			compatible = "arm,cortex-a9";
17			reg = <2>;
18			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
19			cpu-release-addr = <0x94100A4>;
20			#cooling-cells = <2>;
21		};
22		cpu3: cpu@3 {
23			device_type = "cpu";
24			compatible = "arm,cortex-a9";
25			reg = <3>;
26			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
27			cpu-release-addr = <0x94100A4>;
28			#cooling-cells = <2>;
29		};
30	};
31
32	usb2_picophy1: phy2 {
33		compatible = "st,stih407-usb2-phy";
34		#phy-cells = <0>;
35		st,syscfg = <&syscfg_core 0xf8 0xf4>;
36		resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
37			 <&picophyreset STIH407_PICOPHY0_RESET>;
38		reset-names = "global", "port";
39	};
40
41	usb2_picophy2: phy3 {
42		compatible = "st,stih407-usb2-phy";
43		#phy-cells = <0>;
44		st,syscfg = <&syscfg_core 0xfc 0xf4>;
45		resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
46			 <&picophyreset STIH407_PICOPHY1_RESET>;
47		reset-names = "global", "port";
48	};
49
50	thermal-zones {
51		cpu_thermal: cpu-thermal {
52			polling-delay-passive = <250>;  /* 250ms */
53			polling-delay = <1000>;         /* 1000ms */
54
55			thermal-sensors = <&thermal>;
56
57			trips {
58				cpu_crit: cpu-crit {
59					temperature = <95000>;  /* 95C */
60					hysteresis = <2000>;
61					type = "critical";
62				};
63				cpu_alert: cpu-alert {
64					temperature = <85000>;  /* 85C */
65					hysteresis = <2000>;
66					type = "passive";
67				};
68			};
69
70			cooling-maps {
71				map {
72					trip = <&cpu_alert>;
73					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
74							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
75							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
76							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
77				};
78			};
79		};
80	};
81
82	soc {
83		rng11: rng@8a8a000 {
84			status = "disabled";
85		};
86
87		ohci0: usb@9a03c00 {
88			compatible = "st,st-ohci-300x";
89			reg = <0x9a03c00 0x100>;
90			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
91			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
92			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
93				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
94			reset-names = "power", "softreset";
95			phys = <&usb2_picophy1>;
96			phy-names = "usb";
97		};
98
99		ehci0: usb@9a03e00 {
100			compatible = "st,st-ehci-300x";
101			reg = <0x9a03e00 0x100>;
102			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
103			pinctrl-names = "default";
104			pinctrl-0 = <&pinctrl_usb0>;
105			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
106			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
107				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
108			reset-names = "power", "softreset";
109			phys = <&usb2_picophy1>;
110			phy-names = "usb";
111		};
112
113		ohci1: usb@9a83c00 {
114			compatible = "st,st-ohci-300x";
115			reg = <0x9a83c00 0x100>;
116			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
117			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
118			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
119				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
120			reset-names = "power", "softreset";
121			phys = <&usb2_picophy2>;
122			phy-names = "usb";
123		};
124
125		ehci1: usb@9a83e00 {
126			compatible = "st,st-ehci-300x";
127			reg = <0x9a83e00 0x100>;
128			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
129			pinctrl-names = "default";
130			pinctrl-0 = <&pinctrl_usb1>;
131			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
132			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
133				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
134			reset-names = "power", "softreset";
135			phys = <&usb2_picophy2>;
136			phy-names = "usb";
137		};
138
139		mmc0: sdhci@9060000 {
140			assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
141			assigned-clock-parents = <&clk_s_c0_pll1 0>;
142			assigned-clock-rates = <200000000>;
143		};
144
145		thermal: thermal@91a0000 {
146			compatible = "st,stih407-thermal";
147			reg = <0x91a0000 0x28>;
148			clock-names = "thermal";
149			clocks = <&clk_sysin>;
150			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
151			#thermal-sensor-cells = <0>;
152		};
153	};
154};
155