1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3 
4 #include <linux/cleanup.h>
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/clk.h>
11 #include <sound/soc.h>
12 #include <sound/pcm.h>
13 #include <sound/pcm_params.h>
14 #include <sound/soc-dapm.h>
15 #include <sound/tlv.h>
16 #include <linux/of_clk.h>
17 #include <linux/clk-provider.h>
18 
19 #include "lpass-macro-common.h"
20 
21 #define CDC_RX_TOP_TOP_CFG0		(0x0000)
22 #define CDC_RX_TOP_SWR_CTRL		(0x0008)
23 #define CDC_RX_TOP_DEBUG		(0x000C)
24 #define CDC_RX_TOP_DEBUG_BUS		(0x0010)
25 #define CDC_RX_TOP_DEBUG_EN0		(0x0014)
26 #define CDC_RX_TOP_DEBUG_EN1		(0x0018)
27 #define CDC_RX_TOP_DEBUG_EN2		(0x001C)
28 #define CDC_RX_TOP_HPHL_COMP_WR_LSB	(0x0020)
29 #define CDC_RX_TOP_HPHL_COMP_WR_MSB	(0x0024)
30 #define CDC_RX_TOP_HPHL_COMP_LUT	(0x0028)
31 #define CDC_RX_TOP_HPH_LUT_BYPASS_MASK	BIT(7)
32 #define CDC_RX_TOP_HPHL_COMP_RD_LSB	(0x002C)
33 #define CDC_RX_TOP_HPHL_COMP_RD_MSB	(0x0030)
34 #define CDC_RX_TOP_HPHR_COMP_WR_LSB	(0x0034)
35 #define CDC_RX_TOP_HPHR_COMP_WR_MSB	(0x0038)
36 #define CDC_RX_TOP_HPHR_COMP_LUT	(0x003C)
37 #define CDC_RX_TOP_HPHR_COMP_RD_LSB	(0x0040)
38 #define CDC_RX_TOP_HPHR_COMP_RD_MSB	(0x0044)
39 #define CDC_RX_TOP_DSD0_DEBUG_CFG0	(0x0070)
40 #define CDC_RX_TOP_DSD0_DEBUG_CFG1	(0x0074)
41 #define CDC_RX_TOP_DSD0_DEBUG_CFG2	(0x0078)
42 #define CDC_RX_TOP_DSD0_DEBUG_CFG3	(0x007C)
43 #define CDC_RX_TOP_DSD1_DEBUG_CFG0	(0x0080)
44 #define CDC_RX_TOP_DSD1_DEBUG_CFG1	(0x0084)
45 #define CDC_RX_TOP_DSD1_DEBUG_CFG2	(0x0088)
46 #define CDC_RX_TOP_DSD1_DEBUG_CFG3	(0x008C)
47 #define CDC_RX_TOP_RX_I2S_CTL		(0x0090)
48 #define CDC_RX_TOP_TX_I2S2_CTL		(0x0094)
49 #define CDC_RX_TOP_I2S_CLK		(0x0098)
50 #define CDC_RX_TOP_I2S_RESET		(0x009C)
51 #define CDC_RX_TOP_I2S_MUX		(0x00A0)
52 #define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL	(0x0100)
53 #define CDC_RX_CLK_MCLK_EN_MASK		BIT(0)
54 #define CDC_RX_CLK_MCLK_ENABLE		BIT(0)
55 #define CDC_RX_CLK_MCLK2_EN_MASK	BIT(1)
56 #define CDC_RX_CLK_MCLK2_ENABLE		BIT(1)
57 #define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL	(0x0104)
58 #define CDC_RX_FS_MCLK_CNT_EN_MASK	BIT(0)
59 #define CDC_RX_FS_MCLK_CNT_ENABLE	BIT(0)
60 #define CDC_RX_FS_MCLK_CNT_CLR_MASK	BIT(1)
61 #define CDC_RX_FS_MCLK_CNT_CLR		BIT(1)
62 #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL	(0x0108)
63 #define CDC_RX_SWR_CLK_EN_MASK		BIT(0)
64 #define CDC_RX_SWR_RESET_MASK		BIT(1)
65 #define CDC_RX_SWR_RESET		BIT(1)
66 #define CDC_RX_CLK_RST_CTRL_DSD_CONTROL	(0x010C)
67 #define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL	(0x0110)
68 #define CDC_RX_SOFTCLIP_CRC		(0x0140)
69 #define CDC_RX_SOFTCLIP_CLK_EN_MASK	BIT(0)
70 #define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL	(0x0144)
71 #define CDC_RX_SOFTCLIP_EN_MASK		BIT(0)
72 #define CDC_RX_INP_MUX_RX_INT0_CFG0	(0x0180)
73 #define CDC_RX_INTX_1_MIX_INP0_SEL_MASK	GENMASK(3, 0)
74 #define CDC_RX_INTX_1_MIX_INP1_SEL_MASK	GENMASK(7, 4)
75 #define CDC_RX_INP_MUX_RX_INT0_CFG1	(0x0184)
76 #define CDC_RX_INTX_2_SEL_MASK		GENMASK(3, 0)
77 #define CDC_RX_INTX_1_MIX_INP2_SEL_MASK	GENMASK(7, 4)
78 #define CDC_RX_INP_MUX_RX_INT1_CFG0	(0x0188)
79 #define CDC_RX_INP_MUX_RX_INT1_CFG1	(0x018C)
80 #define CDC_RX_INP_MUX_RX_INT2_CFG0	(0x0190)
81 #define CDC_RX_INP_MUX_RX_INT2_CFG1	(0x0194)
82 #define CDC_RX_INP_MUX_RX_MIX_CFG4	(0x0198)
83 #define CDC_RX_INP_MUX_RX_MIX_CFG5	(0x019C)
84 #define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0	(0x01A0)
85 #define CDC_RX_CLSH_CRC			(0x0200)
86 #define CDC_RX_CLSH_CLK_EN_MASK		BIT(0)
87 #define CDC_RX_CLSH_DLY_CTRL		(0x0204)
88 #define CDC_RX_CLSH_DECAY_CTRL		(0x0208)
89 #define CDC_RX_CLSH_DECAY_RATE_MASK	GENMASK(2, 0)
90 #define CDC_RX_CLSH_HPH_V_PA		(0x020C)
91 #define CDC_RX_CLSH_HPH_V_PA_MIN_MASK	GENMASK(5, 0)
92 #define CDC_RX_CLSH_EAR_V_PA		(0x0210)
93 #define CDC_RX_CLSH_HPH_V_HD		(0x0214)
94 #define CDC_RX_CLSH_EAR_V_HD		(0x0218)
95 #define CDC_RX_CLSH_K1_MSB		(0x021C)
96 #define CDC_RX_CLSH_K1_MSB_COEFF_MASK	GENMASK(3, 0)
97 #define CDC_RX_CLSH_K1_LSB		(0x0220)
98 #define CDC_RX_CLSH_K2_MSB		(0x0224)
99 #define CDC_RX_CLSH_K2_LSB		(0x0228)
100 #define CDC_RX_CLSH_IDLE_CTRL		(0x022C)
101 #define CDC_RX_CLSH_IDLE_HPH		(0x0230)
102 #define CDC_RX_CLSH_IDLE_EAR		(0x0234)
103 #define CDC_RX_CLSH_TEST0		(0x0238)
104 #define CDC_RX_CLSH_TEST1		(0x023C)
105 #define CDC_RX_CLSH_OVR_VREF		(0x0240)
106 #define CDC_RX_CLSH_CLSG_CTL		(0x0244)
107 #define CDC_RX_CLSH_CLSG_CFG1		(0x0248)
108 #define CDC_RX_CLSH_CLSG_CFG2		(0x024C)
109 #define CDC_RX_BCL_VBAT_PATH_CTL	(0x0280)
110 #define CDC_RX_BCL_VBAT_CFG		(0x0284)
111 #define CDC_RX_BCL_VBAT_ADC_CAL1	(0x0288)
112 #define CDC_RX_BCL_VBAT_ADC_CAL2	(0x028C)
113 #define CDC_RX_BCL_VBAT_ADC_CAL3	(0x0290)
114 #define CDC_RX_BCL_VBAT_PK_EST1		(0x0294)
115 #define CDC_RX_BCL_VBAT_PK_EST2		(0x0298)
116 #define CDC_RX_BCL_VBAT_PK_EST3		(0x029C)
117 #define CDC_RX_BCL_VBAT_RF_PROC1	(0x02A0)
118 #define CDC_RX_BCL_VBAT_RF_PROC2	(0x02A4)
119 #define CDC_RX_BCL_VBAT_TAC1		(0x02A8)
120 #define CDC_RX_BCL_VBAT_TAC2		(0x02AC)
121 #define CDC_RX_BCL_VBAT_TAC3		(0x02B0)
122 #define CDC_RX_BCL_VBAT_TAC4		(0x02B4)
123 #define CDC_RX_BCL_VBAT_GAIN_UPD1	(0x02B8)
124 #define CDC_RX_BCL_VBAT_GAIN_UPD2	(0x02BC)
125 #define CDC_RX_BCL_VBAT_GAIN_UPD3	(0x02C0)
126 #define CDC_RX_BCL_VBAT_GAIN_UPD4	(0x02C4)
127 #define CDC_RX_BCL_VBAT_GAIN_UPD5	(0x02C8)
128 #define CDC_RX_BCL_VBAT_DEBUG1		(0x02CC)
129 #define CDC_RX_BCL_VBAT_GAIN_UPD_MON	(0x02D0)
130 #define CDC_RX_BCL_VBAT_GAIN_MON_VAL	(0x02D4)
131 #define CDC_RX_BCL_VBAT_BAN		(0x02D8)
132 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1	(0x02DC)
133 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2	(0x02E0)
134 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3	(0x02E4)
135 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4	(0x02E8)
136 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5	(0x02EC)
137 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6	(0x02F0)
138 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7	(0x02F4)
139 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8	(0x02F8)
140 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9	(0x02FC)
141 #define CDC_RX_BCL_VBAT_ATTN1		(0x0300)
142 #define CDC_RX_BCL_VBAT_ATTN2		(0x0304)
143 #define CDC_RX_BCL_VBAT_ATTN3		(0x0308)
144 #define CDC_RX_BCL_VBAT_DECODE_CTL1	(0x030C)
145 #define CDC_RX_BCL_VBAT_DECODE_CTL2	(0x0310)
146 #define CDC_RX_BCL_VBAT_DECODE_CFG1	(0x0314)
147 #define CDC_RX_BCL_VBAT_DECODE_CFG2	(0x0318)
148 #define CDC_RX_BCL_VBAT_DECODE_CFG3	(0x031C)
149 #define CDC_RX_BCL_VBAT_DECODE_CFG4	(0x0320)
150 #define CDC_RX_BCL_VBAT_DECODE_ST	(0x0324)
151 #define CDC_RX_INTR_CTRL_CFG		(0x0340)
152 #define CDC_RX_INTR_CTRL_CLR_COMMIT	(0x0344)
153 #define CDC_RX_INTR_CTRL_PIN1_MASK0	(0x0360)
154 #define CDC_RX_INTR_CTRL_PIN1_STATUS0	(0x0368)
155 #define CDC_RX_INTR_CTRL_PIN1_CLEAR0	(0x0370)
156 #define CDC_RX_INTR_CTRL_PIN2_MASK0	(0x0380)
157 #define CDC_RX_INTR_CTRL_PIN2_STATUS0	(0x0388)
158 #define CDC_RX_INTR_CTRL_PIN2_CLEAR0	(0x0390)
159 #define CDC_RX_INTR_CTRL_LEVEL0		(0x03C0)
160 #define CDC_RX_INTR_CTRL_BYPASS0	(0x03C8)
161 #define CDC_RX_INTR_CTRL_SET0		(0x03D0)
162 #define CDC_RX_RXn_RX_PATH_CTL(rx, n)	(0x0400  + rx->rxn_reg_stride * n)
163 #define CDC_RX_RX0_RX_PATH_CTL		(0x0400)
164 #define CDC_RX_PATH_RESET_EN_MASK	BIT(6)
165 #define CDC_RX_PATH_CLK_EN_MASK		BIT(5)
166 #define CDC_RX_PATH_CLK_ENABLE		BIT(5)
167 #define CDC_RX_PATH_PGA_MUTE_MASK	BIT(4)
168 #define CDC_RX_PATH_PGA_MUTE_ENABLE	BIT(4)
169 #define CDC_RX_PATH_PCM_RATE_MASK	GENMASK(3, 0)
170 #define CDC_RX_RXn_RX_PATH_CFG0(rx, n)	(0x0404  + rx->rxn_reg_stride * n)
171 #define CDC_RX_RXn_COMP_EN_MASK		BIT(1)
172 #define CDC_RX_RX0_RX_PATH_CFG0		(0x0404)
173 #define CDC_RX_RXn_CLSH_EN_MASK		BIT(6)
174 #define CDC_RX_DLY_ZN_EN_MASK		BIT(3)
175 #define CDC_RX_DLY_ZN_ENABLE		BIT(3)
176 #define CDC_RX_RXn_HD2_EN_MASK		BIT(2)
177 #define CDC_RX_RXn_RX_PATH_CFG1(rx, n)	(0x0408  + rx->rxn_reg_stride * n)
178 #define CDC_RX_RXn_SIDETONE_EN_MASK	BIT(4)
179 #define CDC_RX_RX0_RX_PATH_CFG1		(0x0408)
180 #define CDC_RX_RX0_HPH_L_EAR_SEL_MASK	BIT(1)
181 #define CDC_RX_RXn_RX_PATH_CFG2(rx, n)	(0x040C  + rx->rxn_reg_stride * n)
182 #define CDC_RX_RXn_HPF_CUT_FREQ_MASK	GENMASK(1, 0)
183 #define CDC_RX_RX0_RX_PATH_CFG2		(0x040C)
184 #define CDC_RX_RXn_RX_PATH_CFG3(rx, n)	(0x0410  + rx->rxn_reg_stride * n)
185 #define CDC_RX_RX0_RX_PATH_CFG3		(0x0410)
186 #define CDC_RX_DC_COEFF_SEL_MASK	GENMASK(1, 0)
187 #define CDC_RX_DC_COEFF_SEL_TWO		0x2
188 #define CDC_RX_RXn_RX_VOL_CTL(rx, n)	(0x0414  + rx->rxn_reg_stride * n)
189 #define CDC_RX_RX0_RX_VOL_CTL		(0x0414)
190 #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n)	(0x0418  + rx->rxn_reg_stride * n)
191 #define CDC_RX_RXn_MIX_PCM_RATE_MASK	GENMASK(3, 0)
192 #define CDC_RX_RXn_MIX_RESET_MASK	BIT(6)
193 #define CDC_RX_RXn_MIX_RESET		BIT(6)
194 #define CDC_RX_RXn_MIX_CLK_EN_MASK	BIT(5)
195 #define CDC_RX_RX0_RX_PATH_MIX_CTL	(0x0418)
196 #define CDC_RX_RX0_RX_PATH_MIX_CFG	(0x041C)
197 #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n)	(0x0420  + rx->rxn_reg_stride * n)
198 #define CDC_RX_RX0_RX_VOL_MIX_CTL	(0x0420)
199 #define CDC_RX_RX0_RX_PATH_SEC1		(0x0424)
200 #define CDC_RX_RX0_RX_PATH_SEC2		(0x0428)
201 #define CDC_RX_RX0_RX_PATH_SEC3		(0x042C)
202 #define CDC_RX_RXn_RX_PATH_SEC3(rx, n)	(0x042c  + rx->rxn_reg_stride * n)
203 #define CDC_RX_RX0_RX_PATH_SEC4		(0x0430)
204 #define CDC_RX_RX0_RX_PATH_SEC7		(0x0434)
205 #define CDC_RX_RXn_RX_PATH_SEC7(rx, n)		\
206 	(0x0434 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
207 #define CDC_RX_DSM_OUT_DELAY_SEL_MASK	GENMASK(2, 0)
208 #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE	0x2
209 #define CDC_RX_RX0_RX_PATH_MIX_SEC0	(0x0438)
210 #define CDC_RX_RX0_RX_PATH_MIX_SEC1	(0x043C)
211 #define CDC_RX_RXn_RX_PATH_DSM_CTL(rx, n)	\
212 	(0x0440 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
213 #define CDC_RX_RXn_DSM_CLK_EN_MASK	BIT(0)
214 #define CDC_RX_RX0_RX_PATH_DSM_CTL	(0x0440)
215 #define CDC_RX_RX0_RX_PATH_DSM_DATA1	(0x0444)
216 #define CDC_RX_RX0_RX_PATH_DSM_DATA2	(0x0448)
217 #define CDC_RX_RX0_RX_PATH_DSM_DATA3	(0x044C)
218 #define CDC_RX_RX0_RX_PATH_DSM_DATA4	(0x0450)
219 #define CDC_RX_RX0_RX_PATH_DSM_DATA5	(0x0454)
220 #define CDC_RX_RX0_RX_PATH_DSM_DATA6	(0x0458)
221 /* RX offsets prior to 2.5 codec version */
222 #define CDC_RX_RX1_RX_PATH_CTL		(0x0480)
223 #define CDC_RX_RX1_RX_PATH_CFG0		(0x0484)
224 #define CDC_RX_RX1_RX_PATH_CFG1		(0x0488)
225 #define CDC_RX_RX1_RX_PATH_CFG2		(0x048C)
226 #define CDC_RX_RX1_RX_PATH_CFG3		(0x0490)
227 #define CDC_RX_RX1_RX_VOL_CTL		(0x0494)
228 #define CDC_RX_RX1_RX_PATH_MIX_CTL	(0x0498)
229 #define CDC_RX_RX1_RX_PATH_MIX_CFG	(0x049C)
230 #define CDC_RX_RX1_RX_VOL_MIX_CTL	(0x04A0)
231 #define CDC_RX_RX1_RX_PATH_SEC1		(0x04A4)
232 #define CDC_RX_RX1_RX_PATH_SEC2		(0x04A8)
233 #define CDC_RX_RX1_RX_PATH_SEC3		(0x04AC)
234 #define CDC_RX_RXn_HD2_ALPHA_MASK	GENMASK(5, 2)
235 #define CDC_RX_RX1_RX_PATH_SEC4		(0x04B0)
236 #define CDC_RX_RX1_RX_PATH_SEC7		(0x04B4)
237 #define CDC_RX_RX1_RX_PATH_MIX_SEC0	(0x04B8)
238 #define CDC_RX_RX1_RX_PATH_MIX_SEC1	(0x04BC)
239 #define CDC_RX_RX1_RX_PATH_DSM_CTL	(0x04C0)
240 #define CDC_RX_RX1_RX_PATH_DSM_DATA1	(0x04C4)
241 #define CDC_RX_RX1_RX_PATH_DSM_DATA2	(0x04C8)
242 #define CDC_RX_RX1_RX_PATH_DSM_DATA3	(0x04CC)
243 #define CDC_RX_RX1_RX_PATH_DSM_DATA4	(0x04D0)
244 #define CDC_RX_RX1_RX_PATH_DSM_DATA5	(0x04D4)
245 #define CDC_RX_RX1_RX_PATH_DSM_DATA6	(0x04D8)
246 #define CDC_RX_RX2_RX_PATH_CTL		(0x0500)
247 #define CDC_RX_RX2_RX_PATH_CFG0		(0x0504)
248 #define CDC_RX_RX2_CLSH_EN_MASK		BIT(4)
249 #define CDC_RX_RX2_DLY_Z_EN_MASK	BIT(3)
250 #define CDC_RX_RX2_RX_PATH_CFG1		(0x0508)
251 #define CDC_RX_RX2_RX_PATH_CFG2		(0x050C)
252 #define CDC_RX_RX2_RX_PATH_CFG3		(0x0510)
253 #define CDC_RX_RX2_RX_VOL_CTL		(0x0514)
254 #define CDC_RX_RX2_RX_PATH_MIX_CTL	(0x0518)
255 #define CDC_RX_RX2_RX_PATH_MIX_CFG	(0x051C)
256 #define CDC_RX_RX2_RX_VOL_MIX_CTL	(0x0520)
257 #define CDC_RX_RX2_RX_PATH_SEC0		(0x0524)
258 #define CDC_RX_RX2_RX_PATH_SEC1		(0x0528)
259 #define CDC_RX_RX2_RX_PATH_SEC2		(0x052C)
260 #define CDC_RX_RX2_RX_PATH_SEC3		(0x0530)
261 #define CDC_RX_RX2_RX_PATH_SEC4		(0x0534)
262 #define CDC_RX_RX2_RX_PATH_SEC5		(0x0538)
263 #define CDC_RX_RX2_RX_PATH_SEC6		(0x053C)
264 #define CDC_RX_RX2_RX_PATH_SEC7		(0x0540)
265 #define CDC_RX_RX2_RX_PATH_MIX_SEC0	(0x0544)
266 #define CDC_RX_RX2_RX_PATH_MIX_SEC1	(0x0548)
267 #define CDC_RX_RX2_RX_PATH_DSM_CTL	(0x054C)
268 
269 /* LPASS CODEC version 2.5 rx reg offsets */
270 #define CDC_2_5_RX_RX1_RX_PATH_CTL		(0x04c0)
271 #define CDC_2_5_RX_RX1_RX_PATH_CFG0		(0x04c4)
272 #define CDC_2_5_RX_RX1_RX_PATH_CFG1		(0x04c8)
273 #define CDC_2_5_RX_RX1_RX_PATH_CFG2		(0x04cC)
274 #define CDC_2_5_RX_RX1_RX_PATH_CFG3		(0x04d0)
275 #define CDC_2_5_RX_RX1_RX_VOL_CTL		(0x04d4)
276 #define CDC_2_5_RX_RX1_RX_PATH_MIX_CTL		(0x04d8)
277 #define CDC_2_5_RX_RX1_RX_PATH_MIX_CFG		(0x04dC)
278 #define CDC_2_5_RX_RX1_RX_VOL_MIX_CTL		(0x04e0)
279 #define CDC_2_5_RX_RX1_RX_PATH_SEC1		(0x04e4)
280 #define CDC_2_5_RX_RX1_RX_PATH_SEC2		(0x04e8)
281 #define CDC_2_5_RX_RX1_RX_PATH_SEC3		(0x04eC)
282 #define CDC_2_5_RX_RX1_RX_PATH_SEC4		(0x04f0)
283 #define CDC_2_5_RX_RX1_RX_PATH_SEC7		(0x04f4)
284 #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0		(0x04f8)
285 #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1		(0x04fC)
286 #define CDC_2_5_RX_RX1_RX_PATH_DSM_CTL		(0x0500)
287 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1	(0x0504)
288 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2	(0x0508)
289 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3	(0x050C)
290 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4	(0x0510)
291 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5	(0x0514)
292 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6	(0x0518)
293 
294 #define CDC_2_5_RX_RX2_RX_PATH_CTL		(0x0580)
295 #define CDC_2_5_RX_RX2_RX_PATH_CFG0		(0x0584)
296 #define CDC_2_5_RX_RX2_RX_PATH_CFG1		(0x0588)
297 #define CDC_2_5_RX_RX2_RX_PATH_CFG2		(0x058C)
298 #define CDC_2_5_RX_RX2_RX_PATH_CFG3		(0x0590)
299 #define CDC_2_5_RX_RX2_RX_VOL_CTL		(0x0594)
300 #define CDC_2_5_RX_RX2_RX_PATH_MIX_CTL		(0x0598)
301 #define CDC_2_5_RX_RX2_RX_PATH_MIX_CFG		(0x059C)
302 #define CDC_2_5_RX_RX2_RX_VOL_MIX_CTL		(0x05a0)
303 #define CDC_2_5_RX_RX2_RX_PATH_SEC0		(0x05a4)
304 #define CDC_2_5_RX_RX2_RX_PATH_SEC1		(0x05a8)
305 #define CDC_2_5_RX_RX2_RX_PATH_SEC2		(0x05aC)
306 #define CDC_2_5_RX_RX2_RX_PATH_SEC3		(0x05b0)
307 #define CDC_2_5_RX_RX2_RX_PATH_SEC4		(0x05b4)
308 #define CDC_2_5_RX_RX2_RX_PATH_SEC5		(0x05b8)
309 #define CDC_2_5_RX_RX2_RX_PATH_SEC6		(0x05bC)
310 #define CDC_2_5_RX_RX2_RX_PATH_SEC7		(0x05c0)
311 #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0		(0x05c4)
312 #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1		(0x05c8)
313 #define CDC_2_5_RX_RX2_RX_PATH_DSM_CTL		(0x05cC)
314 
315 #define CDC_RX_IDLE_DETECT_PATH_CTL	(0x0780)
316 #define CDC_RX_IDLE_DETECT_CFG0		(0x0784)
317 #define CDC_RX_IDLE_DETECT_CFG1		(0x0788)
318 #define CDC_RX_IDLE_DETECT_CFG2		(0x078C)
319 #define CDC_RX_IDLE_DETECT_CFG3		(0x0790)
320 #define CDC_RX_COMPANDERn_CTL0(n)	(0x0800 + 0x40 * n)
321 #define CDC_RX_COMPANDERn_CLK_EN_MASK	BIT(0)
322 #define CDC_RX_COMPANDERn_SOFT_RST_MASK	BIT(1)
323 #define CDC_RX_COMPANDERn_HALT_MASK	BIT(2)
324 #define CDC_RX_COMPANDER0_CTL0		(0x0800)
325 #define CDC_RX_COMPANDER0_CTL1		(0x0804)
326 #define CDC_RX_COMPANDER0_CTL2		(0x0808)
327 #define CDC_RX_COMPANDER0_CTL3		(0x080C)
328 #define CDC_RX_COMPANDER0_CTL4		(0x0810)
329 #define CDC_RX_COMPANDER0_CTL5		(0x0814)
330 #define CDC_RX_COMPANDER0_CTL6		(0x0818)
331 #define CDC_RX_COMPANDER0_CTL7		(0x081C)
332 #define CDC_RX_COMPANDER1_CTL0		(0x0840)
333 #define CDC_RX_COMPANDER1_CTL1		(0x0844)
334 #define CDC_RX_COMPANDER1_CTL2		(0x0848)
335 #define CDC_RX_COMPANDER1_CTL3		(0x084C)
336 #define CDC_RX_COMPANDER1_CTL4		(0x0850)
337 #define CDC_RX_COMPANDER1_CTL5		(0x0854)
338 #define CDC_RX_COMPANDER1_CTL6		(0x0858)
339 #define CDC_RX_COMPANDER1_CTL7		(0x085C)
340 #define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK	BIT(5)
341 #define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL	(0x0A00)
342 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL	(0x0A04)
343 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL	(0x0A08)
344 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL	(0x0A0C)
345 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL	(0x0A10)
346 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL	(0x0A14)
347 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL	(0x0A18)
348 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL	(0x0A1C)
349 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL	(0x0A20)
350 #define CDC_RX_SIDETONE_IIR0_IIR_CTL		(0x0A24)
351 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL	(0x0A28)
352 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL	(0x0A2C)
353 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL	(0x0A30)
354 #define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL	(0x0A80)
355 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL	(0x0A84)
356 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL	(0x0A88)
357 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL	(0x0A8C)
358 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL	(0x0A90)
359 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL	(0x0A94)
360 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL	(0x0A98)
361 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL	(0x0A9C)
362 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL	(0x0AA0)
363 #define CDC_RX_SIDETONE_IIR1_IIR_CTL		(0x0AA4)
364 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL	(0x0AA8)
365 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL	(0x0AAC)
366 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL	(0x0AB0)
367 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0	(0x0B00)
368 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1	(0x0B04)
369 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2	(0x0B08)
370 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3	(0x0B0C)
371 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0	(0x0B10)
372 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1	(0x0B14)
373 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2	(0x0B18)
374 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3	(0x0B1C)
375 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL	(0x0B40)
376 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1	(0x0B44)
377 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL	(0x0B50)
378 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1	(0x0B54)
379 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL	(0x0C00)
380 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0	(0x0C04)
381 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL	(0x0C40)
382 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0	(0x0C44)
383 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL	(0x0C80)
384 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0	(0x0C84)
385 #define CDC_RX_EC_ASRC0_CLK_RST_CTL		(0x0D00)
386 #define CDC_RX_EC_ASRC0_CTL0			(0x0D04)
387 #define CDC_RX_EC_ASRC0_CTL1			(0x0D08)
388 #define CDC_RX_EC_ASRC0_FIFO_CTL		(0x0D0C)
389 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB	(0x0D10)
390 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB	(0x0D14)
391 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB	(0x0D18)
392 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB	(0x0D1C)
393 #define CDC_RX_EC_ASRC0_STATUS_FIFO		(0x0D20)
394 #define CDC_RX_EC_ASRC1_CLK_RST_CTL		(0x0D40)
395 #define CDC_RX_EC_ASRC1_CTL0			(0x0D44)
396 #define CDC_RX_EC_ASRC1_CTL1			(0x0D48)
397 #define CDC_RX_EC_ASRC1_FIFO_CTL		(0x0D4C)
398 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB	(0x0D50)
399 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB	(0x0D54)
400 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB	(0x0D58)
401 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB	(0x0D5C)
402 #define CDC_RX_EC_ASRC1_STATUS_FIFO		(0x0D60)
403 #define CDC_RX_EC_ASRC2_CLK_RST_CTL		(0x0D80)
404 #define CDC_RX_EC_ASRC2_CTL0			(0x0D84)
405 #define CDC_RX_EC_ASRC2_CTL1			(0x0D88)
406 #define CDC_RX_EC_ASRC2_FIFO_CTL		(0x0D8C)
407 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB	(0x0D90)
408 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB	(0x0D94)
409 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB	(0x0D98)
410 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB	(0x0D9C)
411 #define CDC_RX_EC_ASRC2_STATUS_FIFO		(0x0DA0)
412 #define CDC_RX_DSD0_PATH_CTL			(0x0F00)
413 #define CDC_RX_DSD0_CFG0			(0x0F04)
414 #define CDC_RX_DSD0_CFG1			(0x0F08)
415 #define CDC_RX_DSD0_CFG2			(0x0F0C)
416 #define CDC_RX_DSD1_PATH_CTL			(0x0F80)
417 #define CDC_RX_DSD1_CFG0			(0x0F84)
418 #define CDC_RX_DSD1_CFG1			(0x0F88)
419 #define CDC_RX_DSD1_CFG2			(0x0F8C)
420 #define RX_MAX_OFFSET				(0x0F8C)
421 
422 #define MCLK_FREQ		19200000
423 
424 #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
425 			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
426 			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
427 			SNDRV_PCM_RATE_384000)
428 /* Fractional Rates */
429 #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
430 				SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
431 
432 #define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
433 		SNDRV_PCM_FMTBIT_S24_LE |\
434 		SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
435 
436 #define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
437 			SNDRV_PCM_RATE_48000)
438 #define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
439 		SNDRV_PCM_FMTBIT_S24_LE |\
440 		SNDRV_PCM_FMTBIT_S24_3LE)
441 
442 #define RX_MACRO_MAX_DMA_CH_PER_PORT 2
443 
444 #define RX_MACRO_EC_MIX_TX0_MASK 0xf0
445 #define RX_MACRO_EC_MIX_TX1_MASK 0x0f
446 #define RX_MACRO_EC_MIX_TX2_MASK 0x0f
447 
448 #define COMP_MAX_COEFF 25
449 #define RX_NUM_CLKS_MAX	5
450 
451 struct comp_coeff_val {
452 	u8 lsb;
453 	u8 msb;
454 };
455 
456 enum {
457 	HPH_ULP,
458 	HPH_LOHIFI,
459 	HPH_MODE_MAX,
460 };
461 
462 static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = {
463 	{
464 		{0x40, 0x00},
465 		{0x4C, 0x00},
466 		{0x5A, 0x00},
467 		{0x6B, 0x00},
468 		{0x7F, 0x00},
469 		{0x97, 0x00},
470 		{0xB3, 0x00},
471 		{0xD5, 0x00},
472 		{0xFD, 0x00},
473 		{0x2D, 0x01},
474 		{0x66, 0x01},
475 		{0xA7, 0x01},
476 		{0xF8, 0x01},
477 		{0x57, 0x02},
478 		{0xC7, 0x02},
479 		{0x4B, 0x03},
480 		{0xE9, 0x03},
481 		{0xA3, 0x04},
482 		{0x7D, 0x05},
483 		{0x90, 0x06},
484 		{0xD1, 0x07},
485 		{0x49, 0x09},
486 		{0x00, 0x0B},
487 		{0x01, 0x0D},
488 		{0x59, 0x0F},
489 	},
490 	{
491 		{0x40, 0x00},
492 		{0x4C, 0x00},
493 		{0x5A, 0x00},
494 		{0x6B, 0x00},
495 		{0x80, 0x00},
496 		{0x98, 0x00},
497 		{0xB4, 0x00},
498 		{0xD5, 0x00},
499 		{0xFE, 0x00},
500 		{0x2E, 0x01},
501 		{0x66, 0x01},
502 		{0xA9, 0x01},
503 		{0xF8, 0x01},
504 		{0x56, 0x02},
505 		{0xC4, 0x02},
506 		{0x4F, 0x03},
507 		{0xF0, 0x03},
508 		{0xAE, 0x04},
509 		{0x8B, 0x05},
510 		{0x8E, 0x06},
511 		{0xBC, 0x07},
512 		{0x56, 0x09},
513 		{0x0F, 0x0B},
514 		{0x13, 0x0D},
515 		{0x6F, 0x0F},
516 	},
517 };
518 
519 enum {
520 	INTERP_HPHL,
521 	INTERP_HPHR,
522 	INTERP_AUX,
523 	INTERP_MAX
524 };
525 
526 enum {
527 	RX_MACRO_RX0,
528 	RX_MACRO_RX1,
529 	RX_MACRO_RX2,
530 	RX_MACRO_RX3,
531 	RX_MACRO_RX4,
532 	RX_MACRO_RX5,
533 	RX_MACRO_PORTS_MAX
534 };
535 
536 enum {
537 	RX_MACRO_COMP1, /* HPH_L */
538 	RX_MACRO_COMP2, /* HPH_R */
539 	RX_MACRO_COMP_MAX
540 };
541 
542 enum {
543 	RX_MACRO_EC0_MUX = 0,
544 	RX_MACRO_EC1_MUX,
545 	RX_MACRO_EC2_MUX,
546 	RX_MACRO_EC_MUX_MAX,
547 };
548 
549 enum {
550 	INTn_1_INP_SEL_ZERO = 0,
551 	INTn_1_INP_SEL_DEC0,
552 	INTn_1_INP_SEL_DEC1,
553 	INTn_1_INP_SEL_IIR0,
554 	INTn_1_INP_SEL_IIR1,
555 	INTn_1_INP_SEL_RX0,
556 	INTn_1_INP_SEL_RX1,
557 	INTn_1_INP_SEL_RX2,
558 	INTn_1_INP_SEL_RX3,
559 	INTn_1_INP_SEL_RX4,
560 	INTn_1_INP_SEL_RX5,
561 };
562 
563 enum {
564 	INTn_2_INP_SEL_ZERO = 0,
565 	INTn_2_INP_SEL_RX0,
566 	INTn_2_INP_SEL_RX1,
567 	INTn_2_INP_SEL_RX2,
568 	INTn_2_INP_SEL_RX3,
569 	INTn_2_INP_SEL_RX4,
570 	INTn_2_INP_SEL_RX5,
571 };
572 
573 enum {
574 	INTERP_MAIN_PATH,
575 	INTERP_MIX_PATH,
576 };
577 
578 /* Codec supports 2 IIR filters */
579 enum {
580 	IIR0 = 0,
581 	IIR1,
582 	IIR_MAX,
583 };
584 
585 /* Each IIR has 5 Filter Stages */
586 enum {
587 	BAND1 = 0,
588 	BAND2,
589 	BAND3,
590 	BAND4,
591 	BAND5,
592 	BAND_MAX,
593 };
594 
595 #define RX_MACRO_IIR_FILTER_SIZE	(sizeof(u32) * BAND_MAX)
596 
597 #define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \
598 { \
599 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
600 	.info = rx_macro_iir_filter_info, \
601 	.get = rx_macro_get_iir_band_audio_mixer, \
602 	.put = rx_macro_put_iir_band_audio_mixer, \
603 	.private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
604 		.iir_idx = iidx, \
605 		.band_idx = bidx, \
606 		.bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \
607 	} \
608 }
609 
610 struct interp_sample_rate {
611 	int sample_rate;
612 	int rate_val;
613 };
614 
615 static struct interp_sample_rate sr_val_tbl[] = {
616 	{8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5},
617 	{192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA},
618 	{176400, 0xB}, {352800, 0xC},
619 };
620 
621 enum {
622 	RX_MACRO_AIF_INVALID = 0,
623 	RX_MACRO_AIF1_PB,
624 	RX_MACRO_AIF2_PB,
625 	RX_MACRO_AIF3_PB,
626 	RX_MACRO_AIF4_PB,
627 	RX_MACRO_AIF_ECHO,
628 	RX_MACRO_MAX_DAIS,
629 };
630 
631 enum {
632 	RX_MACRO_AIF1_CAP = 0,
633 	RX_MACRO_AIF2_CAP,
634 	RX_MACRO_AIF3_CAP,
635 	RX_MACRO_MAX_AIF_CAP_DAIS
636 };
637 
638 struct rx_macro {
639 	struct device *dev;
640 	int comp_enabled[RX_MACRO_COMP_MAX];
641 	/* Main path clock users count */
642 	int main_clk_users[INTERP_MAX];
643 	int rx_port_value[RX_MACRO_PORTS_MAX];
644 	u16 prim_int_users[INTERP_MAX];
645 	int rx_mclk_users;
646 	int clsh_users;
647 	int rx_mclk_cnt;
648 	enum lpass_codec_version codec_version;
649 	int rxn_reg_stride;
650 	int rxn_reg_stride2;
651 	bool is_ear_mode_on;
652 	bool hph_pwr_mode;
653 	bool hph_hd2_mode;
654 	struct snd_soc_component *component;
655 	unsigned long active_ch_mask[RX_MACRO_MAX_DAIS];
656 	unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS];
657 	u16 bit_width[RX_MACRO_MAX_DAIS];
658 	int is_softclip_on;
659 	int is_aux_hpf_on;
660 	int softclip_clk_users;
661 	struct lpass_macro *pds;
662 	struct regmap *regmap;
663 	struct clk *mclk;
664 	struct clk *npl;
665 	struct clk *macro;
666 	struct clk *dcodec;
667 	struct clk *fsgen;
668 	struct clk_hw hw;
669 };
670 #define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw)
671 
672 struct wcd_iir_filter_ctl {
673 	unsigned int iir_idx;
674 	unsigned int band_idx;
675 	struct soc_bytes_ext bytes_ext;
676 };
677 
678 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
679 
680 static const char * const rx_int_mix_mux_text[] = {
681 	"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
682 };
683 
684 static const char * const rx_prim_mix_text[] = {
685 	"ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
686 	"RX3", "RX4", "RX5"
687 };
688 
689 static const char * const rx_sidetone_mix_text[] = {
690 	"ZERO", "SRC0", "SRC1", "SRC_SUM"
691 };
692 
693 static const char * const iir_inp_mux_text[] = {
694 	"ZERO", "DEC0", "DEC1", "DEC2", "DEC3",
695 	"RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
696 };
697 
698 static const char * const rx_int_dem_inp_mux_text[] = {
699 	"NORMAL_DSM_OUT", "CLSH_DSM_OUT",
700 };
701 
702 static const char * const rx_int0_1_interp_mux_text[] = {
703 	"ZERO", "RX INT0_1 MIX1",
704 };
705 
706 static const char * const rx_int1_1_interp_mux_text[] = {
707 	"ZERO", "RX INT1_1 MIX1",
708 };
709 
710 static const char * const rx_int2_1_interp_mux_text[] = {
711 	"ZERO", "RX INT2_1 MIX1",
712 };
713 
714 static const char * const rx_int0_2_interp_mux_text[] = {
715 	"ZERO", "RX INT0_2 MUX",
716 };
717 
718 static const char * const rx_int1_2_interp_mux_text[] = {
719 	"ZERO", "RX INT1_2 MUX",
720 };
721 
722 static const char * const rx_int2_2_interp_mux_text[] = {
723 	"ZERO", "RX INT2_2 MUX",
724 };
725 
726 static const char *const rx_macro_mux_text[] = {
727 	"ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB"
728 };
729 
730 static const char *const rx_macro_hph_pwr_mode_text[] = {
731 	"ULP", "LOHIFI"
732 };
733 
734 static const char * const rx_echo_mux_text[] = {
735 	"ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2"
736 };
737 
738 static const struct soc_enum rx_macro_hph_pwr_mode_enum =
739 		SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text);
740 static const struct soc_enum rx_mix_tx2_mux_enum =
741 		SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text);
742 static const struct soc_enum rx_mix_tx1_mux_enum =
743 		SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text);
744 static const struct soc_enum rx_mix_tx0_mux_enum =
745 		SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, rx_echo_mux_text);
746 
747 static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0,
748 			    rx_int_mix_mux_text);
749 static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0,
750 			    rx_int_mix_mux_text);
751 static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0,
752 			    rx_int_mix_mux_text);
753 
754 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0,
755 			    rx_prim_mix_text);
756 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4,
757 			    rx_prim_mix_text);
758 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4,
759 			    rx_prim_mix_text);
760 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0,
761 			    rx_prim_mix_text);
762 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4,
763 			    rx_prim_mix_text);
764 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4,
765 			    rx_prim_mix_text);
766 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0,
767 			    rx_prim_mix_text);
768 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4,
769 			    rx_prim_mix_text);
770 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4,
771 			    rx_prim_mix_text);
772 
773 static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2,
774 			    rx_sidetone_mix_text);
775 static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4,
776 			    rx_sidetone_mix_text);
777 static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6,
778 			    rx_sidetone_mix_text);
779 static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0,
780 			    iir_inp_mux_text);
781 static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0,
782 			    iir_inp_mux_text);
783 static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0,
784 			    iir_inp_mux_text);
785 static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0,
786 			    iir_inp_mux_text);
787 static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0,
788 			    iir_inp_mux_text);
789 static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0,
790 			    iir_inp_mux_text);
791 static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0,
792 			    iir_inp_mux_text);
793 static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0,
794 			    iir_inp_mux_text);
795 
796 static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0,
797 			    rx_int0_1_interp_mux_text);
798 static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0,
799 			    rx_int1_1_interp_mux_text);
800 static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0,
801 			    rx_int2_1_interp_mux_text);
802 static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0,
803 			    rx_int0_2_interp_mux_text);
804 static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,
805 			    rx_int1_2_interp_mux_text);
806 static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,
807 			    rx_int2_2_interp_mux_text);
808 static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,
809 			    rx_int_dem_inp_mux_text);
810 static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,
811 			    rx_int_dem_inp_mux_text);
812 static SOC_ENUM_SINGLE_DECL(rx_2_5_int1_dem_inp_enum, CDC_2_5_RX_RX1_RX_PATH_CFG1, 0,
813 			    rx_int_dem_inp_mux_text);
814 
815 static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
816 static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
817 static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
818 static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
819 static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
820 static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
821 
822 static const struct snd_kcontrol_new rx_mix_tx1_mux =
823 		SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
824 static const struct snd_kcontrol_new rx_mix_tx2_mux =
825 		SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
826 static const struct snd_kcontrol_new rx_int0_2_mux =
827 		SOC_DAPM_ENUM("rx_int0_2", rx_int0_2_enum);
828 static const struct snd_kcontrol_new rx_int1_2_mux =
829 		SOC_DAPM_ENUM("rx_int1_2", rx_int1_2_enum);
830 static const struct snd_kcontrol_new rx_int2_2_mux =
831 		SOC_DAPM_ENUM("rx_int2_2", rx_int2_2_enum);
832 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
833 		SOC_DAPM_ENUM("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum);
834 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
835 		SOC_DAPM_ENUM("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum);
836 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
837 		SOC_DAPM_ENUM("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum);
838 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
839 		SOC_DAPM_ENUM("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum);
840 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
841 		SOC_DAPM_ENUM("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum);
842 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
843 		SOC_DAPM_ENUM("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum);
844 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
845 		SOC_DAPM_ENUM("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum);
846 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
847 		SOC_DAPM_ENUM("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum);
848 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
849 		SOC_DAPM_ENUM("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum);
850 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
851 		SOC_DAPM_ENUM("rx_int0_mix2_inp", rx_int0_mix2_inp_enum);
852 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
853 		SOC_DAPM_ENUM("rx_int1_mix2_inp", rx_int1_mix2_inp_enum);
854 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
855 		SOC_DAPM_ENUM("rx_int2_mix2_inp", rx_int2_mix2_inp_enum);
856 static const struct snd_kcontrol_new iir0_inp0_mux =
857 		SOC_DAPM_ENUM("iir0_inp0", iir0_inp0_enum);
858 static const struct snd_kcontrol_new iir0_inp1_mux =
859 		SOC_DAPM_ENUM("iir0_inp1", iir0_inp1_enum);
860 static const struct snd_kcontrol_new iir0_inp2_mux =
861 		SOC_DAPM_ENUM("iir0_inp2", iir0_inp2_enum);
862 static const struct snd_kcontrol_new iir0_inp3_mux =
863 		SOC_DAPM_ENUM("iir0_inp3", iir0_inp3_enum);
864 static const struct snd_kcontrol_new iir1_inp0_mux =
865 		SOC_DAPM_ENUM("iir1_inp0", iir1_inp0_enum);
866 static const struct snd_kcontrol_new iir1_inp1_mux =
867 		SOC_DAPM_ENUM("iir1_inp1", iir1_inp1_enum);
868 static const struct snd_kcontrol_new iir1_inp2_mux =
869 		SOC_DAPM_ENUM("iir1_inp2", iir1_inp2_enum);
870 static const struct snd_kcontrol_new iir1_inp3_mux =
871 		SOC_DAPM_ENUM("iir1_inp3", iir1_inp3_enum);
872 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
873 		SOC_DAPM_ENUM("rx_int0_1_interp", rx_int0_1_interp_enum);
874 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
875 		SOC_DAPM_ENUM("rx_int1_1_interp", rx_int1_1_interp_enum);
876 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
877 		SOC_DAPM_ENUM("rx_int2_1_interp", rx_int2_1_interp_enum);
878 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
879 		SOC_DAPM_ENUM("rx_int0_2_interp", rx_int0_2_interp_enum);
880 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
881 		SOC_DAPM_ENUM("rx_int1_2_interp", rx_int1_2_interp_enum);
882 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
883 		SOC_DAPM_ENUM("rx_int2_2_interp", rx_int2_2_interp_enum);
884 static const struct snd_kcontrol_new rx_mix_tx0_mux =
885 		SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
886 
887 static const struct reg_default rx_defaults[] = {
888 	/* RX Macro */
889 	{ CDC_RX_TOP_TOP_CFG0, 0x00 },
890 	{ CDC_RX_TOP_SWR_CTRL, 0x00 },
891 	{ CDC_RX_TOP_DEBUG, 0x00 },
892 	{ CDC_RX_TOP_DEBUG_BUS, 0x00 },
893 	{ CDC_RX_TOP_DEBUG_EN0, 0x00 },
894 	{ CDC_RX_TOP_DEBUG_EN1, 0x00 },
895 	{ CDC_RX_TOP_DEBUG_EN2, 0x00 },
896 	{ CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 },
897 	{ CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 },
898 	{ CDC_RX_TOP_HPHL_COMP_LUT, 0x00 },
899 	{ CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 },
900 	{ CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 },
901 	{ CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 },
902 	{ CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 },
903 	{ CDC_RX_TOP_HPHR_COMP_LUT, 0x00 },
904 	{ CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 },
905 	{ CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 },
906 	{ CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 },
907 	{ CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 },
908 	{ CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 },
909 	{ CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 },
910 	{ CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 },
911 	{ CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 },
912 	{ CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 },
913 	{ CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 },
914 	{ CDC_RX_TOP_RX_I2S_CTL, 0x0C },
915 	{ CDC_RX_TOP_TX_I2S2_CTL, 0x0C },
916 	{ CDC_RX_TOP_I2S_CLK, 0x0C },
917 	{ CDC_RX_TOP_I2S_RESET, 0x00 },
918 	{ CDC_RX_TOP_I2S_MUX, 0x00 },
919 	{ CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
920 	{ CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
921 	{ CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
922 	{ CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 },
923 	{ CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 },
924 	{ CDC_RX_SOFTCLIP_CRC, 0x00 },
925 	{ CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 },
926 	{ CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
927 	{ CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
928 	{ CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
929 	{ CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
930 	{ CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
931 	{ CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
932 	{ CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
933 	{ CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 },
934 	{ CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
935 	{ CDC_RX_CLSH_CRC, 0x00 },
936 	{ CDC_RX_CLSH_DLY_CTRL, 0x03 },
937 	{ CDC_RX_CLSH_DECAY_CTRL, 0x02 },
938 	{ CDC_RX_CLSH_HPH_V_PA, 0x1C },
939 	{ CDC_RX_CLSH_EAR_V_PA, 0x39 },
940 	{ CDC_RX_CLSH_HPH_V_HD, 0x0C },
941 	{ CDC_RX_CLSH_EAR_V_HD, 0x0C },
942 	{ CDC_RX_CLSH_K1_MSB, 0x01 },
943 	{ CDC_RX_CLSH_K1_LSB, 0x00 },
944 	{ CDC_RX_CLSH_K2_MSB, 0x00 },
945 	{ CDC_RX_CLSH_K2_LSB, 0x80 },
946 	{ CDC_RX_CLSH_IDLE_CTRL, 0x00 },
947 	{ CDC_RX_CLSH_IDLE_HPH, 0x00 },
948 	{ CDC_RX_CLSH_IDLE_EAR, 0x00 },
949 	{ CDC_RX_CLSH_TEST0, 0x07 },
950 	{ CDC_RX_CLSH_TEST1, 0x00 },
951 	{ CDC_RX_CLSH_OVR_VREF, 0x00 },
952 	{ CDC_RX_CLSH_CLSG_CTL, 0x02 },
953 	{ CDC_RX_CLSH_CLSG_CFG1, 0x9A },
954 	{ CDC_RX_CLSH_CLSG_CFG2, 0x10 },
955 	{ CDC_RX_BCL_VBAT_PATH_CTL, 0x00 },
956 	{ CDC_RX_BCL_VBAT_CFG, 0x10 },
957 	{ CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 },
958 	{ CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 },
959 	{ CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 },
960 	{ CDC_RX_BCL_VBAT_PK_EST1, 0xE0 },
961 	{ CDC_RX_BCL_VBAT_PK_EST2, 0x01 },
962 	{ CDC_RX_BCL_VBAT_PK_EST3, 0x40 },
963 	{ CDC_RX_BCL_VBAT_RF_PROC1, 0x2A },
964 	{ CDC_RX_BCL_VBAT_RF_PROC2, 0x00 },
965 	{ CDC_RX_BCL_VBAT_TAC1, 0x00 },
966 	{ CDC_RX_BCL_VBAT_TAC2, 0x18 },
967 	{ CDC_RX_BCL_VBAT_TAC3, 0x18 },
968 	{ CDC_RX_BCL_VBAT_TAC4, 0x03 },
969 	{ CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 },
970 	{ CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 },
971 	{ CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 },
972 	{ CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 },
973 	{ CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 },
974 	{ CDC_RX_BCL_VBAT_DEBUG1, 0x00 },
975 	{ CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 },
976 	{ CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 },
977 	{ CDC_RX_BCL_VBAT_BAN, 0x0C },
978 	{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 },
979 	{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 },
980 	{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 },
981 	{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 },
982 	{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B },
983 	{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 },
984 	{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 },
985 	{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 },
986 	{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 },
987 	{ CDC_RX_BCL_VBAT_ATTN1, 0x04 },
988 	{ CDC_RX_BCL_VBAT_ATTN2, 0x08 },
989 	{ CDC_RX_BCL_VBAT_ATTN3, 0x0C },
990 	{ CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 },
991 	{ CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 },
992 	{ CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 },
993 	{ CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 },
994 	{ CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 },
995 	{ CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 },
996 	{ CDC_RX_BCL_VBAT_DECODE_ST, 0x00 },
997 	{ CDC_RX_INTR_CTRL_CFG, 0x00 },
998 	{ CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 },
999 	{ CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF },
1000 	{ CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 },
1001 	{ CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 },
1002 	{ CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF },
1003 	{ CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 },
1004 	{ CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 },
1005 	{ CDC_RX_INTR_CTRL_LEVEL0, 0x00 },
1006 	{ CDC_RX_INTR_CTRL_BYPASS0, 0x00 },
1007 	{ CDC_RX_INTR_CTRL_SET0, 0x00 },
1008 	{ CDC_RX_RX0_RX_PATH_CTL, 0x04 },
1009 	{ CDC_RX_RX0_RX_PATH_CFG0, 0x00 },
1010 	{ CDC_RX_RX0_RX_PATH_CFG1, 0x64 },
1011 	{ CDC_RX_RX0_RX_PATH_CFG2, 0x8F },
1012 	{ CDC_RX_RX0_RX_PATH_CFG3, 0x00 },
1013 	{ CDC_RX_RX0_RX_VOL_CTL, 0x00 },
1014 	{ CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 },
1015 	{ CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E },
1016 	{ CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 },
1017 	{ CDC_RX_RX0_RX_PATH_SEC1, 0x08 },
1018 	{ CDC_RX_RX0_RX_PATH_SEC2, 0x00 },
1019 	{ CDC_RX_RX0_RX_PATH_SEC3, 0x00 },
1020 	{ CDC_RX_RX0_RX_PATH_SEC4, 0x00 },
1021 	{ CDC_RX_RX0_RX_PATH_SEC7, 0x00 },
1022 	{ CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 },
1023 	{ CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 },
1024 	{ CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 },
1025 	{ CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 },
1026 	{ CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 },
1027 	{ CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 },
1028 	{ CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 },
1029 	{ CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 },
1030 	{ CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 },
1031 	{ CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 },
1032 	{ CDC_RX_IDLE_DETECT_CFG0, 0x07 },
1033 	{ CDC_RX_IDLE_DETECT_CFG1, 0x3C },
1034 	{ CDC_RX_IDLE_DETECT_CFG2, 0x00 },
1035 	{ CDC_RX_IDLE_DETECT_CFG3, 0x00 },
1036 	{ CDC_RX_COMPANDER0_CTL0, 0x60 },
1037 	{ CDC_RX_COMPANDER0_CTL1, 0xDB },
1038 	{ CDC_RX_COMPANDER0_CTL2, 0xFF },
1039 	{ CDC_RX_COMPANDER0_CTL3, 0x35 },
1040 	{ CDC_RX_COMPANDER0_CTL4, 0xFF },
1041 	{ CDC_RX_COMPANDER0_CTL5, 0x00 },
1042 	{ CDC_RX_COMPANDER0_CTL6, 0x01 },
1043 	{ CDC_RX_COMPANDER0_CTL7, 0x28 },
1044 	{ CDC_RX_COMPANDER1_CTL0, 0x60 },
1045 	{ CDC_RX_COMPANDER1_CTL1, 0xDB },
1046 	{ CDC_RX_COMPANDER1_CTL2, 0xFF },
1047 	{ CDC_RX_COMPANDER1_CTL3, 0x35 },
1048 	{ CDC_RX_COMPANDER1_CTL4, 0xFF },
1049 	{ CDC_RX_COMPANDER1_CTL5, 0x00 },
1050 	{ CDC_RX_COMPANDER1_CTL6, 0x01 },
1051 	{ CDC_RX_COMPANDER1_CTL7, 0x28 },
1052 	{ CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
1053 	{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
1054 	{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
1055 	{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
1056 	{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
1057 	{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
1058 	{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
1059 	{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
1060 	{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
1061 	{ CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 },
1062 	{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
1063 	{ CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
1064 	{ CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
1065 	{ CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
1066 	{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
1067 	{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
1068 	{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
1069 	{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
1070 	{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
1071 	{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
1072 	{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
1073 	{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
1074 	{ CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 },
1075 	{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
1076 	{ CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
1077 	{ CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
1078 	{ CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
1079 	{ CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
1080 	{ CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
1081 	{ CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
1082 	{ CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
1083 	{ CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
1084 	{ CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
1085 	{ CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
1086 	{ CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
1087 	{ CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
1088 	{ CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
1089 	{ CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
1090 	{ CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 },
1091 	{ CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 },
1092 	{ CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 },
1093 	{ CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 },
1094 	{ CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 },
1095 	{ CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 },
1096 	{ CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 },
1097 	{ CDC_RX_EC_ASRC0_CTL0, 0x00 },
1098 	{ CDC_RX_EC_ASRC0_CTL1, 0x00 },
1099 	{ CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 },
1100 	{ CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
1101 	{ CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
1102 	{ CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
1103 	{ CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
1104 	{ CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 },
1105 	{ CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 },
1106 	{ CDC_RX_EC_ASRC1_CTL0, 0x00 },
1107 	{ CDC_RX_EC_ASRC1_CTL1, 0x00 },
1108 	{ CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 },
1109 	{ CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
1110 	{ CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
1111 	{ CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
1112 	{ CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
1113 	{ CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 },
1114 	{ CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 },
1115 	{ CDC_RX_EC_ASRC2_CTL0, 0x00 },
1116 	{ CDC_RX_EC_ASRC2_CTL1, 0x00 },
1117 	{ CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 },
1118 	{ CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 },
1119 	{ CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 },
1120 	{ CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 },
1121 	{ CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 },
1122 	{ CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 },
1123 	{ CDC_RX_DSD0_PATH_CTL, 0x00 },
1124 	{ CDC_RX_DSD0_CFG0, 0x00 },
1125 	{ CDC_RX_DSD0_CFG1, 0x62 },
1126 	{ CDC_RX_DSD0_CFG2, 0x96 },
1127 	{ CDC_RX_DSD1_PATH_CTL, 0x00 },
1128 	{ CDC_RX_DSD1_CFG0, 0x00 },
1129 	{ CDC_RX_DSD1_CFG1, 0x62 },
1130 	{ CDC_RX_DSD1_CFG2, 0x96 },
1131 };
1132 
1133 static const struct reg_default rx_2_5_defaults[] = {
1134 	{ CDC_2_5_RX_RX1_RX_PATH_CTL, 0x04 },
1135 	{ CDC_2_5_RX_RX1_RX_PATH_CFG0, 0x00 },
1136 	{ CDC_2_5_RX_RX1_RX_PATH_CFG1, 0x64 },
1137 	{ CDC_2_5_RX_RX1_RX_PATH_CFG2, 0x8F },
1138 	{ CDC_2_5_RX_RX1_RX_PATH_CFG3, 0x00 },
1139 	{ CDC_2_5_RX_RX1_RX_VOL_CTL, 0x00 },
1140 	{ CDC_2_5_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
1141 	{ CDC_2_5_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
1142 	{ CDC_2_5_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
1143 	{ CDC_2_5_RX_RX1_RX_PATH_SEC1, 0x08 },
1144 	{ CDC_2_5_RX_RX1_RX_PATH_SEC2, 0x00 },
1145 	{ CDC_2_5_RX_RX1_RX_PATH_SEC3, 0x00 },
1146 	{ CDC_2_5_RX_RX1_RX_PATH_SEC4, 0x00 },
1147 	{ CDC_2_5_RX_RX1_RX_PATH_SEC7, 0x00 },
1148 	{ CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
1149 	{ CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
1150 	{ CDC_2_5_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
1151 	{ CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
1152 	{ CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
1153 	{ CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
1154 	{ CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
1155 	{ CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
1156 	{ CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
1157 	{ CDC_2_5_RX_RX2_RX_PATH_CTL, 0x04 },
1158 	{ CDC_2_5_RX_RX2_RX_PATH_CFG0, 0x00 },
1159 	{ CDC_2_5_RX_RX2_RX_PATH_CFG1, 0x64 },
1160 	{ CDC_2_5_RX_RX2_RX_PATH_CFG2, 0x8F },
1161 	{ CDC_2_5_RX_RX2_RX_PATH_CFG3, 0x00 },
1162 	{ CDC_2_5_RX_RX2_RX_VOL_CTL, 0x00 },
1163 	{ CDC_2_5_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
1164 	{ CDC_2_5_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
1165 	{ CDC_2_5_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
1166 	{ CDC_2_5_RX_RX2_RX_PATH_SEC0, 0x04 },
1167 	{ CDC_2_5_RX_RX2_RX_PATH_SEC1, 0x08 },
1168 	{ CDC_2_5_RX_RX2_RX_PATH_SEC2, 0x00 },
1169 	{ CDC_2_5_RX_RX2_RX_PATH_SEC3, 0x00 },
1170 	{ CDC_2_5_RX_RX2_RX_PATH_SEC4, 0x00 },
1171 	{ CDC_2_5_RX_RX2_RX_PATH_SEC5, 0x00 },
1172 	{ CDC_2_5_RX_RX2_RX_PATH_SEC6, 0x00 },
1173 	{ CDC_2_5_RX_RX2_RX_PATH_SEC7, 0x00 },
1174 	{ CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
1175 	{ CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
1176 	{ CDC_2_5_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
1177 };
1178 
1179 static const struct reg_default rx_pre_2_5_defaults[] = {
1180 	{ CDC_RX_RX1_RX_PATH_CTL, 0x04 },
1181 	{ CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
1182 	{ CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
1183 	{ CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
1184 	{ CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
1185 	{ CDC_RX_RX1_RX_VOL_CTL, 0x00 },
1186 	{ CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
1187 	{ CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
1188 	{ CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
1189 	{ CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
1190 	{ CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
1191 	{ CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
1192 	{ CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
1193 	{ CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
1194 	{ CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
1195 	{ CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
1196 	{ CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
1197 	{ CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
1198 	{ CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
1199 	{ CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
1200 	{ CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
1201 	{ CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
1202 	{ CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
1203 	{ CDC_RX_RX2_RX_PATH_CTL, 0x04 },
1204 	{ CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
1205 	{ CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
1206 	{ CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
1207 	{ CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
1208 	{ CDC_RX_RX2_RX_VOL_CTL, 0x00 },
1209 	{ CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
1210 	{ CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
1211 	{ CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
1212 	{ CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
1213 	{ CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
1214 	{ CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
1215 	{ CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
1216 	{ CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
1217 	{ CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
1218 	{ CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
1219 	{ CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
1220 	{ CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
1221 	{ CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
1222 	{ CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
1223 
1224 };
1225 
rx_is_wronly_register(struct device * dev,unsigned int reg)1226 static bool rx_is_wronly_register(struct device *dev,
1227 					unsigned int reg)
1228 {
1229 	switch (reg) {
1230 	case CDC_RX_BCL_VBAT_GAIN_UPD_MON:
1231 	case CDC_RX_INTR_CTRL_CLR_COMMIT:
1232 	case CDC_RX_INTR_CTRL_PIN1_CLEAR0:
1233 	case CDC_RX_INTR_CTRL_PIN2_CLEAR0:
1234 		return true;
1235 	}
1236 
1237 	return false;
1238 }
1239 
rx_is_volatile_register(struct device * dev,unsigned int reg)1240 static bool rx_is_volatile_register(struct device *dev, unsigned int reg)
1241 {
1242 	/* Update volatile list for rx/tx macros */
1243 	switch (reg) {
1244 	case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1245 	case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1246 	case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1247 	case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1248 	case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1249 	case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1250 	case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1251 	case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1252 	case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1253 	case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1254 	case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1255 	case CDC_RX_BCL_VBAT_DECODE_ST:
1256 	case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1257 	case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1258 	case CDC_RX_COMPANDER0_CTL6:
1259 	case CDC_RX_COMPANDER1_CTL6:
1260 	case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1261 	case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1262 	case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1263 	case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1264 	case CDC_RX_EC_ASRC0_STATUS_FIFO:
1265 	case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1266 	case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1267 	case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1268 	case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1269 	case CDC_RX_EC_ASRC1_STATUS_FIFO:
1270 	case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1271 	case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1272 	case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1273 	case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1274 	case CDC_RX_EC_ASRC2_STATUS_FIFO:
1275 		return true;
1276 	}
1277 	return false;
1278 }
1279 
rx_pre_2_5_is_rw_register(struct device * dev,unsigned int reg)1280 static bool rx_pre_2_5_is_rw_register(struct device *dev, unsigned int reg)
1281 {
1282 	switch (reg) {
1283 	case CDC_RX_RX1_RX_PATH_CTL:
1284 	case CDC_RX_RX1_RX_PATH_CFG0:
1285 	case CDC_RX_RX1_RX_PATH_CFG1:
1286 	case CDC_RX_RX1_RX_PATH_CFG2:
1287 	case CDC_RX_RX1_RX_PATH_CFG3:
1288 	case CDC_RX_RX1_RX_VOL_CTL:
1289 	case CDC_RX_RX1_RX_PATH_MIX_CTL:
1290 	case CDC_RX_RX1_RX_PATH_MIX_CFG:
1291 	case CDC_RX_RX1_RX_VOL_MIX_CTL:
1292 	case CDC_RX_RX1_RX_PATH_SEC1:
1293 	case CDC_RX_RX1_RX_PATH_SEC2:
1294 	case CDC_RX_RX1_RX_PATH_SEC3:
1295 	case CDC_RX_RX1_RX_PATH_SEC4:
1296 	case CDC_RX_RX1_RX_PATH_SEC7:
1297 	case CDC_RX_RX1_RX_PATH_MIX_SEC0:
1298 	case CDC_RX_RX1_RX_PATH_MIX_SEC1:
1299 	case CDC_RX_RX1_RX_PATH_DSM_CTL:
1300 	case CDC_RX_RX1_RX_PATH_DSM_DATA1:
1301 	case CDC_RX_RX1_RX_PATH_DSM_DATA2:
1302 	case CDC_RX_RX1_RX_PATH_DSM_DATA3:
1303 	case CDC_RX_RX1_RX_PATH_DSM_DATA4:
1304 	case CDC_RX_RX1_RX_PATH_DSM_DATA5:
1305 	case CDC_RX_RX1_RX_PATH_DSM_DATA6:
1306 	case CDC_RX_RX2_RX_PATH_CTL:
1307 	case CDC_RX_RX2_RX_PATH_CFG0:
1308 	case CDC_RX_RX2_RX_PATH_CFG1:
1309 	case CDC_RX_RX2_RX_PATH_CFG2:
1310 	case CDC_RX_RX2_RX_PATH_CFG3:
1311 	case CDC_RX_RX2_RX_VOL_CTL:
1312 	case CDC_RX_RX2_RX_PATH_MIX_CTL:
1313 	case CDC_RX_RX2_RX_PATH_MIX_CFG:
1314 	case CDC_RX_RX2_RX_VOL_MIX_CTL:
1315 	case CDC_RX_RX2_RX_PATH_SEC0:
1316 	case CDC_RX_RX2_RX_PATH_SEC1:
1317 	case CDC_RX_RX2_RX_PATH_SEC2:
1318 	case CDC_RX_RX2_RX_PATH_SEC3:
1319 	case CDC_RX_RX2_RX_PATH_SEC4:
1320 	case CDC_RX_RX2_RX_PATH_SEC5:
1321 	case CDC_RX_RX2_RX_PATH_SEC6:
1322 	case CDC_RX_RX2_RX_PATH_SEC7:
1323 	case CDC_RX_RX2_RX_PATH_MIX_SEC0:
1324 	case CDC_RX_RX2_RX_PATH_MIX_SEC1:
1325 	case CDC_RX_RX2_RX_PATH_DSM_CTL:
1326 		return true;
1327 	}
1328 
1329 	return false;
1330 }
1331 
rx_2_5_is_rw_register(struct device * dev,unsigned int reg)1332 static bool rx_2_5_is_rw_register(struct device *dev, unsigned int reg)
1333 {
1334 	switch (reg) {
1335 	case CDC_2_5_RX_RX1_RX_PATH_CTL:
1336 	case CDC_2_5_RX_RX1_RX_PATH_CFG0:
1337 	case CDC_2_5_RX_RX1_RX_PATH_CFG1:
1338 	case CDC_2_5_RX_RX1_RX_PATH_CFG2:
1339 	case CDC_2_5_RX_RX1_RX_PATH_CFG3:
1340 	case CDC_2_5_RX_RX1_RX_VOL_CTL:
1341 	case CDC_2_5_RX_RX1_RX_PATH_MIX_CTL:
1342 	case CDC_2_5_RX_RX1_RX_PATH_MIX_CFG:
1343 	case CDC_2_5_RX_RX1_RX_VOL_MIX_CTL:
1344 	case CDC_2_5_RX_RX1_RX_PATH_SEC1:
1345 	case CDC_2_5_RX_RX1_RX_PATH_SEC2:
1346 	case CDC_2_5_RX_RX1_RX_PATH_SEC3:
1347 	case CDC_2_5_RX_RX1_RX_PATH_SEC4:
1348 	case CDC_2_5_RX_RX1_RX_PATH_SEC7:
1349 	case CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0:
1350 	case CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1:
1351 	case CDC_2_5_RX_RX1_RX_PATH_DSM_CTL:
1352 	case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1:
1353 	case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2:
1354 	case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3:
1355 	case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4:
1356 	case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5:
1357 	case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6:
1358 	case CDC_2_5_RX_RX2_RX_PATH_CTL:
1359 	case CDC_2_5_RX_RX2_RX_PATH_CFG0:
1360 	case CDC_2_5_RX_RX2_RX_PATH_CFG1:
1361 	case CDC_2_5_RX_RX2_RX_PATH_CFG2:
1362 	case CDC_2_5_RX_RX2_RX_PATH_CFG3:
1363 	case CDC_2_5_RX_RX2_RX_VOL_CTL:
1364 	case CDC_2_5_RX_RX2_RX_PATH_MIX_CTL:
1365 	case CDC_2_5_RX_RX2_RX_PATH_MIX_CFG:
1366 	case CDC_2_5_RX_RX2_RX_VOL_MIX_CTL:
1367 	case CDC_2_5_RX_RX2_RX_PATH_SEC0:
1368 	case CDC_2_5_RX_RX2_RX_PATH_SEC1:
1369 	case CDC_2_5_RX_RX2_RX_PATH_SEC2:
1370 	case CDC_2_5_RX_RX2_RX_PATH_SEC3:
1371 	case CDC_2_5_RX_RX2_RX_PATH_SEC4:
1372 	case CDC_2_5_RX_RX2_RX_PATH_SEC5:
1373 	case CDC_2_5_RX_RX2_RX_PATH_SEC6:
1374 	case CDC_2_5_RX_RX2_RX_PATH_SEC7:
1375 	case CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0:
1376 	case CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1:
1377 	case CDC_2_5_RX_RX2_RX_PATH_DSM_CTL:
1378 		return true;
1379 	}
1380 
1381 	return false;
1382 }
1383 
rx_is_rw_register(struct device * dev,unsigned int reg)1384 static bool rx_is_rw_register(struct device *dev, unsigned int reg)
1385 {
1386 	struct rx_macro *rx = dev_get_drvdata(dev);
1387 
1388 	switch (reg) {
1389 	case CDC_RX_TOP_TOP_CFG0:
1390 	case CDC_RX_TOP_SWR_CTRL:
1391 	case CDC_RX_TOP_DEBUG:
1392 	case CDC_RX_TOP_DEBUG_BUS:
1393 	case CDC_RX_TOP_DEBUG_EN0:
1394 	case CDC_RX_TOP_DEBUG_EN1:
1395 	case CDC_RX_TOP_DEBUG_EN2:
1396 	case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1397 	case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1398 	case CDC_RX_TOP_HPHL_COMP_LUT:
1399 	case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1400 	case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1401 	case CDC_RX_TOP_HPHR_COMP_LUT:
1402 	case CDC_RX_TOP_DSD0_DEBUG_CFG0:
1403 	case CDC_RX_TOP_DSD0_DEBUG_CFG1:
1404 	case CDC_RX_TOP_DSD0_DEBUG_CFG3:
1405 	case CDC_RX_TOP_DSD1_DEBUG_CFG0:
1406 	case CDC_RX_TOP_DSD1_DEBUG_CFG1:
1407 	case CDC_RX_TOP_DSD1_DEBUG_CFG3:
1408 	case CDC_RX_TOP_RX_I2S_CTL:
1409 	case CDC_RX_TOP_TX_I2S2_CTL:
1410 	case CDC_RX_TOP_I2S_CLK:
1411 	case CDC_RX_TOP_I2S_RESET:
1412 	case CDC_RX_TOP_I2S_MUX:
1413 	case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL:
1414 	case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL:
1415 	case CDC_RX_CLK_RST_CTRL_SWR_CONTROL:
1416 	case CDC_RX_CLK_RST_CTRL_DSD_CONTROL:
1417 	case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL:
1418 	case CDC_RX_SOFTCLIP_CRC:
1419 	case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL:
1420 	case CDC_RX_INP_MUX_RX_INT0_CFG0:
1421 	case CDC_RX_INP_MUX_RX_INT0_CFG1:
1422 	case CDC_RX_INP_MUX_RX_INT1_CFG0:
1423 	case CDC_RX_INP_MUX_RX_INT1_CFG1:
1424 	case CDC_RX_INP_MUX_RX_INT2_CFG0:
1425 	case CDC_RX_INP_MUX_RX_INT2_CFG1:
1426 	case CDC_RX_INP_MUX_RX_MIX_CFG4:
1427 	case CDC_RX_INP_MUX_RX_MIX_CFG5:
1428 	case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0:
1429 	case CDC_RX_CLSH_CRC:
1430 	case CDC_RX_CLSH_DLY_CTRL:
1431 	case CDC_RX_CLSH_DECAY_CTRL:
1432 	case CDC_RX_CLSH_HPH_V_PA:
1433 	case CDC_RX_CLSH_EAR_V_PA:
1434 	case CDC_RX_CLSH_HPH_V_HD:
1435 	case CDC_RX_CLSH_EAR_V_HD:
1436 	case CDC_RX_CLSH_K1_MSB:
1437 	case CDC_RX_CLSH_K1_LSB:
1438 	case CDC_RX_CLSH_K2_MSB:
1439 	case CDC_RX_CLSH_K2_LSB:
1440 	case CDC_RX_CLSH_IDLE_CTRL:
1441 	case CDC_RX_CLSH_IDLE_HPH:
1442 	case CDC_RX_CLSH_IDLE_EAR:
1443 	case CDC_RX_CLSH_TEST0:
1444 	case CDC_RX_CLSH_TEST1:
1445 	case CDC_RX_CLSH_OVR_VREF:
1446 	case CDC_RX_CLSH_CLSG_CTL:
1447 	case CDC_RX_CLSH_CLSG_CFG1:
1448 	case CDC_RX_CLSH_CLSG_CFG2:
1449 	case CDC_RX_BCL_VBAT_PATH_CTL:
1450 	case CDC_RX_BCL_VBAT_CFG:
1451 	case CDC_RX_BCL_VBAT_ADC_CAL1:
1452 	case CDC_RX_BCL_VBAT_ADC_CAL2:
1453 	case CDC_RX_BCL_VBAT_ADC_CAL3:
1454 	case CDC_RX_BCL_VBAT_PK_EST1:
1455 	case CDC_RX_BCL_VBAT_PK_EST2:
1456 	case CDC_RX_BCL_VBAT_PK_EST3:
1457 	case CDC_RX_BCL_VBAT_RF_PROC1:
1458 	case CDC_RX_BCL_VBAT_RF_PROC2:
1459 	case CDC_RX_BCL_VBAT_TAC1:
1460 	case CDC_RX_BCL_VBAT_TAC2:
1461 	case CDC_RX_BCL_VBAT_TAC3:
1462 	case CDC_RX_BCL_VBAT_TAC4:
1463 	case CDC_RX_BCL_VBAT_GAIN_UPD1:
1464 	case CDC_RX_BCL_VBAT_GAIN_UPD2:
1465 	case CDC_RX_BCL_VBAT_GAIN_UPD3:
1466 	case CDC_RX_BCL_VBAT_GAIN_UPD4:
1467 	case CDC_RX_BCL_VBAT_GAIN_UPD5:
1468 	case CDC_RX_BCL_VBAT_DEBUG1:
1469 	case CDC_RX_BCL_VBAT_BAN:
1470 	case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1:
1471 	case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2:
1472 	case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3:
1473 	case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4:
1474 	case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5:
1475 	case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6:
1476 	case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7:
1477 	case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8:
1478 	case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9:
1479 	case CDC_RX_BCL_VBAT_ATTN1:
1480 	case CDC_RX_BCL_VBAT_ATTN2:
1481 	case CDC_RX_BCL_VBAT_ATTN3:
1482 	case CDC_RX_BCL_VBAT_DECODE_CTL1:
1483 	case CDC_RX_BCL_VBAT_DECODE_CTL2:
1484 	case CDC_RX_BCL_VBAT_DECODE_CFG1:
1485 	case CDC_RX_BCL_VBAT_DECODE_CFG2:
1486 	case CDC_RX_BCL_VBAT_DECODE_CFG3:
1487 	case CDC_RX_BCL_VBAT_DECODE_CFG4:
1488 	case CDC_RX_INTR_CTRL_CFG:
1489 	case CDC_RX_INTR_CTRL_PIN1_MASK0:
1490 	case CDC_RX_INTR_CTRL_PIN2_MASK0:
1491 	case CDC_RX_INTR_CTRL_LEVEL0:
1492 	case CDC_RX_INTR_CTRL_BYPASS0:
1493 	case CDC_RX_INTR_CTRL_SET0:
1494 	case CDC_RX_RX0_RX_PATH_CTL:
1495 	case CDC_RX_RX0_RX_PATH_CFG0:
1496 	case CDC_RX_RX0_RX_PATH_CFG1:
1497 	case CDC_RX_RX0_RX_PATH_CFG2:
1498 	case CDC_RX_RX0_RX_PATH_CFG3:
1499 	case CDC_RX_RX0_RX_VOL_CTL:
1500 	case CDC_RX_RX0_RX_PATH_MIX_CTL:
1501 	case CDC_RX_RX0_RX_PATH_MIX_CFG:
1502 	case CDC_RX_RX0_RX_VOL_MIX_CTL:
1503 	case CDC_RX_RX0_RX_PATH_SEC1:
1504 	case CDC_RX_RX0_RX_PATH_SEC2:
1505 	case CDC_RX_RX0_RX_PATH_SEC3:
1506 	case CDC_RX_RX0_RX_PATH_SEC4:
1507 	case CDC_RX_RX0_RX_PATH_SEC7:
1508 	case CDC_RX_RX0_RX_PATH_MIX_SEC0:
1509 	case CDC_RX_RX0_RX_PATH_MIX_SEC1:
1510 	case CDC_RX_RX0_RX_PATH_DSM_CTL:
1511 	case CDC_RX_RX0_RX_PATH_DSM_DATA1:
1512 	case CDC_RX_RX0_RX_PATH_DSM_DATA2:
1513 	case CDC_RX_RX0_RX_PATH_DSM_DATA3:
1514 	case CDC_RX_RX0_RX_PATH_DSM_DATA4:
1515 	case CDC_RX_RX0_RX_PATH_DSM_DATA5:
1516 	case CDC_RX_RX0_RX_PATH_DSM_DATA6:
1517 	case CDC_RX_IDLE_DETECT_PATH_CTL:
1518 	case CDC_RX_IDLE_DETECT_CFG0:
1519 	case CDC_RX_IDLE_DETECT_CFG1:
1520 	case CDC_RX_IDLE_DETECT_CFG2:
1521 	case CDC_RX_IDLE_DETECT_CFG3:
1522 	case CDC_RX_COMPANDER0_CTL0:
1523 	case CDC_RX_COMPANDER0_CTL1:
1524 	case CDC_RX_COMPANDER0_CTL2:
1525 	case CDC_RX_COMPANDER0_CTL3:
1526 	case CDC_RX_COMPANDER0_CTL4:
1527 	case CDC_RX_COMPANDER0_CTL5:
1528 	case CDC_RX_COMPANDER0_CTL7:
1529 	case CDC_RX_COMPANDER1_CTL0:
1530 	case CDC_RX_COMPANDER1_CTL1:
1531 	case CDC_RX_COMPANDER1_CTL2:
1532 	case CDC_RX_COMPANDER1_CTL3:
1533 	case CDC_RX_COMPANDER1_CTL4:
1534 	case CDC_RX_COMPANDER1_CTL5:
1535 	case CDC_RX_COMPANDER1_CTL7:
1536 	case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL:
1537 	case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL:
1538 	case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL:
1539 	case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL:
1540 	case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL:
1541 	case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL:
1542 	case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL:
1543 	case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL:
1544 	case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL:
1545 	case CDC_RX_SIDETONE_IIR0_IIR_CTL:
1546 	case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL:
1547 	case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL:
1548 	case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:
1549 	case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL:
1550 	case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL:
1551 	case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL:
1552 	case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL:
1553 	case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL:
1554 	case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL:
1555 	case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL:
1556 	case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL:
1557 	case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL:
1558 	case CDC_RX_SIDETONE_IIR1_IIR_CTL:
1559 	case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL:
1560 	case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:
1561 	case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:
1562 	case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0:
1563 	case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1:
1564 	case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2:
1565 	case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3:
1566 	case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0:
1567 	case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1:
1568 	case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2:
1569 	case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3:
1570 	case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL:
1571 	case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1:
1572 	case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL:
1573 	case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1:
1574 	case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL:
1575 	case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0:
1576 	case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL:
1577 	case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0:
1578 	case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL:
1579 	case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0:
1580 	case CDC_RX_EC_ASRC0_CLK_RST_CTL:
1581 	case CDC_RX_EC_ASRC0_CTL0:
1582 	case CDC_RX_EC_ASRC0_CTL1:
1583 	case CDC_RX_EC_ASRC0_FIFO_CTL:
1584 	case CDC_RX_EC_ASRC1_CLK_RST_CTL:
1585 	case CDC_RX_EC_ASRC1_CTL0:
1586 	case CDC_RX_EC_ASRC1_CTL1:
1587 	case CDC_RX_EC_ASRC1_FIFO_CTL:
1588 	case CDC_RX_EC_ASRC2_CLK_RST_CTL:
1589 	case CDC_RX_EC_ASRC2_CTL0:
1590 	case CDC_RX_EC_ASRC2_CTL1:
1591 	case CDC_RX_EC_ASRC2_FIFO_CTL:
1592 	case CDC_RX_DSD0_PATH_CTL:
1593 	case CDC_RX_DSD0_CFG0:
1594 	case CDC_RX_DSD0_CFG1:
1595 	case CDC_RX_DSD0_CFG2:
1596 	case CDC_RX_DSD1_PATH_CTL:
1597 	case CDC_RX_DSD1_CFG0:
1598 	case CDC_RX_DSD1_CFG1:
1599 	case CDC_RX_DSD1_CFG2:
1600 		return true;
1601 	}
1602 
1603 	switch (rx->codec_version) {
1604 	case LPASS_CODEC_VERSION_1_0:
1605 	case LPASS_CODEC_VERSION_1_1:
1606 	case LPASS_CODEC_VERSION_1_2:
1607 	case LPASS_CODEC_VERSION_2_0:
1608 	case LPASS_CODEC_VERSION_2_1:
1609 		return rx_pre_2_5_is_rw_register(dev, reg);
1610 	case LPASS_CODEC_VERSION_2_5:
1611 	case LPASS_CODEC_VERSION_2_6:
1612 	case LPASS_CODEC_VERSION_2_7:
1613 	case LPASS_CODEC_VERSION_2_8:
1614 		return rx_2_5_is_rw_register(dev, reg);
1615 	default:
1616 		break;
1617 	}
1618 
1619 	return false;
1620 }
1621 
rx_is_writeable_register(struct device * dev,unsigned int reg)1622 static bool rx_is_writeable_register(struct device *dev, unsigned int reg)
1623 {
1624 	bool ret;
1625 
1626 	ret = rx_is_rw_register(dev, reg);
1627 	if (!ret)
1628 		return rx_is_wronly_register(dev, reg);
1629 
1630 	return ret;
1631 }
1632 
rx_is_readable_register(struct device * dev,unsigned int reg)1633 static bool rx_is_readable_register(struct device *dev, unsigned int reg)
1634 {
1635 	switch (reg) {
1636 	case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1637 	case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1638 	case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1639 	case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1640 	case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1641 	case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1642 	case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1643 	case CDC_RX_BCL_VBAT_DECODE_ST:
1644 	case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1645 	case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1646 	case CDC_RX_COMPANDER0_CTL6:
1647 	case CDC_RX_COMPANDER1_CTL6:
1648 	case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1649 	case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1650 	case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1651 	case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1652 	case CDC_RX_EC_ASRC0_STATUS_FIFO:
1653 	case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1654 	case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1655 	case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1656 	case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1657 	case CDC_RX_EC_ASRC1_STATUS_FIFO:
1658 	case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1659 	case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1660 	case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1661 	case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1662 	case CDC_RX_EC_ASRC2_STATUS_FIFO:
1663 		return true;
1664 	}
1665 
1666 	return rx_is_rw_register(dev, reg);
1667 }
1668 
1669 static const struct regmap_config rx_regmap_config = {
1670 	.name = "rx_macro",
1671 	.reg_bits = 16,
1672 	.val_bits = 32, /* 8 but with 32 bit read/write */
1673 	.reg_stride = 4,
1674 	.cache_type = REGCACHE_FLAT,
1675 	.max_register = RX_MAX_OFFSET,
1676 	.writeable_reg = rx_is_writeable_register,
1677 	.volatile_reg = rx_is_volatile_register,
1678 	.readable_reg = rx_is_readable_register,
1679 };
1680 
rx_macro_int_dem_inp_mux_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1681 static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
1682 					struct snd_ctl_elem_value *ucontrol)
1683 {
1684 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
1685 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
1686 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1687 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1688 	unsigned short look_ahead_dly_reg;
1689 	unsigned int val;
1690 
1691 	val = ucontrol->value.enumerated.item[0];
1692 
1693 	if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0))
1694 		look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0);
1695 	else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1))
1696 		look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1);
1697 
1698 	/* Set Look Ahead Delay */
1699 	if (val)
1700 		snd_soc_component_update_bits(component, look_ahead_dly_reg,
1701 					      CDC_RX_DLY_ZN_EN_MASK,
1702 					      CDC_RX_DLY_ZN_ENABLE);
1703 	else
1704 		snd_soc_component_update_bits(component, look_ahead_dly_reg,
1705 					      CDC_RX_DLY_ZN_EN_MASK, 0);
1706 	/* Set DEM INP Select */
1707 	return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1708 }
1709 
1710 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1711 		SOC_DAPM_ENUM_EXT("rx_int0_dem_inp", rx_int0_dem_inp_enum,
1712 		  snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1713 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1714 		SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum,
1715 		  snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1716 
1717 static const struct snd_kcontrol_new rx_2_5_int1_dem_inp_mux =
1718 		SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_2_5_int1_dem_inp_enum,
1719 		  snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1720 
rx_macro_set_prim_interpolator_rate(struct snd_soc_dai * dai,int rate_reg_val,u32 sample_rate)1721 static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1722 					       int rate_reg_val, u32 sample_rate)
1723 {
1724 
1725 	u8 int_1_mix1_inp;
1726 	u32 j, port;
1727 	u16 int_mux_cfg0, int_mux_cfg1;
1728 	u16 int_fs_reg;
1729 	u8 inp0_sel, inp1_sel, inp2_sel;
1730 	struct snd_soc_component *component = dai->component;
1731 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1732 
1733 	for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1734 		int_1_mix1_inp = port;
1735 		int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0;
1736 		/*
1737 		 * Loop through all interpolator MUX inputs and find out
1738 		 * to which interpolator input, the rx port
1739 		 * is connected
1740 		 */
1741 		for (j = 0; j < INTERP_MAX; j++) {
1742 			int_mux_cfg1 = int_mux_cfg0 + 4;
1743 
1744 			inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1745 								CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
1746 			inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1747 								CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
1748 			inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
1749 								CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
1750 
1751 			if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1752 			    (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1753 			    (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
1754 				int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(rx, j);
1755 				/* sample_rate is in Hz */
1756 				snd_soc_component_update_bits(component, int_fs_reg,
1757 							      CDC_RX_PATH_PCM_RATE_MASK,
1758 							      rate_reg_val);
1759 			}
1760 			int_mux_cfg0 += 8;
1761 		}
1762 	}
1763 
1764 	return 0;
1765 }
1766 
rx_macro_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_reg_val,u32 sample_rate)1767 static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1768 					      int rate_reg_val, u32 sample_rate)
1769 {
1770 
1771 	u8 int_2_inp;
1772 	u32 j, port;
1773 	u16 int_mux_cfg1, int_fs_reg;
1774 	u8 int_mux_cfg1_val;
1775 	struct snd_soc_component *component = dai->component;
1776 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1777 
1778 	for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1779 		int_2_inp = port;
1780 
1781 		int_mux_cfg1 = CDC_RX_INP_MUX_RX_INT0_CFG1;
1782 		for (j = 0; j < INTERP_MAX; j++) {
1783 			int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
1784 									CDC_RX_INTX_2_SEL_MASK);
1785 
1786 			if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
1787 				int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j);
1788 				snd_soc_component_update_bits(component, int_fs_reg,
1789 							      CDC_RX_RXn_MIX_PCM_RATE_MASK,
1790 							      rate_reg_val);
1791 			}
1792 			int_mux_cfg1 += 8;
1793 		}
1794 	}
1795 	return 0;
1796 }
1797 
rx_macro_set_interpolator_rate(struct snd_soc_dai * dai,u32 sample_rate)1798 static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai,
1799 					  u32 sample_rate)
1800 {
1801 	int rate_val = 0;
1802 	int i, ret;
1803 
1804 	for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++)
1805 		if (sample_rate == sr_val_tbl[i].sample_rate)
1806 			rate_val = sr_val_tbl[i].rate_val;
1807 
1808 	ret = rx_macro_set_prim_interpolator_rate(dai, rate_val, sample_rate);
1809 	if (ret)
1810 		return ret;
1811 
1812 	ret = rx_macro_set_mix_interpolator_rate(dai, rate_val, sample_rate);
1813 
1814 	return ret;
1815 }
1816 
rx_macro_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1817 static int rx_macro_hw_params(struct snd_pcm_substream *substream,
1818 			      struct snd_pcm_hw_params *params,
1819 			      struct snd_soc_dai *dai)
1820 {
1821 	struct snd_soc_component *component = dai->component;
1822 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1823 	int ret;
1824 
1825 	switch (substream->stream) {
1826 	case SNDRV_PCM_STREAM_PLAYBACK:
1827 		ret = rx_macro_set_interpolator_rate(dai, params_rate(params));
1828 		if (ret) {
1829 			dev_err(component->dev, "%s: cannot set sample rate: %u\n",
1830 				__func__, params_rate(params));
1831 			return ret;
1832 		}
1833 		rx->bit_width[dai->id] = params_width(params);
1834 		break;
1835 	default:
1836 		break;
1837 	}
1838 	return 0;
1839 }
1840 
rx_macro_get_channel_map(const struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)1841 static int rx_macro_get_channel_map(const struct snd_soc_dai *dai,
1842 				    unsigned int *tx_num, unsigned int *tx_slot,
1843 				    unsigned int *rx_num, unsigned int *rx_slot)
1844 {
1845 	struct snd_soc_component *component = dai->component;
1846 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1847 	u16 val, mask = 0, cnt = 0, temp;
1848 
1849 	switch (dai->id) {
1850 	case RX_MACRO_AIF1_PB:
1851 	case RX_MACRO_AIF2_PB:
1852 	case RX_MACRO_AIF3_PB:
1853 	case RX_MACRO_AIF4_PB:
1854 		for_each_set_bit(temp, &rx->active_ch_mask[dai->id],
1855 			 RX_MACRO_PORTS_MAX) {
1856 			mask |= (1 << temp);
1857 			if (++cnt == RX_MACRO_MAX_DMA_CH_PER_PORT)
1858 				break;
1859 		}
1860 		/*
1861 		 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3
1862 		 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3
1863 		 * CDC_DMA_RX_2 port drives RX4     -- ch_mask 0x1
1864 		 * CDC_DMA_RX_3 port drives RX5     -- ch_mask 0x1
1865 		 * AIFn can pair to any CDC_DMA_RX_n port.
1866 		 * In general, below convention is used::
1867 		 * CDC_DMA_RX_0(AIF1)/CDC_DMA_RX_1(AIF2)/
1868 		 * CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4)
1869 		 */
1870 		if (mask & 0x0C)
1871 			mask = mask >> 2;
1872 		if ((mask & 0x10) || (mask & 0x20))
1873 			mask = 0x1;
1874 		*rx_slot = mask;
1875 		*rx_num = rx->active_ch_cnt[dai->id];
1876 		break;
1877 	case RX_MACRO_AIF_ECHO:
1878 		val = snd_soc_component_read(component,	CDC_RX_INP_MUX_RX_MIX_CFG4);
1879 		if (val & RX_MACRO_EC_MIX_TX0_MASK) {
1880 			mask |= 0x1;
1881 			cnt++;
1882 		}
1883 		if (val & RX_MACRO_EC_MIX_TX1_MASK) {
1884 			mask |= 0x2;
1885 			cnt++;
1886 		}
1887 		val = snd_soc_component_read(component,
1888 			CDC_RX_INP_MUX_RX_MIX_CFG5);
1889 		if (val & RX_MACRO_EC_MIX_TX2_MASK) {
1890 			mask |= 0x4;
1891 			cnt++;
1892 		}
1893 		*tx_slot = mask;
1894 		*tx_num = cnt;
1895 		break;
1896 	default:
1897 		dev_err(component->dev, "%s: Invalid AIF\n", __func__);
1898 		break;
1899 	}
1900 	return 0;
1901 }
1902 
rx_macro_digital_mute(struct snd_soc_dai * dai,int mute,int stream)1903 static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1904 {
1905 	struct snd_soc_component *component = dai->component;
1906 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1907 	uint16_t j, reg, mix_reg, dsm_reg;
1908 	u16 int_mux_cfg0, int_mux_cfg1;
1909 	u8 int_mux_cfg0_val, int_mux_cfg1_val;
1910 
1911 	switch (dai->id) {
1912 	case RX_MACRO_AIF1_PB:
1913 	case RX_MACRO_AIF2_PB:
1914 	case RX_MACRO_AIF3_PB:
1915 	case RX_MACRO_AIF4_PB:
1916 		for (j = 0; j < INTERP_MAX; j++) {
1917 			reg = CDC_RX_RXn_RX_PATH_CTL(rx, j);
1918 			mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j);
1919 			dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, j);
1920 
1921 			if (mute) {
1922 				snd_soc_component_update_bits(component, reg,
1923 							      CDC_RX_PATH_PGA_MUTE_MASK,
1924 							      CDC_RX_PATH_PGA_MUTE_ENABLE);
1925 				snd_soc_component_update_bits(component, mix_reg,
1926 							      CDC_RX_PATH_PGA_MUTE_MASK,
1927 							      CDC_RX_PATH_PGA_MUTE_ENABLE);
1928 			} else {
1929 				snd_soc_component_update_bits(component, reg,
1930 							      CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1931 				snd_soc_component_update_bits(component, mix_reg,
1932 							      CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1933 			}
1934 
1935 			int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
1936 			int_mux_cfg1 = int_mux_cfg0 + 4;
1937 			int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
1938 			int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
1939 
1940 			if (snd_soc_component_read(component, dsm_reg) & 0x01) {
1941 				if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0))
1942 					snd_soc_component_update_bits(component, reg, 0x20, 0x20);
1943 				if (int_mux_cfg1_val & 0x0F) {
1944 					snd_soc_component_update_bits(component, reg, 0x20, 0x20);
1945 					snd_soc_component_update_bits(component, mix_reg, 0x20,
1946 								      0x20);
1947 				}
1948 			}
1949 		}
1950 		break;
1951 	default:
1952 		break;
1953 	}
1954 	return 0;
1955 }
1956 
1957 static const struct snd_soc_dai_ops rx_macro_dai_ops = {
1958 	.hw_params = rx_macro_hw_params,
1959 	.get_channel_map = rx_macro_get_channel_map,
1960 	.mute_stream = rx_macro_digital_mute,
1961 };
1962 
1963 static struct snd_soc_dai_driver rx_macro_dai[] = {
1964 	{
1965 		.name = "rx_macro_rx1",
1966 		.id = RX_MACRO_AIF1_PB,
1967 		.playback = {
1968 			.stream_name = "RX_MACRO_AIF1 Playback",
1969 			.rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1970 			.formats = RX_MACRO_FORMATS,
1971 			.rate_max = 384000,
1972 			.rate_min = 8000,
1973 			.channels_min = 1,
1974 			.channels_max = 2,
1975 		},
1976 		.ops = &rx_macro_dai_ops,
1977 	},
1978 	{
1979 		.name = "rx_macro_rx2",
1980 		.id = RX_MACRO_AIF2_PB,
1981 		.playback = {
1982 			.stream_name = "RX_MACRO_AIF2 Playback",
1983 			.rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1984 			.formats = RX_MACRO_FORMATS,
1985 			.rate_max = 384000,
1986 			.rate_min = 8000,
1987 			.channels_min = 1,
1988 			.channels_max = 2,
1989 		},
1990 		.ops = &rx_macro_dai_ops,
1991 	},
1992 	{
1993 		.name = "rx_macro_rx3",
1994 		.id = RX_MACRO_AIF3_PB,
1995 		.playback = {
1996 			.stream_name = "RX_MACRO_AIF3 Playback",
1997 			.rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1998 			.formats = RX_MACRO_FORMATS,
1999 			.rate_max = 384000,
2000 			.rate_min = 8000,
2001 			.channels_min = 1,
2002 			.channels_max = 2,
2003 		},
2004 		.ops = &rx_macro_dai_ops,
2005 	},
2006 	{
2007 		.name = "rx_macro_rx4",
2008 		.id = RX_MACRO_AIF4_PB,
2009 		.playback = {
2010 			.stream_name = "RX_MACRO_AIF4 Playback",
2011 			.rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
2012 			.formats = RX_MACRO_FORMATS,
2013 			.rate_max = 384000,
2014 			.rate_min = 8000,
2015 			.channels_min = 1,
2016 			.channels_max = 2,
2017 		},
2018 		.ops = &rx_macro_dai_ops,
2019 	},
2020 	{
2021 		.name = "rx_macro_echo",
2022 		.id = RX_MACRO_AIF_ECHO,
2023 		.capture = {
2024 			.stream_name = "RX_AIF_ECHO Capture",
2025 			.rates = RX_MACRO_ECHO_RATES,
2026 			.formats = RX_MACRO_ECHO_FORMATS,
2027 			.rate_max = 48000,
2028 			.rate_min = 8000,
2029 			.channels_min = 1,
2030 			.channels_max = 3,
2031 		},
2032 		.ops = &rx_macro_dai_ops,
2033 	},
2034 };
2035 
rx_macro_mclk_enable(struct rx_macro * rx,bool mclk_enable)2036 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable)
2037 {
2038 	struct regmap *regmap = rx->regmap;
2039 
2040 	if (mclk_enable) {
2041 		if (rx->rx_mclk_users == 0) {
2042 			regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
2043 					   CDC_RX_CLK_MCLK_EN_MASK |
2044 					   CDC_RX_CLK_MCLK2_EN_MASK,
2045 					   CDC_RX_CLK_MCLK_ENABLE |
2046 					   CDC_RX_CLK_MCLK2_ENABLE);
2047 			regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
2048 					   CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00);
2049 			regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
2050 					   CDC_RX_FS_MCLK_CNT_EN_MASK,
2051 					   CDC_RX_FS_MCLK_CNT_ENABLE);
2052 			regcache_mark_dirty(regmap);
2053 			regcache_sync(regmap);
2054 		}
2055 		rx->rx_mclk_users++;
2056 	} else {
2057 		if (rx->rx_mclk_users <= 0) {
2058 			dev_err(rx->dev, "%s: clock already disabled\n", __func__);
2059 			rx->rx_mclk_users = 0;
2060 			return;
2061 		}
2062 		rx->rx_mclk_users--;
2063 		if (rx->rx_mclk_users == 0) {
2064 			regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
2065 					   CDC_RX_FS_MCLK_CNT_EN_MASK, 0x0);
2066 			regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
2067 					   CDC_RX_FS_MCLK_CNT_CLR_MASK,
2068 					   CDC_RX_FS_MCLK_CNT_CLR);
2069 			regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
2070 					   CDC_RX_CLK_MCLK_EN_MASK |
2071 					   CDC_RX_CLK_MCLK2_EN_MASK, 0x0);
2072 		}
2073 	}
2074 }
2075 
rx_macro_mclk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2076 static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w,
2077 			       struct snd_kcontrol *kcontrol, int event)
2078 {
2079 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2080 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2081 	int ret = 0;
2082 
2083 	switch (event) {
2084 	case SND_SOC_DAPM_PRE_PMU:
2085 		rx_macro_mclk_enable(rx, true);
2086 		break;
2087 	case SND_SOC_DAPM_POST_PMD:
2088 		rx_macro_mclk_enable(rx, false);
2089 		break;
2090 	default:
2091 		dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event);
2092 		ret = -EINVAL;
2093 	}
2094 	return ret;
2095 }
2096 
rx_macro_adie_lb(struct snd_soc_component * component,int interp_idx)2097 static bool rx_macro_adie_lb(struct snd_soc_component *component,
2098 			     int interp_idx)
2099 {
2100 	u16 int_mux_cfg0, int_mux_cfg1;
2101 	u8 int_n_inp0, int_n_inp1, int_n_inp2;
2102 
2103 	int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
2104 	int_mux_cfg1 = int_mux_cfg0 + 4;
2105 
2106 	int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
2107 						  CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
2108 	int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
2109 						  CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
2110 	int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
2111 						  CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
2112 
2113 	if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
2114 		int_n_inp0 == INTn_1_INP_SEL_DEC1 ||
2115 		int_n_inp0 == INTn_1_INP_SEL_IIR0 ||
2116 		int_n_inp0 == INTn_1_INP_SEL_IIR1)
2117 		return true;
2118 
2119 	if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
2120 		int_n_inp1 == INTn_1_INP_SEL_DEC1 ||
2121 		int_n_inp1 == INTn_1_INP_SEL_IIR0 ||
2122 		int_n_inp1 == INTn_1_INP_SEL_IIR1)
2123 		return true;
2124 
2125 	if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
2126 		int_n_inp2 == INTn_1_INP_SEL_DEC1 ||
2127 		int_n_inp2 == INTn_1_INP_SEL_IIR0 ||
2128 		int_n_inp2 == INTn_1_INP_SEL_IIR1)
2129 		return true;
2130 
2131 	return false;
2132 }
2133 
2134 static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
2135 				      int event, int interp_idx);
rx_macro_enable_main_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2136 static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
2137 					struct snd_kcontrol *kcontrol,
2138 					int event)
2139 {
2140 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2141 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2142 	u16 gain_reg, reg;
2143 
2144 	reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift);
2145 	gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift);
2146 
2147 	switch (event) {
2148 	case SND_SOC_DAPM_PRE_PMU:
2149 		rx_macro_enable_interp_clk(component, event, w->shift);
2150 		if (rx_macro_adie_lb(component, w->shift))
2151 			snd_soc_component_update_bits(component, reg,
2152 						      CDC_RX_PATH_CLK_EN_MASK,
2153 						      CDC_RX_PATH_CLK_ENABLE);
2154 		break;
2155 	case SND_SOC_DAPM_POST_PMU:
2156 		snd_soc_component_write(component, gain_reg,
2157 			snd_soc_component_read(component, gain_reg));
2158 		break;
2159 	case SND_SOC_DAPM_POST_PMD:
2160 		rx_macro_enable_interp_clk(component, event, w->shift);
2161 		break;
2162 	}
2163 
2164 	return 0;
2165 }
2166 
rx_macro_config_compander(struct snd_soc_component * component,struct rx_macro * rx,int comp,int event)2167 static int rx_macro_config_compander(struct snd_soc_component *component,
2168 				struct rx_macro *rx,
2169 				int comp, int event)
2170 {
2171 	u8 pcm_rate, val;
2172 
2173 	/* AUX does not have compander */
2174 	if (comp == INTERP_AUX)
2175 		return 0;
2176 
2177 	pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(rx, comp)) & 0x0F;
2178 	if (pcm_rate < 0x06)
2179 		val = 0x03;
2180 	else if (pcm_rate < 0x08)
2181 		val = 0x01;
2182 	else if (pcm_rate < 0x0B)
2183 		val = 0x02;
2184 	else
2185 		val = 0x00;
2186 
2187 	if (SND_SOC_DAPM_EVENT_ON(event))
2188 		snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp),
2189 					      CDC_RX_DC_COEFF_SEL_MASK, val);
2190 
2191 	if (SND_SOC_DAPM_EVENT_OFF(event))
2192 		snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp),
2193 					      CDC_RX_DC_COEFF_SEL_MASK, 0x3);
2194 	if (!rx->comp_enabled[comp])
2195 		return 0;
2196 
2197 	if (SND_SOC_DAPM_EVENT_ON(event)) {
2198 		/* Enable Compander Clock */
2199 		snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2200 					      CDC_RX_COMPANDERn_CLK_EN_MASK, 0x1);
2201 		snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2202 					      CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1);
2203 		snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2204 					      CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0);
2205 		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp),
2206 					      CDC_RX_RXn_COMP_EN_MASK, 0x1);
2207 	}
2208 
2209 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
2210 		snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2211 					      CDC_RX_COMPANDERn_HALT_MASK, 0x1);
2212 		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp),
2213 					      CDC_RX_RXn_COMP_EN_MASK, 0x0);
2214 		snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2215 					      CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0);
2216 		snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2217 					      CDC_RX_COMPANDERn_HALT_MASK, 0x0);
2218 	}
2219 
2220 	return 0;
2221 }
2222 
rx_macro_load_compander_coeff(struct snd_soc_component * component,struct rx_macro * rx,int comp,int event)2223 static int rx_macro_load_compander_coeff(struct snd_soc_component *component,
2224 					 struct rx_macro *rx,
2225 					 int comp, int event)
2226 {
2227 	u16 comp_coeff_lsb_reg, comp_coeff_msb_reg;
2228 	int i;
2229 	int hph_pwr_mode;
2230 
2231 	/* AUX does not have compander */
2232 	if (comp == INTERP_AUX)
2233 		return 0;
2234 
2235 	if (!rx->comp_enabled[comp])
2236 		return 0;
2237 
2238 	if (comp == INTERP_HPHL) {
2239 		comp_coeff_lsb_reg = CDC_RX_TOP_HPHL_COMP_WR_LSB;
2240 		comp_coeff_msb_reg = CDC_RX_TOP_HPHL_COMP_WR_MSB;
2241 	} else if (comp == INTERP_HPHR) {
2242 		comp_coeff_lsb_reg = CDC_RX_TOP_HPHR_COMP_WR_LSB;
2243 		comp_coeff_msb_reg = CDC_RX_TOP_HPHR_COMP_WR_MSB;
2244 	} else {
2245 		/* compander coefficients are loaded only for hph path */
2246 		return 0;
2247 	}
2248 
2249 	hph_pwr_mode = rx->hph_pwr_mode;
2250 
2251 	if (SND_SOC_DAPM_EVENT_ON(event)) {
2252 		/* Load Compander Coeff */
2253 		for (i = 0; i < COMP_MAX_COEFF; i++) {
2254 			snd_soc_component_write(component, comp_coeff_lsb_reg,
2255 					comp_coeff_table[hph_pwr_mode][i].lsb);
2256 			snd_soc_component_write(component, comp_coeff_msb_reg,
2257 					comp_coeff_table[hph_pwr_mode][i].msb);
2258 		}
2259 	}
2260 
2261 	return 0;
2262 }
2263 
rx_macro_enable_softclip_clk(struct snd_soc_component * component,struct rx_macro * rx,bool enable)2264 static void rx_macro_enable_softclip_clk(struct snd_soc_component *component,
2265 					 struct rx_macro *rx, bool enable)
2266 {
2267 	if (enable) {
2268 		if (rx->softclip_clk_users == 0)
2269 			snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2270 						      CDC_RX_SOFTCLIP_CLK_EN_MASK, 1);
2271 		rx->softclip_clk_users++;
2272 	} else {
2273 		rx->softclip_clk_users--;
2274 		if (rx->softclip_clk_users == 0)
2275 			snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2276 						      CDC_RX_SOFTCLIP_CLK_EN_MASK, 0);
2277 	}
2278 }
2279 
rx_macro_config_softclip(struct snd_soc_component * component,struct rx_macro * rx,int event)2280 static int rx_macro_config_softclip(struct snd_soc_component *component,
2281 				    struct rx_macro *rx, int event)
2282 {
2283 
2284 	if (!rx->is_softclip_on)
2285 		return 0;
2286 
2287 	if (SND_SOC_DAPM_EVENT_ON(event)) {
2288 		/* Enable Softclip clock */
2289 		rx_macro_enable_softclip_clk(component, rx, true);
2290 		/* Enable Softclip control */
2291 		snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2292 					     CDC_RX_SOFTCLIP_EN_MASK, 0x01);
2293 	}
2294 
2295 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
2296 		snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2297 					     CDC_RX_SOFTCLIP_EN_MASK, 0x0);
2298 		rx_macro_enable_softclip_clk(component, rx, false);
2299 	}
2300 
2301 	return 0;
2302 }
2303 
rx_macro_config_aux_hpf(struct snd_soc_component * component,struct rx_macro * rx,int event)2304 static int rx_macro_config_aux_hpf(struct snd_soc_component *component,
2305 				   struct rx_macro *rx, int event)
2306 {
2307 	if (SND_SOC_DAPM_EVENT_ON(event)) {
2308 		/* Update Aux HPF control */
2309 		if (!rx->is_aux_hpf_on)
2310 			snd_soc_component_update_bits(component,
2311 				CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x00);
2312 	}
2313 
2314 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
2315 		/* Reset to default (HPF=ON) */
2316 		snd_soc_component_update_bits(component,
2317 			CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x04);
2318 	}
2319 
2320 	return 0;
2321 }
2322 
rx_macro_enable_clsh_block(struct rx_macro * rx,bool enable)2323 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable)
2324 {
2325 	if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0))
2326 		snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC,
2327 					     CDC_RX_CLSH_CLK_EN_MASK, enable);
2328 	if (rx->clsh_users < 0)
2329 		rx->clsh_users = 0;
2330 }
2331 
rx_macro_config_classh(struct snd_soc_component * component,struct rx_macro * rx,int interp_n,int event)2332 static int rx_macro_config_classh(struct snd_soc_component *component,
2333 				struct rx_macro *rx,
2334 				int interp_n, int event)
2335 {
2336 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
2337 		rx_macro_enable_clsh_block(rx, false);
2338 		return 0;
2339 	}
2340 
2341 	if (!SND_SOC_DAPM_EVENT_ON(event))
2342 		return 0;
2343 
2344 	rx_macro_enable_clsh_block(rx, true);
2345 	if (interp_n == INTERP_HPHL ||
2346 		interp_n == INTERP_HPHR) {
2347 		/*
2348 		 * These K1 values depend on the Headphone Impedance
2349 		 * For now it is assumed to be 16 ohm
2350 		 */
2351 		snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, 0xc0);
2352 		snd_soc_component_write_field(component, CDC_RX_CLSH_K1_MSB,
2353 					      CDC_RX_CLSH_K1_MSB_COEFF_MASK, 0);
2354 	}
2355 	switch (interp_n) {
2356 	case INTERP_HPHL:
2357 		if (rx->is_ear_mode_on)
2358 			snd_soc_component_update_bits(component,
2359 				CDC_RX_CLSH_HPH_V_PA,
2360 				CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
2361 		else
2362 			snd_soc_component_update_bits(component,
2363 				CDC_RX_CLSH_HPH_V_PA,
2364 				CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
2365 		snd_soc_component_update_bits(component,
2366 				CDC_RX_CLSH_DECAY_CTRL,
2367 				CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
2368 		snd_soc_component_write_field(component,
2369 				CDC_RX_RXn_RX_PATH_CFG0(rx, 0),
2370 				CDC_RX_RXn_CLSH_EN_MASK, 0x1);
2371 		break;
2372 	case INTERP_HPHR:
2373 		if (rx->is_ear_mode_on)
2374 			snd_soc_component_update_bits(component,
2375 				CDC_RX_CLSH_HPH_V_PA,
2376 				CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
2377 		else
2378 			snd_soc_component_update_bits(component,
2379 				CDC_RX_CLSH_HPH_V_PA,
2380 				CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
2381 		snd_soc_component_update_bits(component,
2382 				CDC_RX_CLSH_DECAY_CTRL,
2383 				CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
2384 		snd_soc_component_write_field(component,
2385 				CDC_RX_RXn_RX_PATH_CFG0(rx, 1),
2386 				CDC_RX_RXn_CLSH_EN_MASK, 0x1);
2387 		break;
2388 	case INTERP_AUX:
2389 		snd_soc_component_update_bits(component,
2390 				CDC_RX_RXn_RX_PATH_CFG0(rx, 2),
2391 				CDC_RX_RX2_DLY_Z_EN_MASK, 1);
2392 		snd_soc_component_write_field(component,
2393 				CDC_RX_RXn_RX_PATH_CFG0(rx, 2),
2394 				CDC_RX_RX2_CLSH_EN_MASK, 1);
2395 		break;
2396 	}
2397 
2398 	return 0;
2399 }
2400 
rx_macro_hd2_control(struct snd_soc_component * component,u16 interp_idx,int event)2401 static void rx_macro_hd2_control(struct snd_soc_component *component,
2402 				 u16 interp_idx, int event)
2403 {
2404 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2405 	u16 hd2_scale_reg, hd2_enable_reg;
2406 
2407 	switch (interp_idx) {
2408 	case INTERP_HPHL:
2409 		hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 0);
2410 		hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0);
2411 		break;
2412 	case INTERP_HPHR:
2413 		hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 1);
2414 		hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1);
2415 		break;
2416 	}
2417 
2418 	if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2419 		snd_soc_component_update_bits(component, hd2_scale_reg,
2420 				CDC_RX_RXn_HD2_ALPHA_MASK, 0x14);
2421 		snd_soc_component_write_field(component, hd2_enable_reg,
2422 					      CDC_RX_RXn_HD2_EN_MASK, 1);
2423 	}
2424 
2425 	if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2426 		snd_soc_component_write_field(component, hd2_enable_reg,
2427 					      CDC_RX_RXn_HD2_EN_MASK, 0);
2428 		snd_soc_component_update_bits(component, hd2_scale_reg,
2429 				CDC_RX_RXn_HD2_ALPHA_MASK, 0x0);
2430 	}
2431 }
2432 
rx_macro_get_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2433 static int rx_macro_get_compander(struct snd_kcontrol *kcontrol,
2434 			       struct snd_ctl_elem_value *ucontrol)
2435 {
2436 	struct snd_soc_component *component =
2437 				snd_soc_kcontrol_component(kcontrol);
2438 	int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2439 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2440 
2441 	ucontrol->value.integer.value[0] = rx->comp_enabled[comp];
2442 	return 0;
2443 }
2444 
rx_macro_set_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2445 static int rx_macro_set_compander(struct snd_kcontrol *kcontrol,
2446 			       struct snd_ctl_elem_value *ucontrol)
2447 {
2448 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2449 	int comp = ((struct soc_mixer_control *)  kcontrol->private_value)->shift;
2450 	int value = ucontrol->value.integer.value[0];
2451 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2452 
2453 	rx->comp_enabled[comp] = value;
2454 
2455 	return 0;
2456 }
2457 
rx_macro_mux_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2458 static int rx_macro_mux_get(struct snd_kcontrol *kcontrol,
2459 			  struct snd_ctl_elem_value *ucontrol)
2460 {
2461 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2462 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2463 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2464 
2465 	ucontrol->value.enumerated.item[0] =
2466 			rx->rx_port_value[widget->shift];
2467 	return 0;
2468 }
2469 
rx_macro_mux_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2470 static int rx_macro_mux_put(struct snd_kcontrol *kcontrol,
2471 			    struct snd_ctl_elem_value *ucontrol)
2472 {
2473 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2474 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2475 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2476 	struct snd_soc_dapm_update *update = NULL;
2477 	u32 rx_port_value = ucontrol->value.enumerated.item[0];
2478 	u32 aif_rst;
2479 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2480 
2481 	aif_rst = rx->rx_port_value[widget->shift];
2482 	if (!rx_port_value) {
2483 		if (aif_rst == 0)
2484 			return 0;
2485 		if (aif_rst > RX_MACRO_AIF4_PB) {
2486 			dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
2487 			return 0;
2488 		}
2489 	}
2490 	rx->rx_port_value[widget->shift] = rx_port_value;
2491 
2492 	switch (rx_port_value) {
2493 	case 0:
2494 		if (rx->active_ch_cnt[aif_rst]) {
2495 			clear_bit(widget->shift,
2496 				&rx->active_ch_mask[aif_rst]);
2497 			rx->active_ch_cnt[aif_rst]--;
2498 		}
2499 		break;
2500 	case 1:
2501 	case 2:
2502 	case 3:
2503 	case 4:
2504 		set_bit(widget->shift,
2505 			&rx->active_ch_mask[rx_port_value]);
2506 		rx->active_ch_cnt[rx_port_value]++;
2507 		break;
2508 	default:
2509 		dev_err(component->dev,
2510 			"%s:Invalid AIF_ID for RX_MACRO MUX %d\n",
2511 			__func__, rx_port_value);
2512 		goto err;
2513 	}
2514 
2515 	snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
2516 					rx_port_value, e, update);
2517 	return 0;
2518 err:
2519 	return -EINVAL;
2520 }
2521 
2522 static const struct snd_kcontrol_new rx_macro_rx0_mux =
2523 		SOC_DAPM_ENUM_EXT("rx_macro_rx0", rx_macro_rx0_enum,
2524 		  rx_macro_mux_get, rx_macro_mux_put);
2525 static const struct snd_kcontrol_new rx_macro_rx1_mux =
2526 		SOC_DAPM_ENUM_EXT("rx_macro_rx1", rx_macro_rx1_enum,
2527 		  rx_macro_mux_get, rx_macro_mux_put);
2528 static const struct snd_kcontrol_new rx_macro_rx2_mux =
2529 		SOC_DAPM_ENUM_EXT("rx_macro_rx2", rx_macro_rx2_enum,
2530 		  rx_macro_mux_get, rx_macro_mux_put);
2531 static const struct snd_kcontrol_new rx_macro_rx3_mux =
2532 		SOC_DAPM_ENUM_EXT("rx_macro_rx3", rx_macro_rx3_enum,
2533 		  rx_macro_mux_get, rx_macro_mux_put);
2534 static const struct snd_kcontrol_new rx_macro_rx4_mux =
2535 		SOC_DAPM_ENUM_EXT("rx_macro_rx4", rx_macro_rx4_enum,
2536 		  rx_macro_mux_get, rx_macro_mux_put);
2537 static const struct snd_kcontrol_new rx_macro_rx5_mux =
2538 		SOC_DAPM_ENUM_EXT("rx_macro_rx5", rx_macro_rx5_enum,
2539 		  rx_macro_mux_get, rx_macro_mux_put);
2540 
rx_macro_get_ear_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2541 static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol,
2542 			       struct snd_ctl_elem_value *ucontrol)
2543 {
2544 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2545 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2546 
2547 	ucontrol->value.integer.value[0] = rx->is_ear_mode_on;
2548 	return 0;
2549 }
2550 
rx_macro_put_ear_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2551 static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol,
2552 			       struct snd_ctl_elem_value *ucontrol)
2553 {
2554 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2555 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2556 
2557 	rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true);
2558 	return 0;
2559 }
2560 
rx_macro_get_hph_hd2_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2561 static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2562 			       struct snd_ctl_elem_value *ucontrol)
2563 {
2564 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2565 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2566 
2567 	ucontrol->value.integer.value[0] = rx->hph_hd2_mode;
2568 	return 0;
2569 }
2570 
rx_macro_put_hph_hd2_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2571 static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2572 			       struct snd_ctl_elem_value *ucontrol)
2573 {
2574 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2575 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2576 
2577 	rx->hph_hd2_mode = ucontrol->value.integer.value[0];
2578 	return 0;
2579 }
2580 
rx_macro_get_hph_pwr_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2581 static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2582 			       struct snd_ctl_elem_value *ucontrol)
2583 {
2584 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2585 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2586 
2587 	ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode;
2588 	return 0;
2589 }
2590 
rx_macro_put_hph_pwr_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2591 static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2592 			       struct snd_ctl_elem_value *ucontrol)
2593 {
2594 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2595 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2596 
2597 	rx->hph_pwr_mode = ucontrol->value.enumerated.item[0];
2598 	return 0;
2599 }
2600 
rx_macro_soft_clip_enable_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2601 static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
2602 					  struct snd_ctl_elem_value *ucontrol)
2603 {
2604 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2605 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2606 
2607 	ucontrol->value.integer.value[0] = rx->is_softclip_on;
2608 
2609 	return 0;
2610 }
2611 
rx_macro_soft_clip_enable_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2612 static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
2613 					  struct snd_ctl_elem_value *ucontrol)
2614 {
2615 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2616 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2617 
2618 	rx->is_softclip_on = ucontrol->value.integer.value[0];
2619 
2620 	return 0;
2621 }
2622 
rx_macro_aux_hpf_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2623 static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol,
2624 					  struct snd_ctl_elem_value *ucontrol)
2625 {
2626 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2627 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2628 
2629 	ucontrol->value.integer.value[0] = rx->is_aux_hpf_on;
2630 
2631 	return 0;
2632 }
2633 
rx_macro_aux_hpf_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2634 static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol,
2635 					  struct snd_ctl_elem_value *ucontrol)
2636 {
2637 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2638 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2639 
2640 	rx->is_aux_hpf_on = ucontrol->value.integer.value[0];
2641 
2642 	return 0;
2643 }
2644 
rx_macro_hphdelay_lutbypass(struct snd_soc_component * component,struct rx_macro * rx,u16 interp_idx,int event)2645 static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
2646 					struct rx_macro *rx,
2647 					u16 interp_idx, int event)
2648 {
2649 	u16 hph_lut_bypass_reg;
2650 	u16 hph_comp_ctrl7;
2651 
2652 	switch (interp_idx) {
2653 	case INTERP_HPHL:
2654 		hph_lut_bypass_reg = CDC_RX_TOP_HPHL_COMP_LUT;
2655 		hph_comp_ctrl7 = CDC_RX_COMPANDER0_CTL7;
2656 		break;
2657 	case INTERP_HPHR:
2658 		hph_lut_bypass_reg = CDC_RX_TOP_HPHR_COMP_LUT;
2659 		hph_comp_ctrl7 = CDC_RX_COMPANDER1_CTL7;
2660 		break;
2661 	default:
2662 		return -EINVAL;
2663 	}
2664 
2665 	if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2666 		if (interp_idx == INTERP_HPHL) {
2667 			if (rx->is_ear_mode_on)
2668 				snd_soc_component_write_field(component,
2669 					CDC_RX_RXn_RX_PATH_CFG1(rx, 0),
2670 					CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1);
2671 			else
2672 				snd_soc_component_write_field(component,
2673 					hph_lut_bypass_reg,
2674 					CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
2675 		} else {
2676 			snd_soc_component_write_field(component, hph_lut_bypass_reg,
2677 					CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
2678 		}
2679 		if (rx->hph_pwr_mode)
2680 			snd_soc_component_write_field(component, hph_comp_ctrl7,
2681 					CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x0);
2682 	}
2683 
2684 	if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2685 		snd_soc_component_write_field(component,
2686 					CDC_RX_RXn_RX_PATH_CFG1(rx, 0),
2687 					CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0);
2688 		snd_soc_component_update_bits(component, hph_lut_bypass_reg,
2689 					CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0);
2690 		snd_soc_component_write_field(component, hph_comp_ctrl7,
2691 					CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x1);
2692 	}
2693 
2694 	return 0;
2695 }
2696 
rx_macro_enable_interp_clk(struct snd_soc_component * component,int event,int interp_idx)2697 static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
2698 				      int event, int interp_idx)
2699 {
2700 	u16 main_reg, dsm_reg, rx_cfg2_reg;
2701 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2702 
2703 	main_reg = CDC_RX_RXn_RX_PATH_CTL(rx, interp_idx);
2704 	dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, interp_idx);
2705 	rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(rx, interp_idx);
2706 
2707 	if (SND_SOC_DAPM_EVENT_ON(event)) {
2708 		if (rx->main_clk_users[interp_idx] == 0) {
2709 			/* Main path PGA mute enable */
2710 			snd_soc_component_write_field(component, main_reg,
2711 						      CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
2712 			snd_soc_component_write_field(component, dsm_reg,
2713 						      CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1);
2714 			snd_soc_component_update_bits(component, rx_cfg2_reg,
2715 					CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03);
2716 			rx_macro_load_compander_coeff(component, rx, interp_idx, event);
2717 			if (rx->hph_hd2_mode)
2718 				rx_macro_hd2_control(component, interp_idx, event);
2719 			rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2720 			rx_macro_config_compander(component, rx, interp_idx, event);
2721 			if (interp_idx == INTERP_AUX) {
2722 				rx_macro_config_softclip(component, rx,	event);
2723 				rx_macro_config_aux_hpf(component, rx, event);
2724 			}
2725 			rx_macro_config_classh(component, rx, interp_idx, event);
2726 		}
2727 		rx->main_clk_users[interp_idx]++;
2728 	}
2729 
2730 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
2731 		rx->main_clk_users[interp_idx]--;
2732 		if (rx->main_clk_users[interp_idx] <= 0) {
2733 			rx->main_clk_users[interp_idx] = 0;
2734 			/* Main path PGA mute enable */
2735 			snd_soc_component_write_field(component, main_reg,
2736 						      CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
2737 			/* Clk Disable */
2738 			snd_soc_component_write_field(component, dsm_reg,
2739 						      CDC_RX_RXn_DSM_CLK_EN_MASK, 0);
2740 			snd_soc_component_write_field(component, main_reg,
2741 						      CDC_RX_PATH_CLK_EN_MASK, 0);
2742 			/* Reset enable and disable */
2743 			snd_soc_component_write_field(component, main_reg,
2744 						      CDC_RX_PATH_RESET_EN_MASK, 1);
2745 			snd_soc_component_write_field(component, main_reg,
2746 						      CDC_RX_PATH_RESET_EN_MASK, 0);
2747 			/* Reset rate to 48K*/
2748 			snd_soc_component_update_bits(component, main_reg,
2749 						      CDC_RX_PATH_PCM_RATE_MASK,
2750 						      0x04);
2751 			snd_soc_component_update_bits(component, rx_cfg2_reg,
2752 						      CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x00);
2753 			rx_macro_config_classh(component, rx, interp_idx, event);
2754 			rx_macro_config_compander(component, rx, interp_idx, event);
2755 			if (interp_idx ==  INTERP_AUX) {
2756 				rx_macro_config_softclip(component, rx,	event);
2757 				rx_macro_config_aux_hpf(component, rx, event);
2758 			}
2759 			rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2760 			if (rx->hph_hd2_mode)
2761 				rx_macro_hd2_control(component, interp_idx, event);
2762 		}
2763 	}
2764 
2765 	return rx->main_clk_users[interp_idx];
2766 }
2767 
rx_macro_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2768 static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
2769 				    struct snd_kcontrol *kcontrol, int event)
2770 {
2771 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2772 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2773 	u16 gain_reg, mix_reg;
2774 
2775 	gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift);
2776 	mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift);
2777 
2778 	switch (event) {
2779 	case SND_SOC_DAPM_PRE_PMU:
2780 		rx_macro_enable_interp_clk(component, event, w->shift);
2781 		break;
2782 	case SND_SOC_DAPM_POST_PMU:
2783 		snd_soc_component_write(component, gain_reg,
2784 					snd_soc_component_read(component, gain_reg));
2785 		break;
2786 	case SND_SOC_DAPM_POST_PMD:
2787 		/* Clk Disable */
2788 		snd_soc_component_update_bits(component, mix_reg,
2789 					      CDC_RX_RXn_MIX_CLK_EN_MASK, 0x00);
2790 		rx_macro_enable_interp_clk(component, event, w->shift);
2791 		/* Reset enable and disable */
2792 		snd_soc_component_update_bits(component, mix_reg,
2793 					      CDC_RX_RXn_MIX_RESET_MASK,
2794 					      CDC_RX_RXn_MIX_RESET);
2795 		snd_soc_component_update_bits(component, mix_reg,
2796 					      CDC_RX_RXn_MIX_RESET_MASK, 0x00);
2797 		break;
2798 	}
2799 
2800 	return 0;
2801 }
2802 
rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2803 static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w,
2804 				       struct snd_kcontrol *kcontrol, int event)
2805 {
2806 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2807 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2808 
2809 	switch (event) {
2810 	case SND_SOC_DAPM_PRE_PMU:
2811 		rx_macro_enable_interp_clk(component, event, w->shift);
2812 		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift),
2813 					      CDC_RX_RXn_SIDETONE_EN_MASK, 1);
2814 		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift),
2815 					      CDC_RX_PATH_CLK_EN_MASK, 1);
2816 		break;
2817 	case SND_SOC_DAPM_POST_PMD:
2818 		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift),
2819 					      CDC_RX_RXn_SIDETONE_EN_MASK, 0);
2820 		rx_macro_enable_interp_clk(component, event, w->shift);
2821 		break;
2822 	default:
2823 		break;
2824 	}
2825 	return 0;
2826 }
2827 
rx_macro_set_iir_gain(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2828 static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
2829 				 struct snd_kcontrol *kcontrol, int event)
2830 {
2831 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2832 
2833 	switch (event) {
2834 	case SND_SOC_DAPM_POST_PMU: /* fall through */
2835 	case SND_SOC_DAPM_PRE_PMD:
2836 		if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
2837 			snd_soc_component_write(component,
2838 				CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
2839 			snd_soc_component_read(component,
2840 				CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL));
2841 			snd_soc_component_write(component,
2842 				CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL,
2843 			snd_soc_component_read(component,
2844 				CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL));
2845 			snd_soc_component_write(component,
2846 				CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL,
2847 			snd_soc_component_read(component,
2848 				CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL));
2849 			snd_soc_component_write(component,
2850 				CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL,
2851 			snd_soc_component_read(component,
2852 				CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL));
2853 		} else {
2854 			snd_soc_component_write(component,
2855 				CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
2856 			snd_soc_component_read(component,
2857 				CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL));
2858 			snd_soc_component_write(component,
2859 				CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL,
2860 			snd_soc_component_read(component,
2861 				CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL));
2862 			snd_soc_component_write(component,
2863 				CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL,
2864 			snd_soc_component_read(component,
2865 				CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL));
2866 			snd_soc_component_write(component,
2867 				CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL,
2868 			snd_soc_component_read(component,
2869 				CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL));
2870 		}
2871 		break;
2872 	}
2873 	return 0;
2874 }
2875 
get_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,int coeff_idx)2876 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2877 				   int iir_idx, int band_idx, int coeff_idx)
2878 {
2879 	u32 value;
2880 	int reg, b2_reg;
2881 
2882 	/* Address does not automatically update if reading */
2883 	reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx;
2884 	b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx;
2885 
2886 	snd_soc_component_write(component, reg,
2887 				((band_idx * BAND_MAX + coeff_idx) *
2888 				 sizeof(uint32_t)) & 0x7F);
2889 
2890 	value = snd_soc_component_read(component, b2_reg);
2891 	snd_soc_component_write(component, reg,
2892 				((band_idx * BAND_MAX + coeff_idx)
2893 				 * sizeof(uint32_t) + 1) & 0x7F);
2894 
2895 	value |= (snd_soc_component_read(component, b2_reg) << 8);
2896 	snd_soc_component_write(component, reg,
2897 				((band_idx * BAND_MAX + coeff_idx)
2898 				 * sizeof(uint32_t) + 2) & 0x7F);
2899 
2900 	value |= (snd_soc_component_read(component, b2_reg) << 16);
2901 	snd_soc_component_write(component, reg,
2902 		((band_idx * BAND_MAX + coeff_idx)
2903 		* sizeof(uint32_t) + 3) & 0x7F);
2904 
2905 	/* Mask bits top 2 bits since they are reserved */
2906 	value |= (snd_soc_component_read(component, b2_reg) << 24);
2907 	return value;
2908 }
2909 
set_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,uint32_t value)2910 static void set_iir_band_coeff(struct snd_soc_component *component,
2911 			       int iir_idx, int band_idx, uint32_t value)
2912 {
2913 	int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx;
2914 
2915 	snd_soc_component_write(component, reg, (value & 0xFF));
2916 	snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
2917 	snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
2918 	/* Mask top 2 bits, 7-8 are reserved */
2919 	snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
2920 }
2921 
rx_macro_put_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2922 static int rx_macro_put_iir_band_audio_mixer(
2923 					struct snd_kcontrol *kcontrol,
2924 					struct snd_ctl_elem_value *ucontrol)
2925 {
2926 	struct snd_soc_component *component =
2927 			snd_soc_kcontrol_component(kcontrol);
2928 	struct wcd_iir_filter_ctl *ctl =
2929 			(struct wcd_iir_filter_ctl *)kcontrol->private_value;
2930 	struct soc_bytes_ext *params = &ctl->bytes_ext;
2931 	int iir_idx = ctl->iir_idx;
2932 	int band_idx = ctl->band_idx;
2933 	u32 coeff[BAND_MAX];
2934 	int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx;
2935 
2936 	memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2937 
2938 	/* Mask top bit it is reserved */
2939 	/* Updates addr automatically for each B2 write */
2940 	snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
2941 						 sizeof(uint32_t)) & 0x7F);
2942 
2943 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
2944 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
2945 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
2946 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
2947 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
2948 
2949 	return 0;
2950 }
2951 
rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2952 static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2953 				    struct snd_ctl_elem_value *ucontrol)
2954 {
2955 	struct snd_soc_component *component =
2956 			snd_soc_kcontrol_component(kcontrol);
2957 	struct wcd_iir_filter_ctl *ctl =
2958 			(struct wcd_iir_filter_ctl *)kcontrol->private_value;
2959 	struct soc_bytes_ext *params = &ctl->bytes_ext;
2960 	int iir_idx = ctl->iir_idx;
2961 	int band_idx = ctl->band_idx;
2962 	u32 coeff[BAND_MAX];
2963 
2964 	coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
2965 	coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
2966 	coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
2967 	coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
2968 	coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
2969 
2970 	memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2971 
2972 	return 0;
2973 }
2974 
rx_macro_iir_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * ucontrol)2975 static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
2976 				   struct snd_ctl_elem_info *ucontrol)
2977 {
2978 	struct wcd_iir_filter_ctl *ctl =
2979 		(struct wcd_iir_filter_ctl *)kcontrol->private_value;
2980 	struct soc_bytes_ext *params = &ctl->bytes_ext;
2981 
2982 	ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2983 	ucontrol->count = params->max;
2984 
2985 	return 0;
2986 }
2987 
2988 static const struct snd_kcontrol_new rx_macro_def_snd_controls[] = {
2989 	SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL,
2990 			  -84, 40, digital_gain),
2991 	SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL,
2992 			  -84, 40, digital_gain),
2993 	SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL,
2994 			  -84, 40, digital_gain),
2995 	SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL,
2996 			  -84, 40, digital_gain),
2997 };
2998 
2999 static const struct snd_kcontrol_new rx_macro_2_5_snd_controls[] = {
3000 
3001 	SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_2_5_RX_RX1_RX_VOL_CTL,
3002 			  -84, 40, digital_gain),
3003 	SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_2_5_RX_RX2_RX_VOL_CTL,
3004 			  -84, 40, digital_gain),
3005 	SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_2_5_RX_RX1_RX_VOL_MIX_CTL,
3006 			  -84, 40, digital_gain),
3007 	SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_2_5_RX_RX2_RX_VOL_MIX_CTL,
3008 			  -84, 40, digital_gain),
3009 };
3010 
3011 static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
3012 	SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
3013 			  -84, 40, digital_gain),
3014 	SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
3015 			  -84, 40, digital_gain),
3016 	SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0,
3017 		rx_macro_get_compander, rx_macro_set_compander),
3018 	SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0,
3019 		rx_macro_get_compander, rx_macro_set_compander),
3020 
3021 	SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0,
3022 		rx_macro_get_ear_mode, rx_macro_put_ear_mode),
3023 
3024 	SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0,
3025 		rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode),
3026 
3027 	SOC_ENUM_EXT("RX_HPH PWR Mode", rx_macro_hph_pwr_mode_enum,
3028 		rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode),
3029 
3030 	SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0,
3031 		     rx_macro_soft_clip_enable_get,
3032 		     rx_macro_soft_clip_enable_put),
3033 	SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0,
3034 			rx_macro_aux_hpf_mode_get,
3035 			rx_macro_aux_hpf_mode_put),
3036 
3037 	SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
3038 		CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3039 		digital_gain),
3040 	SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
3041 		CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3042 		digital_gain),
3043 	SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
3044 		CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3045 		digital_gain),
3046 	SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
3047 		CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3048 		digital_gain),
3049 	SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
3050 		CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3051 		digital_gain),
3052 	SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
3053 		CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3054 		digital_gain),
3055 	SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
3056 		CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3057 		digital_gain),
3058 	SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
3059 		CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3060 		digital_gain),
3061 
3062 	SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
3063 		   0, 1, 0),
3064 	SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
3065 		   1, 1, 0),
3066 	SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
3067 		   2, 1, 0),
3068 	SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
3069 		   3, 1, 0),
3070 	SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
3071 		   4, 1, 0),
3072 	SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
3073 		   0, 1, 0),
3074 	SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
3075 		   1, 1, 0),
3076 	SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
3077 		   2, 1, 0),
3078 	SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
3079 		   3, 1, 0),
3080 	SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
3081 		   4, 1, 0),
3082 
3083 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
3084 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
3085 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
3086 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
3087 	RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
3088 
3089 	RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
3090 	RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
3091 	RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
3092 	RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
3093 	RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
3094 
3095 };
3096 
rx_macro_enable_echo(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3097 static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
3098 				struct snd_kcontrol *kcontrol,
3099 				int event)
3100 {
3101 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3102 	u16 val, ec_hq_reg;
3103 	int ec_tx = -1;
3104 
3105 	val = snd_soc_component_read(component,
3106 			CDC_RX_INP_MUX_RX_MIX_CFG4);
3107 	if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX0 MUX")))
3108 		ec_tx = ((val & 0xf0) >> 0x4) - 1;
3109 	else if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX1 MUX")))
3110 		ec_tx = (val & 0x0f) - 1;
3111 
3112 	val = snd_soc_component_read(component,
3113 			CDC_RX_INP_MUX_RX_MIX_CFG5);
3114 	if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX2 MUX")))
3115 		ec_tx = (val & 0x0f) - 1;
3116 
3117 	if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) {
3118 		dev_err(component->dev, "%s: EC mix control not set correctly\n",
3119 			__func__);
3120 		return -EINVAL;
3121 	}
3122 	ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL +
3123 			    0x40 * ec_tx;
3124 	snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01);
3125 	ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 +
3126 				0x40 * ec_tx;
3127 	/* default set to 48k */
3128 	snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08);
3129 
3130 	return 0;
3131 }
3132 
3133 static const struct snd_soc_dapm_widget rx_macro_2_5_dapm_widgets[] = {
3134 	SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3135 			 &rx_2_5_int1_dem_inp_mux),
3136 };
3137 
3138 static const struct snd_soc_dapm_widget rx_macro_def_dapm_widgets[] = {
3139 	SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3140 			 &rx_int1_dem_inp_mux),
3141 };
3142 
3143 static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
3144 	SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
3145 		SND_SOC_NOPM, 0, 0),
3146 
3147 	SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
3148 		SND_SOC_NOPM, 0, 0),
3149 
3150 	SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
3151 		SND_SOC_NOPM, 0, 0),
3152 
3153 	SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
3154 		SND_SOC_NOPM, 0, 0),
3155 
3156 	SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
3157 		SND_SOC_NOPM, 0, 0),
3158 
3159 	SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0,
3160 			 &rx_macro_rx0_mux),
3161 	SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0,
3162 			 &rx_macro_rx1_mux),
3163 	SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0,
3164 			 &rx_macro_rx2_mux),
3165 	SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0,
3166 			 &rx_macro_rx3_mux),
3167 	SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0,
3168 			 &rx_macro_rx4_mux),
3169 	SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0,
3170 			 &rx_macro_rx5_mux),
3171 
3172 	SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
3173 	SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3174 	SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3175 	SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
3176 	SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
3177 	SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
3178 
3179 	SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
3180 	SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
3181 	SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
3182 	SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
3183 	SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
3184 	SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
3185 	SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
3186 	SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
3187 
3188 	SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
3189 			   RX_MACRO_EC0_MUX, 0,
3190 			   &rx_mix_tx0_mux, rx_macro_enable_echo,
3191 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3192 	SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
3193 			   RX_MACRO_EC1_MUX, 0,
3194 			   &rx_mix_tx1_mux, rx_macro_enable_echo,
3195 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3196 	SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
3197 			   RX_MACRO_EC2_MUX, 0,
3198 			   &rx_mix_tx2_mux, rx_macro_enable_echo,
3199 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3200 
3201 	SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL,
3202 		4, 0, NULL, 0, rx_macro_set_iir_gain,
3203 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3204 	SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL,
3205 		4, 0, NULL, 0, rx_macro_set_iir_gain,
3206 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3207 	SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL,
3208 		4, 0, NULL, 0),
3209 	SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
3210 		4, 0, NULL, 0),
3211 
3212 	SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
3213 			 &rx_int0_dem_inp_mux),
3214 
3215 	SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3216 		&rx_int0_2_mux, rx_macro_enable_mix_path,
3217 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3218 		SND_SOC_DAPM_POST_PMD),
3219 	SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3220 		&rx_int1_2_mux, rx_macro_enable_mix_path,
3221 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3222 		SND_SOC_DAPM_POST_PMD),
3223 	SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3224 		&rx_int2_2_mux, rx_macro_enable_mix_path,
3225 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3226 		SND_SOC_DAPM_POST_PMD),
3227 
3228 	SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3229 	SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3230 	SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3231 	SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3232 	SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3233 	SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3234 	SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3235 	SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3236 	SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3237 
3238 	SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3239 		&rx_int0_1_interp_mux, rx_macro_enable_main_path,
3240 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3241 		SND_SOC_DAPM_POST_PMD),
3242 	SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3243 		&rx_int1_1_interp_mux, rx_macro_enable_main_path,
3244 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3245 		SND_SOC_DAPM_POST_PMD),
3246 	SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3247 		&rx_int2_1_interp_mux, rx_macro_enable_main_path,
3248 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3249 		SND_SOC_DAPM_POST_PMD),
3250 
3251 	SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3252 			 &rx_int0_2_interp_mux),
3253 	SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3254 			 &rx_int1_2_interp_mux),
3255 	SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3256 			 &rx_int2_2_interp_mux),
3257 
3258 	SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3259 	SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3260 	SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3261 	SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3262 	SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3263 	SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3264 
3265 	SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
3266 		0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3267 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3268 	SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
3269 		0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3270 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3271 	SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
3272 		0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3273 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3274 
3275 	SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3276 	SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3277 	SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3278 
3279 	SND_SOC_DAPM_OUTPUT("HPHL_OUT"),
3280 	SND_SOC_DAPM_OUTPUT("HPHR_OUT"),
3281 	SND_SOC_DAPM_OUTPUT("AUX_OUT"),
3282 
3283 	SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"),
3284 	SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"),
3285 	SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"),
3286 	SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"),
3287 
3288 	SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0,
3289 	rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3290 };
3291 
3292 static const struct snd_soc_dapm_route rx_audio_map[] = {
3293 	{"RX AIF1 PB", NULL, "RX_MCLK"},
3294 	{"RX AIF2 PB", NULL, "RX_MCLK"},
3295 	{"RX AIF3 PB", NULL, "RX_MCLK"},
3296 	{"RX AIF4 PB", NULL, "RX_MCLK"},
3297 
3298 	{"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
3299 	{"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
3300 	{"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
3301 	{"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
3302 	{"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
3303 	{"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
3304 
3305 	{"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
3306 	{"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
3307 	{"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
3308 	{"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
3309 	{"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
3310 	{"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
3311 
3312 	{"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3313 	{"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3314 	{"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3315 	{"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3316 	{"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3317 	{"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3318 
3319 	{"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
3320 	{"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
3321 	{"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
3322 	{"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
3323 	{"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
3324 	{"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
3325 
3326 	{"RX_RX0", NULL, "RX_MACRO RX0 MUX"},
3327 	{"RX_RX1", NULL, "RX_MACRO RX1 MUX"},
3328 	{"RX_RX2", NULL, "RX_MACRO RX2 MUX"},
3329 	{"RX_RX3", NULL, "RX_MACRO RX3 MUX"},
3330 	{"RX_RX4", NULL, "RX_MACRO RX4 MUX"},
3331 	{"RX_RX5", NULL, "RX_MACRO RX5 MUX"},
3332 
3333 	{"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
3334 	{"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
3335 	{"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
3336 	{"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
3337 	{"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
3338 	{"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
3339 	{"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3340 	{"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
3341 	{"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3342 	{"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3343 	{"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
3344 	{"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
3345 	{"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
3346 	{"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
3347 	{"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
3348 	{"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
3349 	{"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3350 	{"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
3351 	{"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3352 	{"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3353 	{"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
3354 	{"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
3355 	{"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
3356 	{"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
3357 	{"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
3358 	{"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
3359 	{"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3360 	{"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
3361 	{"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3362 	{"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3363 
3364 	{"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
3365 	{"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
3366 	{"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
3367 	{"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
3368 	{"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
3369 	{"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
3370 	{"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3371 	{"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
3372 	{"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3373 	{"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3374 	{"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
3375 	{"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
3376 	{"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
3377 	{"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
3378 	{"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
3379 	{"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
3380 	{"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3381 	{"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
3382 	{"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3383 	{"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3384 	{"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
3385 	{"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
3386 	{"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
3387 	{"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
3388 	{"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
3389 	{"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
3390 	{"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3391 	{"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
3392 	{"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3393 	{"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3394 
3395 	{"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
3396 	{"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
3397 	{"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
3398 	{"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
3399 	{"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
3400 	{"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
3401 	{"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3402 	{"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
3403 	{"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3404 	{"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3405 	{"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
3406 	{"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
3407 	{"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
3408 	{"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
3409 	{"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
3410 	{"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
3411 	{"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3412 	{"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
3413 	{"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3414 	{"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3415 	{"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
3416 	{"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
3417 	{"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
3418 	{"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
3419 	{"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
3420 	{"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
3421 	{"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3422 	{"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
3423 	{"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3424 	{"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3425 
3426 	{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
3427 	{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
3428 	{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
3429 	{"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
3430 	{"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
3431 	{"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
3432 	{"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
3433 	{"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
3434 	{"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
3435 
3436 	{"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3437 	{"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3438 	{"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3439 	{"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3440 	{"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3441 	{"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3442 	{"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3443 	{"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3444 	{"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3445 	{"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
3446 	{"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
3447 	{"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
3448 	{"RX AIF_ECHO", NULL, "RX_MCLK"},
3449 
3450 	/* Mixing path INT0 */
3451 	{"RX INT0_2 MUX", "RX0", "RX_RX0"},
3452 	{"RX INT0_2 MUX", "RX1", "RX_RX1"},
3453 	{"RX INT0_2 MUX", "RX2", "RX_RX2"},
3454 	{"RX INT0_2 MUX", "RX3", "RX_RX3"},
3455 	{"RX INT0_2 MUX", "RX4", "RX_RX4"},
3456 	{"RX INT0_2 MUX", "RX5", "RX_RX5"},
3457 	{"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
3458 	{"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
3459 
3460 	/* Mixing path INT1 */
3461 	{"RX INT1_2 MUX", "RX0", "RX_RX0"},
3462 	{"RX INT1_2 MUX", "RX1", "RX_RX1"},
3463 	{"RX INT1_2 MUX", "RX2", "RX_RX2"},
3464 	{"RX INT1_2 MUX", "RX3", "RX_RX3"},
3465 	{"RX INT1_2 MUX", "RX4", "RX_RX4"},
3466 	{"RX INT1_2 MUX", "RX5", "RX_RX5"},
3467 	{"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
3468 	{"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
3469 
3470 	/* Mixing path INT2 */
3471 	{"RX INT2_2 MUX", "RX0", "RX_RX0"},
3472 	{"RX INT2_2 MUX", "RX1", "RX_RX1"},
3473 	{"RX INT2_2 MUX", "RX2", "RX_RX2"},
3474 	{"RX INT2_2 MUX", "RX3", "RX_RX3"},
3475 	{"RX INT2_2 MUX", "RX4", "RX_RX4"},
3476 	{"RX INT2_2 MUX", "RX5", "RX_RX5"},
3477 	{"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
3478 	{"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
3479 
3480 	{"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
3481 	{"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
3482 	{"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
3483 	{"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
3484 	{"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
3485 	{"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
3486 	{"HPHL_OUT", NULL, "RX_MCLK"},
3487 
3488 	{"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
3489 	{"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
3490 	{"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
3491 	{"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
3492 	{"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
3493 	{"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
3494 	{"HPHR_OUT", NULL, "RX_MCLK"},
3495 
3496 	{"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
3497 
3498 	{"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
3499 	{"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
3500 	{"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
3501 	{"AUX_OUT", NULL, "RX INT2 MIX2"},
3502 	{"AUX_OUT", NULL, "RX_MCLK"},
3503 
3504 	{"IIR0", NULL, "RX_MCLK"},
3505 	{"IIR0", NULL, "IIR0 INP0 MUX"},
3506 	{"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3507 	{"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3508 	{"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3509 	{"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3510 	{"IIR0 INP0 MUX", "RX0", "RX_RX0"},
3511 	{"IIR0 INP0 MUX", "RX1", "RX_RX1"},
3512 	{"IIR0 INP0 MUX", "RX2", "RX_RX2"},
3513 	{"IIR0 INP0 MUX", "RX3", "RX_RX3"},
3514 	{"IIR0 INP0 MUX", "RX4", "RX_RX4"},
3515 	{"IIR0 INP0 MUX", "RX5", "RX_RX5"},
3516 	{"IIR0", NULL, "IIR0 INP1 MUX"},
3517 	{"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3518 	{"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3519 	{"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3520 	{"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3521 	{"IIR0 INP1 MUX", "RX0", "RX_RX0"},
3522 	{"IIR0 INP1 MUX", "RX1", "RX_RX1"},
3523 	{"IIR0 INP1 MUX", "RX2", "RX_RX2"},
3524 	{"IIR0 INP1 MUX", "RX3", "RX_RX3"},
3525 	{"IIR0 INP1 MUX", "RX4", "RX_RX4"},
3526 	{"IIR0 INP1 MUX", "RX5", "RX_RX5"},
3527 	{"IIR0", NULL, "IIR0 INP2 MUX"},
3528 	{"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3529 	{"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3530 	{"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3531 	{"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3532 	{"IIR0 INP2 MUX", "RX0", "RX_RX0"},
3533 	{"IIR0 INP2 MUX", "RX1", "RX_RX1"},
3534 	{"IIR0 INP2 MUX", "RX2", "RX_RX2"},
3535 	{"IIR0 INP2 MUX", "RX3", "RX_RX3"},
3536 	{"IIR0 INP2 MUX", "RX4", "RX_RX4"},
3537 	{"IIR0 INP2 MUX", "RX5", "RX_RX5"},
3538 	{"IIR0", NULL, "IIR0 INP3 MUX"},
3539 	{"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3540 	{"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3541 	{"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3542 	{"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3543 	{"IIR0 INP3 MUX", "RX0", "RX_RX0"},
3544 	{"IIR0 INP3 MUX", "RX1", "RX_RX1"},
3545 	{"IIR0 INP3 MUX", "RX2", "RX_RX2"},
3546 	{"IIR0 INP3 MUX", "RX3", "RX_RX3"},
3547 	{"IIR0 INP3 MUX", "RX4", "RX_RX4"},
3548 	{"IIR0 INP3 MUX", "RX5", "RX_RX5"},
3549 
3550 	{"IIR1", NULL, "RX_MCLK"},
3551 	{"IIR1", NULL, "IIR1 INP0 MUX"},
3552 	{"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3553 	{"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3554 	{"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3555 	{"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3556 	{"IIR1 INP0 MUX", "RX0", "RX_RX0"},
3557 	{"IIR1 INP0 MUX", "RX1", "RX_RX1"},
3558 	{"IIR1 INP0 MUX", "RX2", "RX_RX2"},
3559 	{"IIR1 INP0 MUX", "RX3", "RX_RX3"},
3560 	{"IIR1 INP0 MUX", "RX4", "RX_RX4"},
3561 	{"IIR1 INP0 MUX", "RX5", "RX_RX5"},
3562 	{"IIR1", NULL, "IIR1 INP1 MUX"},
3563 	{"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3564 	{"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3565 	{"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3566 	{"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3567 	{"IIR1 INP1 MUX", "RX0", "RX_RX0"},
3568 	{"IIR1 INP1 MUX", "RX1", "RX_RX1"},
3569 	{"IIR1 INP1 MUX", "RX2", "RX_RX2"},
3570 	{"IIR1 INP1 MUX", "RX3", "RX_RX3"},
3571 	{"IIR1 INP1 MUX", "RX4", "RX_RX4"},
3572 	{"IIR1 INP1 MUX", "RX5", "RX_RX5"},
3573 	{"IIR1", NULL, "IIR1 INP2 MUX"},
3574 	{"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3575 	{"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3576 	{"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3577 	{"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3578 	{"IIR1 INP2 MUX", "RX0", "RX_RX0"},
3579 	{"IIR1 INP2 MUX", "RX1", "RX_RX1"},
3580 	{"IIR1 INP2 MUX", "RX2", "RX_RX2"},
3581 	{"IIR1 INP2 MUX", "RX3", "RX_RX3"},
3582 	{"IIR1 INP2 MUX", "RX4", "RX_RX4"},
3583 	{"IIR1 INP2 MUX", "RX5", "RX_RX5"},
3584 	{"IIR1", NULL, "IIR1 INP3 MUX"},
3585 	{"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3586 	{"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3587 	{"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3588 	{"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3589 	{"IIR1 INP3 MUX", "RX0", "RX_RX0"},
3590 	{"IIR1 INP3 MUX", "RX1", "RX_RX1"},
3591 	{"IIR1 INP3 MUX", "RX2", "RX_RX2"},
3592 	{"IIR1 INP3 MUX", "RX3", "RX_RX3"},
3593 	{"IIR1 INP3 MUX", "RX4", "RX_RX4"},
3594 	{"IIR1 INP3 MUX", "RX5", "RX_RX5"},
3595 
3596 	{"SRC0", NULL, "IIR0"},
3597 	{"SRC1", NULL, "IIR1"},
3598 	{"RX INT0 MIX2 INP", "SRC0", "SRC0"},
3599 	{"RX INT0 MIX2 INP", "SRC1", "SRC1"},
3600 	{"RX INT1 MIX2 INP", "SRC0", "SRC0"},
3601 	{"RX INT1 MIX2 INP", "SRC1", "SRC1"},
3602 	{"RX INT2 MIX2 INP", "SRC0", "SRC0"},
3603 	{"RX INT2 MIX2 INP", "SRC1", "SRC1"},
3604 };
3605 
rx_macro_component_probe(struct snd_soc_component * component)3606 static int rx_macro_component_probe(struct snd_soc_component *component)
3607 {
3608 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3609 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
3610 	const struct snd_soc_dapm_widget *widgets;
3611 	const struct snd_kcontrol_new *controls;
3612 	unsigned int num_controls, num_widgets;
3613 	int ret;
3614 
3615 	snd_soc_component_init_regmap(component, rx->regmap);
3616 
3617 	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 0),
3618 				      CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3619 				      CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3620 	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 1),
3621 				      CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3622 				      CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3623 	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 2),
3624 				      CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3625 				      CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3626 	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 0),
3627 				      CDC_RX_DC_COEFF_SEL_MASK,
3628 				      CDC_RX_DC_COEFF_SEL_TWO);
3629 	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 1),
3630 				      CDC_RX_DC_COEFF_SEL_MASK,
3631 				      CDC_RX_DC_COEFF_SEL_TWO);
3632 	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 2),
3633 				      CDC_RX_DC_COEFF_SEL_MASK,
3634 				      CDC_RX_DC_COEFF_SEL_TWO);
3635 
3636 	switch (rx->codec_version) {
3637 	case LPASS_CODEC_VERSION_1_0:
3638 	case LPASS_CODEC_VERSION_1_1:
3639 	case LPASS_CODEC_VERSION_1_2:
3640 	case LPASS_CODEC_VERSION_2_0:
3641 	case LPASS_CODEC_VERSION_2_1:
3642 		controls = rx_macro_def_snd_controls;
3643 		num_controls = ARRAY_SIZE(rx_macro_def_snd_controls);
3644 		widgets = rx_macro_def_dapm_widgets;
3645 		num_widgets = ARRAY_SIZE(rx_macro_def_dapm_widgets);
3646 		break;
3647 	case LPASS_CODEC_VERSION_2_5:
3648 	case LPASS_CODEC_VERSION_2_6:
3649 	case LPASS_CODEC_VERSION_2_7:
3650 	case LPASS_CODEC_VERSION_2_8:
3651 		controls = rx_macro_2_5_snd_controls;
3652 		num_controls = ARRAY_SIZE(rx_macro_2_5_snd_controls);
3653 		widgets = rx_macro_2_5_dapm_widgets;
3654 		num_widgets = ARRAY_SIZE(rx_macro_2_5_dapm_widgets);
3655 		break;
3656 	default:
3657 		return -EINVAL;
3658 	}
3659 
3660 	rx->component = component;
3661 
3662 	ret = snd_soc_add_component_controls(component, controls, num_controls);
3663 	if (ret)
3664 		return ret;
3665 
3666 	return snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
3667 }
3668 
swclk_gate_enable(struct clk_hw * hw)3669 static int swclk_gate_enable(struct clk_hw *hw)
3670 {
3671 	struct rx_macro *rx = to_rx_macro(hw);
3672 	int ret;
3673 
3674 	ret = clk_prepare_enable(rx->mclk);
3675 	if (ret) {
3676 		dev_err(rx->dev, "unable to prepare mclk\n");
3677 		return ret;
3678 	}
3679 
3680 	rx_macro_mclk_enable(rx, true);
3681 
3682 	regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3683 			   CDC_RX_SWR_CLK_EN_MASK, 1);
3684 
3685 	return 0;
3686 }
3687 
swclk_gate_disable(struct clk_hw * hw)3688 static void swclk_gate_disable(struct clk_hw *hw)
3689 {
3690 	struct rx_macro *rx = to_rx_macro(hw);
3691 
3692 	regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3693 			   CDC_RX_SWR_CLK_EN_MASK, 0);
3694 
3695 	rx_macro_mclk_enable(rx, false);
3696 	clk_disable_unprepare(rx->mclk);
3697 }
3698 
swclk_gate_is_enabled(struct clk_hw * hw)3699 static int swclk_gate_is_enabled(struct clk_hw *hw)
3700 {
3701 	struct rx_macro *rx = to_rx_macro(hw);
3702 	int ret, val;
3703 
3704 	regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val);
3705 	ret = val & BIT(0);
3706 
3707 	return ret;
3708 }
3709 
swclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)3710 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
3711 				       unsigned long parent_rate)
3712 {
3713 	return parent_rate / 2;
3714 }
3715 
3716 static const struct clk_ops swclk_gate_ops = {
3717 	.prepare = swclk_gate_enable,
3718 	.unprepare = swclk_gate_disable,
3719 	.is_enabled = swclk_gate_is_enabled,
3720 	.recalc_rate = swclk_recalc_rate,
3721 
3722 };
3723 
rx_macro_register_mclk_output(struct rx_macro * rx)3724 static int rx_macro_register_mclk_output(struct rx_macro *rx)
3725 {
3726 	struct device *dev = rx->dev;
3727 	const char *parent_clk_name = NULL;
3728 	const char *clk_name = "lpass-rx-mclk";
3729 	struct clk_hw *hw;
3730 	struct clk_init_data init;
3731 	int ret;
3732 
3733 	if (rx->npl)
3734 		parent_clk_name = __clk_get_name(rx->npl);
3735 	else
3736 		parent_clk_name = __clk_get_name(rx->mclk);
3737 
3738 	init.name = clk_name;
3739 	init.ops = &swclk_gate_ops;
3740 	init.flags = 0;
3741 	init.parent_names = &parent_clk_name;
3742 	init.num_parents = 1;
3743 	rx->hw.init = &init;
3744 	hw = &rx->hw;
3745 	ret = devm_clk_hw_register(rx->dev, hw);
3746 	if (ret)
3747 		return ret;
3748 
3749 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
3750 }
3751 
3752 static const struct snd_soc_component_driver rx_macro_component_drv = {
3753 	.name = "RX-MACRO",
3754 	.probe = rx_macro_component_probe,
3755 	.controls = rx_macro_snd_controls,
3756 	.num_controls = ARRAY_SIZE(rx_macro_snd_controls),
3757 	.dapm_widgets = rx_macro_dapm_widgets,
3758 	.num_dapm_widgets = ARRAY_SIZE(rx_macro_dapm_widgets),
3759 	.dapm_routes = rx_audio_map,
3760 	.num_dapm_routes = ARRAY_SIZE(rx_audio_map),
3761 };
3762 
rx_macro_probe(struct platform_device * pdev)3763 static int rx_macro_probe(struct platform_device *pdev)
3764 {
3765 	struct device *dev = &pdev->dev;
3766 	kernel_ulong_t flags;
3767 	struct rx_macro *rx;
3768 	void __iomem *base;
3769 	int ret, def_count;
3770 
3771 	flags = (kernel_ulong_t)device_get_match_data(dev);
3772 
3773 	rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL);
3774 	if (!rx)
3775 		return -ENOMEM;
3776 
3777 	rx->macro = devm_clk_get_optional(dev, "macro");
3778 	if (IS_ERR(rx->macro))
3779 		return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n");
3780 
3781 	rx->dcodec = devm_clk_get_optional(dev, "dcodec");
3782 	if (IS_ERR(rx->dcodec))
3783 		return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n");
3784 
3785 	rx->mclk = devm_clk_get(dev, "mclk");
3786 	if (IS_ERR(rx->mclk))
3787 		return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n");
3788 
3789 	if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
3790 		rx->npl = devm_clk_get(dev, "npl");
3791 		if (IS_ERR(rx->npl))
3792 			return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n");
3793 	}
3794 
3795 	rx->fsgen = devm_clk_get(dev, "fsgen");
3796 	if (IS_ERR(rx->fsgen))
3797 		return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n");
3798 
3799 	rx->pds = lpass_macro_pds_init(dev);
3800 	if (IS_ERR(rx->pds))
3801 		return PTR_ERR(rx->pds);
3802 
3803 	ret = devm_add_action_or_reset(dev, lpass_macro_pds_exit_action, rx->pds);
3804 	if (ret)
3805 		return ret;
3806 
3807 	base = devm_platform_ioremap_resource(pdev, 0);
3808 	if (IS_ERR(base))
3809 		return PTR_ERR(base);
3810 
3811 	rx->codec_version = lpass_macro_get_codec_version();
3812 	struct reg_default *reg_defaults __free(kfree) = NULL;
3813 
3814 	switch (rx->codec_version) {
3815 	case LPASS_CODEC_VERSION_1_0:
3816 	case LPASS_CODEC_VERSION_1_1:
3817 	case LPASS_CODEC_VERSION_1_2:
3818 	case LPASS_CODEC_VERSION_2_0:
3819 	case LPASS_CODEC_VERSION_2_1:
3820 		rx->rxn_reg_stride = 0x80;
3821 		rx->rxn_reg_stride2 = 0xc;
3822 		def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_pre_2_5_defaults);
3823 		reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL);
3824 		if (!reg_defaults)
3825 			return -ENOMEM;
3826 		memcpy(&reg_defaults[0], rx_defaults, sizeof(rx_defaults));
3827 		memcpy(&reg_defaults[ARRAY_SIZE(rx_defaults)],
3828 				rx_pre_2_5_defaults, sizeof(rx_pre_2_5_defaults));
3829 		break;
3830 	case LPASS_CODEC_VERSION_2_5:
3831 	case LPASS_CODEC_VERSION_2_6:
3832 	case LPASS_CODEC_VERSION_2_7:
3833 	case LPASS_CODEC_VERSION_2_8:
3834 		rx->rxn_reg_stride = 0xc0;
3835 		rx->rxn_reg_stride2 = 0x0;
3836 		def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_2_5_defaults);
3837 		reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL);
3838 		if (!reg_defaults)
3839 			return -ENOMEM;
3840 		memcpy(&reg_defaults[0], rx_defaults, sizeof(rx_defaults));
3841 		memcpy(&reg_defaults[ARRAY_SIZE(rx_defaults)],
3842 				rx_2_5_defaults, sizeof(rx_2_5_defaults));
3843 		break;
3844 	default:
3845 		dev_err(dev, "Unsupported Codec version (%d)\n", rx->codec_version);
3846 		return -EINVAL;
3847 	}
3848 
3849 	struct regmap_config *reg_config __free(kfree) = kmemdup(&rx_regmap_config,
3850 								 sizeof(*reg_config),
3851 								 GFP_KERNEL);
3852 	if (!reg_config)
3853 		return -ENOMEM;
3854 
3855 	reg_config->reg_defaults = reg_defaults;
3856 	reg_config->num_reg_defaults = def_count;
3857 
3858 	rx->regmap = devm_regmap_init_mmio(dev, base, reg_config);
3859 	if (IS_ERR(rx->regmap))
3860 		return PTR_ERR(rx->regmap);
3861 
3862 	dev_set_drvdata(dev, rx);
3863 
3864 	rx->dev = dev;
3865 
3866 	/* set MCLK and NPL rates */
3867 	clk_set_rate(rx->mclk, MCLK_FREQ);
3868 	clk_set_rate(rx->npl, MCLK_FREQ);
3869 
3870 	ret = clk_prepare_enable(rx->macro);
3871 	if (ret)
3872 		return ret;
3873 
3874 	ret = clk_prepare_enable(rx->dcodec);
3875 	if (ret)
3876 		goto err_dcodec;
3877 
3878 	ret = clk_prepare_enable(rx->mclk);
3879 	if (ret)
3880 		goto err_mclk;
3881 
3882 	ret = clk_prepare_enable(rx->npl);
3883 	if (ret)
3884 		goto err_npl;
3885 
3886 	ret = clk_prepare_enable(rx->fsgen);
3887 	if (ret)
3888 		goto err_fsgen;
3889 
3890 	/* reset swr block  */
3891 	regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3892 			   CDC_RX_SWR_RESET_MASK,
3893 			   CDC_RX_SWR_RESET);
3894 
3895 	regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3896 			   CDC_RX_SWR_CLK_EN_MASK, 1);
3897 
3898 	regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3899 			   CDC_RX_SWR_RESET_MASK, 0);
3900 
3901 	ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv,
3902 					      rx_macro_dai,
3903 					      ARRAY_SIZE(rx_macro_dai));
3904 	if (ret)
3905 		goto err_clkout;
3906 
3907 
3908 	pm_runtime_set_autosuspend_delay(dev, 3000);
3909 	pm_runtime_use_autosuspend(dev);
3910 	pm_runtime_mark_last_busy(dev);
3911 	pm_runtime_set_active(dev);
3912 	pm_runtime_enable(dev);
3913 
3914 	ret = rx_macro_register_mclk_output(rx);
3915 	if (ret)
3916 		goto err_clkout;
3917 
3918 	return 0;
3919 
3920 err_clkout:
3921 	clk_disable_unprepare(rx->fsgen);
3922 err_fsgen:
3923 	clk_disable_unprepare(rx->npl);
3924 err_npl:
3925 	clk_disable_unprepare(rx->mclk);
3926 err_mclk:
3927 	clk_disable_unprepare(rx->dcodec);
3928 err_dcodec:
3929 	clk_disable_unprepare(rx->macro);
3930 
3931 	return ret;
3932 }
3933 
rx_macro_remove(struct platform_device * pdev)3934 static void rx_macro_remove(struct platform_device *pdev)
3935 {
3936 	struct rx_macro *rx = dev_get_drvdata(&pdev->dev);
3937 
3938 	clk_disable_unprepare(rx->mclk);
3939 	clk_disable_unprepare(rx->npl);
3940 	clk_disable_unprepare(rx->fsgen);
3941 	clk_disable_unprepare(rx->macro);
3942 	clk_disable_unprepare(rx->dcodec);
3943 }
3944 
3945 static const struct of_device_id rx_macro_dt_match[] = {
3946 	{
3947 		.compatible = "qcom,sc7280-lpass-rx-macro",
3948 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3949 
3950 	}, {
3951 		.compatible = "qcom,sm8250-lpass-rx-macro",
3952 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3953 	}, {
3954 		.compatible = "qcom,sm8450-lpass-rx-macro",
3955 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3956 	}, {
3957 		.compatible = "qcom,sm8550-lpass-rx-macro",
3958 	}, {
3959 		.compatible = "qcom,sc8280xp-lpass-rx-macro",
3960 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3961 	},
3962 	{ }
3963 };
3964 MODULE_DEVICE_TABLE(of, rx_macro_dt_match);
3965 
rx_macro_runtime_suspend(struct device * dev)3966 static int __maybe_unused rx_macro_runtime_suspend(struct device *dev)
3967 {
3968 	struct rx_macro *rx = dev_get_drvdata(dev);
3969 
3970 	regcache_cache_only(rx->regmap, true);
3971 	regcache_mark_dirty(rx->regmap);
3972 
3973 	clk_disable_unprepare(rx->fsgen);
3974 	clk_disable_unprepare(rx->npl);
3975 	clk_disable_unprepare(rx->mclk);
3976 
3977 	return 0;
3978 }
3979 
rx_macro_runtime_resume(struct device * dev)3980 static int __maybe_unused rx_macro_runtime_resume(struct device *dev)
3981 {
3982 	struct rx_macro *rx = dev_get_drvdata(dev);
3983 	int ret;
3984 
3985 	ret = clk_prepare_enable(rx->mclk);
3986 	if (ret) {
3987 		dev_err(dev, "unable to prepare mclk\n");
3988 		return ret;
3989 	}
3990 
3991 	ret = clk_prepare_enable(rx->npl);
3992 	if (ret) {
3993 		dev_err(dev, "unable to prepare mclkx2\n");
3994 		goto err_npl;
3995 	}
3996 
3997 	ret = clk_prepare_enable(rx->fsgen);
3998 	if (ret) {
3999 		dev_err(dev, "unable to prepare fsgen\n");
4000 		goto err_fsgen;
4001 	}
4002 	regcache_cache_only(rx->regmap, false);
4003 	regcache_sync(rx->regmap);
4004 
4005 	return 0;
4006 err_fsgen:
4007 	clk_disable_unprepare(rx->npl);
4008 err_npl:
4009 	clk_disable_unprepare(rx->mclk);
4010 
4011 	return ret;
4012 }
4013 
4014 static const struct dev_pm_ops rx_macro_pm_ops = {
4015 	SET_RUNTIME_PM_OPS(rx_macro_runtime_suspend, rx_macro_runtime_resume, NULL)
4016 };
4017 
4018 static struct platform_driver rx_macro_driver = {
4019 	.driver = {
4020 		.name = "rx_macro",
4021 		.of_match_table = rx_macro_dt_match,
4022 		.suppress_bind_attrs = true,
4023 		.pm = &rx_macro_pm_ops,
4024 	},
4025 	.probe = rx_macro_probe,
4026 	.remove = rx_macro_remove,
4027 };
4028 
4029 module_platform_driver(rx_macro_driver);
4030 
4031 MODULE_DESCRIPTION("RX macro driver");
4032 MODULE_LICENSE("GPL");
4033