1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 *
5 */
6
7#include "rk3588-extra.dtsi"
8
9/ {
10	cluster0_opp_table: opp-table-cluster0 {
11		compatible = "operating-points-v2";
12		opp-shared;
13
14		opp-1416000000 {
15			opp-hz = /bits/ 64 <1416000000>;
16			opp-microvolt = <750000 750000 950000>;
17			clock-latency-ns = <40000>;
18			opp-suspend;
19		};
20		opp-1608000000 {
21			opp-hz = /bits/ 64 <1608000000>;
22			opp-microvolt = <887500 887500 950000>;
23			clock-latency-ns = <40000>;
24		};
25		opp-1704000000 {
26			opp-hz = /bits/ 64 <1704000000>;
27			opp-microvolt = <937500 937500 950000>;
28			clock-latency-ns = <40000>;
29		};
30	};
31
32	cluster1_opp_table: opp-table-cluster1 {
33		compatible = "operating-points-v2";
34		opp-shared;
35
36		opp-1416000000 {
37			opp-hz = /bits/ 64 <1416000000>;
38			opp-microvolt = <750000 750000 950000>;
39			clock-latency-ns = <40000>;
40		};
41		opp-1608000000 {
42			opp-hz = /bits/ 64 <1608000000>;
43			opp-microvolt = <787500 787500 950000>;
44			clock-latency-ns = <40000>;
45		};
46		opp-1800000000 {
47			opp-hz = /bits/ 64 <1800000000>;
48			opp-microvolt = <875000 875000 950000>;
49			clock-latency-ns = <40000>;
50		};
51		opp-2016000000 {
52			opp-hz = /bits/ 64 <2016000000>;
53			opp-microvolt = <950000 950000 950000>;
54			clock-latency-ns = <40000>;
55		};
56	};
57
58	cluster2_opp_table: opp-table-cluster2 {
59		compatible = "operating-points-v2";
60		opp-shared;
61
62		opp-1416000000 {
63			opp-hz = /bits/ 64 <1416000000>;
64			opp-microvolt = <750000 750000 950000>;
65			clock-latency-ns = <40000>;
66		};
67		opp-1608000000 {
68			opp-hz = /bits/ 64 <1608000000>;
69			opp-microvolt = <787500 787500 950000>;
70			clock-latency-ns = <40000>;
71		};
72		opp-1800000000 {
73			opp-hz = /bits/ 64 <1800000000>;
74			opp-microvolt = <875000 875000 950000>;
75			clock-latency-ns = <40000>;
76		};
77		opp-2016000000 {
78			opp-hz = /bits/ 64 <2016000000>;
79			opp-microvolt = <950000 950000 950000>;
80			clock-latency-ns = <40000>;
81		};
82	};
83
84	gpu_opp_table: opp-table {
85		compatible = "operating-points-v2";
86
87		opp-300000000 {
88			opp-hz = /bits/ 64 <300000000>;
89			opp-microvolt = <750000 750000 850000>;
90		};
91		opp-400000000 {
92			opp-hz = /bits/ 64 <400000000>;
93			opp-microvolt = <750000 750000 850000>;
94		};
95		opp-500000000 {
96			opp-hz = /bits/ 64 <500000000>;
97			opp-microvolt = <750000 750000 850000>;
98		};
99		opp-600000000 {
100			opp-hz = /bits/ 64 <600000000>;
101			opp-microvolt = <750000 750000 850000>;
102		};
103		opp-700000000 {
104			opp-hz = /bits/ 64 <700000000>;
105			opp-microvolt = <750000 750000 850000>;
106		};
107		opp-850000000 {
108			opp-hz = /bits/ 64 <800000000>;
109			opp-microvolt = <787500 787500 850000>;
110		};
111	};
112};
113
114&cpu_b0 {
115	operating-points-v2 = <&cluster1_opp_table>;
116};
117
118&cpu_b1 {
119	operating-points-v2 = <&cluster1_opp_table>;
120};
121
122&cpu_b2 {
123	operating-points-v2 = <&cluster2_opp_table>;
124};
125
126&cpu_b3 {
127	operating-points-v2 = <&cluster2_opp_table>;
128};
129
130&cpu_l0 {
131	operating-points-v2 = <&cluster0_opp_table>;
132};
133
134&cpu_l1 {
135	operating-points-v2 = <&cluster0_opp_table>;
136};
137
138&cpu_l2 {
139	operating-points-v2 = <&cluster0_opp_table>;
140};
141
142&cpu_l3 {
143	operating-points-v2 = <&cluster0_opp_table>;
144};
145
146&gpu {
147	operating-points-v2 = <&gpu_opp_table>;
148};
149