1 /* 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33 #include <linux/compat.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pci.h> 39 40 #include <drm/drm_aperture.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_gem.h> 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_pciids.h> 46 #include <drm/drm_probe_helper.h> 47 #include <drm/drm_vblank.h> 48 #include <drm/radeon_drm.h> 49 50 #include "radeon_drv.h" 51 #include "radeon.h" 52 #include "radeon_kms.h" 53 #include "radeon_ttm.h" 54 #include "radeon_device.h" 55 #include "radeon_prime.h" 56 57 /* 58 * KMS wrapper. 59 * - 2.0.0 - initial interface 60 * - 2.1.0 - add square tiling interface 61 * - 2.2.0 - add r6xx/r7xx const buffer support 62 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 63 * - 2.4.0 - add crtc id query 64 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 65 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 66 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 67 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 68 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 69 * 2.10.0 - fusion 2D tiling 70 * 2.11.0 - backend map, initial compute support for the CS checker 71 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 72 * 2.13.0 - virtual memory support, streamout 73 * 2.14.0 - add evergreen tiling informations 74 * 2.15.0 - add max_pipes query 75 * 2.16.0 - fix evergreen 2D tiled surface calculation 76 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 77 * 2.18.0 - r600-eg: allow "invalid" DB formats 78 * 2.19.0 - r600-eg: MSAA textures 79 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 80 * 2.21.0 - r600-r700: FMASK and CMASK 81 * 2.22.0 - r600 only: RESOLVE_BOX allowed 82 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 83 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 84 * 2.25.0 - eg+: new info request for num SE and num SH 85 * 2.26.0 - r600-eg: fix htile size computation 86 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 87 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 88 * 2.29.0 - R500 FP16 color clear registers 89 * 2.30.0 - fix for FMASK texturing 90 * 2.31.0 - Add fastfb support for rs690 91 * 2.32.0 - new info request for rings working 92 * 2.33.0 - Add SI tiling mode array query 93 * 2.34.0 - Add CIK tiling mode array query 94 * 2.35.0 - Add CIK macrotile mode array query 95 * 2.36.0 - Fix CIK DCE tiling setup 96 * 2.37.0 - allow GS ring setup on r6xx/r7xx 97 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 98 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 99 * 2.39.0 - Add INFO query for number of active CUs 100 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 101 * CS to GPU on >= r600 102 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 103 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 104 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 105 * 2.44.0 - SET_APPEND_CNT packet3 support 106 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 107 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 108 * 2.47.0 - Add UVD_NO_OP register support 109 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 110 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 111 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 112 */ 113 #define KMS_DRIVER_MAJOR 2 114 #define KMS_DRIVER_MINOR 50 115 #define KMS_DRIVER_PATCHLEVEL 0 116 117 int radeon_no_wb; 118 int radeon_modeset = -1; 119 int radeon_dynclks = -1; 120 int radeon_r4xx_atom; 121 int radeon_agpmode = -1; 122 int radeon_vram_limit; 123 int radeon_gart_size = -1; /* auto */ 124 int radeon_benchmarking; 125 int radeon_testing; 126 int radeon_connector_table; 127 int radeon_tv = 1; 128 int radeon_audio = -1; 129 int radeon_disp_priority; 130 int radeon_hw_i2c; 131 int radeon_pcie_gen2 = -1; 132 int radeon_msi = -1; 133 int radeon_lockup_timeout = 10000; 134 int radeon_fastfb; 135 int radeon_dpm = -1; 136 int radeon_aspm = -1; 137 int radeon_runtime_pm = -1; 138 int radeon_hard_reset; 139 int radeon_vm_size = 8; 140 int radeon_vm_block_size = -1; 141 int radeon_deep_color; 142 int radeon_use_pflipirq = 2; 143 int radeon_bapm = -1; 144 int radeon_backlight = -1; 145 int radeon_auxch = -1; 146 int radeon_uvd = 1; 147 int radeon_vce = 1; 148 149 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 150 module_param_named(no_wb, radeon_no_wb, int, 0444); 151 152 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 153 module_param_named(modeset, radeon_modeset, int, 0400); 154 155 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 156 module_param_named(dynclks, radeon_dynclks, int, 0444); 157 158 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 159 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 160 161 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 162 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 163 164 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 165 module_param_named(agpmode, radeon_agpmode, int, 0444); 166 167 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 168 module_param_named(gartsize, radeon_gart_size, int, 0600); 169 170 MODULE_PARM_DESC(benchmark, "Run benchmark"); 171 module_param_named(benchmark, radeon_benchmarking, int, 0444); 172 173 MODULE_PARM_DESC(test, "Run tests"); 174 module_param_named(test, radeon_testing, int, 0444); 175 176 MODULE_PARM_DESC(connector_table, "Force connector table"); 177 module_param_named(connector_table, radeon_connector_table, int, 0444); 178 179 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 180 module_param_named(tv, radeon_tv, int, 0444); 181 182 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 183 module_param_named(audio, radeon_audio, int, 0444); 184 185 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 186 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 187 188 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 189 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 190 191 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 192 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 193 194 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 195 module_param_named(msi, radeon_msi, int, 0444); 196 197 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 198 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 199 200 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 201 module_param_named(fastfb, radeon_fastfb, int, 0444); 202 203 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 204 module_param_named(dpm, radeon_dpm, int, 0444); 205 206 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 207 module_param_named(aspm, radeon_aspm, int, 0444); 208 209 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 210 module_param_named(runpm, radeon_runtime_pm, int, 0444); 211 212 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 213 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 214 215 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 216 module_param_named(vm_size, radeon_vm_size, int, 0444); 217 218 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 219 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 220 221 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 222 module_param_named(deep_color, radeon_deep_color, int, 0444); 223 224 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 225 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 226 227 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 228 module_param_named(bapm, radeon_bapm, int, 0444); 229 230 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 231 module_param_named(backlight, radeon_backlight, int, 0444); 232 233 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 234 module_param_named(auxch, radeon_auxch, int, 0444); 235 236 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 237 module_param_named(uvd, radeon_uvd, int, 0444); 238 239 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 240 module_param_named(vce, radeon_vce, int, 0444); 241 242 int radeon_si_support = 1; 243 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 244 module_param_named(si_support, radeon_si_support, int, 0444); 245 246 int radeon_cik_support = 1; 247 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 248 module_param_named(cik_support, radeon_cik_support, int, 0444); 249 250 static struct pci_device_id pciidlist[] = { 251 radeon_PCI_IDS 252 }; 253 254 MODULE_DEVICE_TABLE(pci, pciidlist); 255 256 static const struct drm_driver kms_driver; 257 radeon_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)258 static int radeon_pci_probe(struct pci_dev *pdev, 259 const struct pci_device_id *ent) 260 { 261 unsigned long flags = 0; 262 struct drm_device *ddev; 263 struct radeon_device *rdev; 264 int ret; 265 266 if (!ent) 267 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 268 269 flags = ent->driver_data; 270 271 if (!radeon_si_support) { 272 switch (flags & RADEON_FAMILY_MASK) { 273 case CHIP_TAHITI: 274 case CHIP_PITCAIRN: 275 case CHIP_VERDE: 276 case CHIP_OLAND: 277 case CHIP_HAINAN: 278 dev_info(&pdev->dev, 279 "SI support disabled by module param\n"); 280 return -ENODEV; 281 } 282 } 283 if (!radeon_cik_support) { 284 switch (flags & RADEON_FAMILY_MASK) { 285 case CHIP_KAVERI: 286 case CHIP_BONAIRE: 287 case CHIP_HAWAII: 288 case CHIP_KABINI: 289 case CHIP_MULLINS: 290 dev_info(&pdev->dev, 291 "CIK support disabled by module param\n"); 292 return -ENODEV; 293 } 294 } 295 296 if (vga_switcheroo_client_probe_defer(pdev)) 297 return -EPROBE_DEFER; 298 299 /* Get rid of things like offb */ 300 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &kms_driver); 301 if (ret) 302 return ret; 303 304 rdev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*rdev), ddev); 305 if (IS_ERR(rdev)) 306 return PTR_ERR(rdev); 307 308 rdev->dev = &pdev->dev; 309 rdev->pdev = pdev; 310 ddev = rdev_to_drm(rdev); 311 ddev->dev_private = rdev; 312 313 ret = pci_enable_device(pdev); 314 if (ret) 315 goto err_free; 316 317 pci_set_drvdata(pdev, ddev); 318 319 ret = radeon_driver_load_kms(ddev, flags); 320 if (ret) 321 goto err_agp; 322 323 ret = drm_dev_register(ddev, flags); 324 if (ret) 325 goto err_agp; 326 327 radeon_fbdev_setup(ddev->dev_private); 328 329 return 0; 330 331 err_agp: 332 pci_disable_device(pdev); 333 err_free: 334 drm_dev_put(ddev); 335 return ret; 336 } 337 338 static void radeon_pci_remove(struct pci_dev * pdev)339 radeon_pci_remove(struct pci_dev *pdev) 340 { 341 struct drm_device *dev = pci_get_drvdata(pdev); 342 343 drm_put_dev(dev); 344 } 345 346 static void radeon_pci_shutdown(struct pci_dev * pdev)347 radeon_pci_shutdown(struct pci_dev *pdev) 348 { 349 /* if we are running in a VM, make sure the device 350 * torn down properly on reboot/shutdown 351 */ 352 if (radeon_device_is_virtual()) 353 radeon_pci_remove(pdev); 354 355 #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64) 356 /* 357 * Some adapters need to be suspended before a 358 * shutdown occurs in order to prevent an error 359 * during kexec, shutdown or reboot. 360 * Make this power and Loongson specific because 361 * it breaks some other boards. 362 */ 363 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 364 #endif 365 } 366 radeon_pmops_suspend(struct device * dev)367 static int radeon_pmops_suspend(struct device *dev) 368 { 369 struct drm_device *drm_dev = dev_get_drvdata(dev); 370 371 return radeon_suspend_kms(drm_dev, true, true, false); 372 } 373 radeon_pmops_resume(struct device * dev)374 static int radeon_pmops_resume(struct device *dev) 375 { 376 struct drm_device *drm_dev = dev_get_drvdata(dev); 377 378 /* GPU comes up enabled by the bios on resume */ 379 if (radeon_is_px(drm_dev)) { 380 pm_runtime_disable(dev); 381 pm_runtime_set_active(dev); 382 pm_runtime_enable(dev); 383 } 384 385 return radeon_resume_kms(drm_dev, true, true); 386 } 387 radeon_pmops_freeze(struct device * dev)388 static int radeon_pmops_freeze(struct device *dev) 389 { 390 struct drm_device *drm_dev = dev_get_drvdata(dev); 391 392 return radeon_suspend_kms(drm_dev, false, true, true); 393 } 394 radeon_pmops_thaw(struct device * dev)395 static int radeon_pmops_thaw(struct device *dev) 396 { 397 struct drm_device *drm_dev = dev_get_drvdata(dev); 398 399 return radeon_resume_kms(drm_dev, false, true); 400 } 401 radeon_pmops_runtime_suspend(struct device * dev)402 static int radeon_pmops_runtime_suspend(struct device *dev) 403 { 404 struct pci_dev *pdev = to_pci_dev(dev); 405 struct drm_device *drm_dev = pci_get_drvdata(pdev); 406 407 if (!radeon_is_px(drm_dev)) { 408 pm_runtime_forbid(dev); 409 return -EBUSY; 410 } 411 412 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 413 drm_kms_helper_poll_disable(drm_dev); 414 415 radeon_suspend_kms(drm_dev, false, false, false); 416 pci_save_state(pdev); 417 pci_disable_device(pdev); 418 pci_ignore_hotplug(pdev); 419 if (radeon_is_atpx_hybrid()) 420 pci_set_power_state(pdev, PCI_D3cold); 421 else if (!radeon_has_atpx_dgpu_power_cntl()) 422 pci_set_power_state(pdev, PCI_D3hot); 423 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 424 425 return 0; 426 } 427 radeon_pmops_runtime_resume(struct device * dev)428 static int radeon_pmops_runtime_resume(struct device *dev) 429 { 430 struct pci_dev *pdev = to_pci_dev(dev); 431 struct drm_device *drm_dev = pci_get_drvdata(pdev); 432 int ret; 433 434 if (!radeon_is_px(drm_dev)) 435 return -EINVAL; 436 437 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 438 439 if (radeon_is_atpx_hybrid() || 440 !radeon_has_atpx_dgpu_power_cntl()) 441 pci_set_power_state(pdev, PCI_D0); 442 pci_restore_state(pdev); 443 ret = pci_enable_device(pdev); 444 if (ret) 445 return ret; 446 pci_set_master(pdev); 447 448 ret = radeon_resume_kms(drm_dev, false, false); 449 drm_kms_helper_poll_enable(drm_dev); 450 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 451 return 0; 452 } 453 radeon_pmops_runtime_idle(struct device * dev)454 static int radeon_pmops_runtime_idle(struct device *dev) 455 { 456 struct drm_device *drm_dev = dev_get_drvdata(dev); 457 struct drm_crtc *crtc; 458 459 if (!radeon_is_px(drm_dev)) { 460 pm_runtime_forbid(dev); 461 return -EBUSY; 462 } 463 464 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 465 if (crtc->enabled) { 466 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 467 return -EBUSY; 468 } 469 } 470 471 pm_runtime_mark_last_busy(dev); 472 pm_runtime_autosuspend(dev); 473 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 474 return 1; 475 } 476 radeon_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)477 long radeon_drm_ioctl(struct file *filp, 478 unsigned int cmd, unsigned long arg) 479 { 480 struct drm_file *file_priv = filp->private_data; 481 struct drm_device *dev; 482 long ret; 483 484 dev = file_priv->minor->dev; 485 ret = pm_runtime_get_sync(dev->dev); 486 if (ret < 0) { 487 pm_runtime_put_autosuspend(dev->dev); 488 return ret; 489 } 490 491 ret = drm_ioctl(filp, cmd, arg); 492 493 pm_runtime_mark_last_busy(dev->dev); 494 pm_runtime_put_autosuspend(dev->dev); 495 return ret; 496 } 497 498 #ifdef CONFIG_COMPAT radeon_kms_compat_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)499 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 500 { 501 unsigned int nr = DRM_IOCTL_NR(cmd); 502 503 if (nr < DRM_COMMAND_BASE) 504 return drm_compat_ioctl(filp, cmd, arg); 505 506 return radeon_drm_ioctl(filp, cmd, arg); 507 } 508 #endif 509 510 static const struct dev_pm_ops radeon_pm_ops = { 511 .suspend = radeon_pmops_suspend, 512 .resume = radeon_pmops_resume, 513 .freeze = radeon_pmops_freeze, 514 .thaw = radeon_pmops_thaw, 515 .poweroff = radeon_pmops_freeze, 516 .restore = radeon_pmops_resume, 517 .runtime_suspend = radeon_pmops_runtime_suspend, 518 .runtime_resume = radeon_pmops_runtime_resume, 519 .runtime_idle = radeon_pmops_runtime_idle, 520 }; 521 522 static const struct file_operations radeon_driver_kms_fops = { 523 .owner = THIS_MODULE, 524 .open = drm_open, 525 .release = drm_release, 526 .unlocked_ioctl = radeon_drm_ioctl, 527 .mmap = drm_gem_mmap, 528 .poll = drm_poll, 529 .read = drm_read, 530 #ifdef CONFIG_COMPAT 531 .compat_ioctl = radeon_kms_compat_ioctl, 532 #endif 533 .fop_flags = FOP_UNSIGNED_OFFSET, 534 }; 535 536 static const struct drm_ioctl_desc radeon_ioctls_kms[] = { 537 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 538 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 539 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 540 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 541 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 542 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 543 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 544 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 545 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 546 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 547 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 548 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 549 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 550 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 551 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 552 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 553 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 554 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 555 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 556 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 557 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 558 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 559 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 560 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 561 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 562 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 563 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 564 /* KMS */ 565 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 566 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 567 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 568 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 569 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 570 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 571 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 572 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 573 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 574 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 575 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 576 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 577 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 578 }; 579 580 static const struct drm_driver kms_driver = { 581 .driver_features = 582 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET, 583 .open = radeon_driver_open_kms, 584 .postclose = radeon_driver_postclose_kms, 585 .unload = radeon_driver_unload_kms, 586 .ioctls = radeon_ioctls_kms, 587 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms), 588 .dumb_create = radeon_mode_dumb_create, 589 .dumb_map_offset = radeon_mode_dumb_mmap, 590 .fops = &radeon_driver_kms_fops, 591 592 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 593 594 .name = DRIVER_NAME, 595 .desc = DRIVER_DESC, 596 .date = DRIVER_DATE, 597 .major = KMS_DRIVER_MAJOR, 598 .minor = KMS_DRIVER_MINOR, 599 .patchlevel = KMS_DRIVER_PATCHLEVEL, 600 }; 601 602 static struct pci_driver radeon_kms_pci_driver = { 603 .name = DRIVER_NAME, 604 .id_table = pciidlist, 605 .probe = radeon_pci_probe, 606 .remove = radeon_pci_remove, 607 .shutdown = radeon_pci_shutdown, 608 .driver.pm = &radeon_pm_ops, 609 }; 610 radeon_module_init(void)611 static int __init radeon_module_init(void) 612 { 613 if (drm_firmware_drivers_only() && radeon_modeset == -1) 614 radeon_modeset = 0; 615 616 if (radeon_modeset == 0) 617 return -EINVAL; 618 619 DRM_INFO("radeon kernel modesetting enabled.\n"); 620 radeon_register_atpx_handler(); 621 622 return pci_register_driver(&radeon_kms_pci_driver); 623 } 624 radeon_module_exit(void)625 static void __exit radeon_module_exit(void) 626 { 627 pci_unregister_driver(&radeon_kms_pci_driver); 628 radeon_unregister_atpx_handler(); 629 mmu_notifier_synchronize(); 630 } 631 632 module_init(radeon_module_init); 633 module_exit(radeon_module_exit); 634 635 MODULE_AUTHOR(DRIVER_AUTHOR); 636 MODULE_DESCRIPTION(DRIVER_DESC); 637 MODULE_LICENSE("GPL and additional rights"); 638