1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
4 * Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * TODO:
7 *
8 * - Replace mdelay with some schedule loop if possible
9 * - Shorten some obfuscated delays on some routines (like modem
10 * power)
11 * - Refcount some clocks (see darwin)
12 * - Split split split...
13 */
14 #include <linux/types.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/spinlock.h>
22 #include <linux/adb.h>
23 #include <linux/pmu.h>
24 #include <linux/ioport.h>
25 #include <linux/export.h>
26 #include <linux/pci.h>
27 #include <asm/sections.h>
28 #include <asm/errno.h>
29 #include <asm/ohare.h>
30 #include <asm/heathrow.h>
31 #include <asm/keylargo.h>
32 #include <asm/uninorth.h>
33 #include <asm/io.h>
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/dbdma.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/pmac_low_i2c.h>
39
40 #include "pmac.h"
41
42 #undef DEBUG_FEATURE
43
44 #ifdef DEBUG_FEATURE
45 #define DBG(fmt...) printk(KERN_DEBUG fmt)
46 #else
47 #define DBG(fmt...)
48 #endif
49
50 #ifdef CONFIG_PPC_BOOK3S_32
51 extern int powersave_lowspeed;
52 #endif
53
54 extern int powersave_nap;
55 extern struct device_node *k2_skiplist[2];
56
57 /*
58 * We use a single global lock to protect accesses. Each driver has
59 * to take care of its own locking
60 */
61 DEFINE_RAW_SPINLOCK(feature_lock);
62
63 #define LOCK(flags) raw_spin_lock_irqsave(&feature_lock, flags);
64 #define UNLOCK(flags) raw_spin_unlock_irqrestore(&feature_lock, flags);
65
66
67 /*
68 * Instance of some macio stuffs
69 */
70 struct macio_chip macio_chips[MAX_MACIO_CHIPS];
71
macio_find(struct device_node * child,int type)72 struct macio_chip *macio_find(struct device_node *child, int type)
73 {
74 while(child) {
75 int i;
76
77 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
78 if (child == macio_chips[i].of_node &&
79 (!type || macio_chips[i].type == type))
80 return &macio_chips[i];
81 child = child->parent;
82 }
83 return NULL;
84 }
85 EXPORT_SYMBOL_GPL(macio_find);
86
87 static const char *macio_names[] =
88 {
89 "Unknown",
90 "Grand Central",
91 "OHare",
92 "OHareII",
93 "Heathrow",
94 "Gatwick",
95 "Paddington",
96 "Keylargo",
97 "Pangea",
98 "Intrepid",
99 "K2",
100 "Shasta",
101 };
102
103
104 struct device_node *uninorth_node;
105 u32 __iomem *uninorth_base;
106
107 static u32 uninorth_rev;
108 static int uninorth_maj;
109 static void __iomem *u3_ht_base;
110
111 /*
112 * For each motherboard family, we have a table of functions pointers
113 * that handle the various features.
114 */
115
116 typedef long (*feature_call)(struct device_node *node, long param, long value);
117
118 struct feature_table_entry {
119 unsigned int selector;
120 feature_call function;
121 };
122
123 struct pmac_mb_def
124 {
125 const char* model_string;
126 const char* model_name;
127 int model_id;
128 struct feature_table_entry* features;
129 unsigned long board_flags;
130 };
131 static struct pmac_mb_def pmac_mb;
132
133 /*
134 * Here are the chip specific feature functions
135 */
136
137 #ifndef CONFIG_PPC64
138
simple_feature_tweak(struct device_node * node,int type,int reg,u32 mask,int value)139 static int simple_feature_tweak(struct device_node *node, int type, int reg,
140 u32 mask, int value)
141 {
142 struct macio_chip* macio;
143 unsigned long flags;
144
145 macio = macio_find(node, type);
146 if (!macio)
147 return -ENODEV;
148 LOCK(flags);
149 if (value)
150 MACIO_BIS(reg, mask);
151 else
152 MACIO_BIC(reg, mask);
153 (void)MACIO_IN32(reg);
154 UNLOCK(flags);
155
156 return 0;
157 }
158
ohare_htw_scc_enable(struct device_node * node,long param,long value)159 static long ohare_htw_scc_enable(struct device_node *node, long param,
160 long value)
161 {
162 struct macio_chip* macio;
163 unsigned long chan_mask;
164 unsigned long fcr;
165 unsigned long flags;
166 int htw, trans;
167 unsigned long rmask;
168
169 macio = macio_find(node, 0);
170 if (!macio)
171 return -ENODEV;
172 if (of_node_name_eq(node, "ch-a"))
173 chan_mask = MACIO_FLAG_SCCA_ON;
174 else if (of_node_name_eq(node, "ch-b"))
175 chan_mask = MACIO_FLAG_SCCB_ON;
176 else
177 return -ENODEV;
178
179 htw = (macio->type == macio_heathrow || macio->type == macio_paddington
180 || macio->type == macio_gatwick);
181 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
182 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
183 pmac_mb.model_id != PMAC_TYPE_YIKES);
184 if (value) {
185 #ifdef CONFIG_ADB_PMU
186 if ((param & 0xfff) == PMAC_SCC_IRDA)
187 pmu_enable_irled(1);
188 #endif /* CONFIG_ADB_PMU */
189 LOCK(flags);
190 fcr = MACIO_IN32(OHARE_FCR);
191 /* Check if scc cell need enabling */
192 if (!(fcr & OH_SCC_ENABLE)) {
193 fcr |= OH_SCC_ENABLE;
194 if (htw) {
195 /* Side effect: this will also power up the
196 * modem, but it's too messy to figure out on which
197 * ports this controls the transceiver and on which
198 * it controls the modem
199 */
200 if (trans)
201 fcr &= ~HRW_SCC_TRANS_EN_N;
202 MACIO_OUT32(OHARE_FCR, fcr);
203 fcr |= (rmask = HRW_RESET_SCC);
204 MACIO_OUT32(OHARE_FCR, fcr);
205 } else {
206 fcr |= (rmask = OH_SCC_RESET);
207 MACIO_OUT32(OHARE_FCR, fcr);
208 }
209 UNLOCK(flags);
210 (void)MACIO_IN32(OHARE_FCR);
211 mdelay(15);
212 LOCK(flags);
213 fcr &= ~rmask;
214 MACIO_OUT32(OHARE_FCR, fcr);
215 }
216 if (chan_mask & MACIO_FLAG_SCCA_ON)
217 fcr |= OH_SCCA_IO;
218 if (chan_mask & MACIO_FLAG_SCCB_ON)
219 fcr |= OH_SCCB_IO;
220 MACIO_OUT32(OHARE_FCR, fcr);
221 macio->flags |= chan_mask;
222 UNLOCK(flags);
223 if (param & PMAC_SCC_FLAG_XMON)
224 macio->flags |= MACIO_FLAG_SCC_LOCKED;
225 } else {
226 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
227 return -EPERM;
228 LOCK(flags);
229 fcr = MACIO_IN32(OHARE_FCR);
230 if (chan_mask & MACIO_FLAG_SCCA_ON)
231 fcr &= ~OH_SCCA_IO;
232 if (chan_mask & MACIO_FLAG_SCCB_ON)
233 fcr &= ~OH_SCCB_IO;
234 MACIO_OUT32(OHARE_FCR, fcr);
235 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
236 fcr &= ~OH_SCC_ENABLE;
237 if (htw && trans)
238 fcr |= HRW_SCC_TRANS_EN_N;
239 MACIO_OUT32(OHARE_FCR, fcr);
240 }
241 macio->flags &= ~(chan_mask);
242 UNLOCK(flags);
243 mdelay(10);
244 #ifdef CONFIG_ADB_PMU
245 if ((param & 0xfff) == PMAC_SCC_IRDA)
246 pmu_enable_irled(0);
247 #endif /* CONFIG_ADB_PMU */
248 }
249 return 0;
250 }
251
ohare_floppy_enable(struct device_node * node,long param,long value)252 static long ohare_floppy_enable(struct device_node *node, long param,
253 long value)
254 {
255 return simple_feature_tweak(node, macio_ohare,
256 OHARE_FCR, OH_FLOPPY_ENABLE, value);
257 }
258
ohare_mesh_enable(struct device_node * node,long param,long value)259 static long ohare_mesh_enable(struct device_node *node, long param, long value)
260 {
261 return simple_feature_tweak(node, macio_ohare,
262 OHARE_FCR, OH_MESH_ENABLE, value);
263 }
264
ohare_ide_enable(struct device_node * node,long param,long value)265 static long ohare_ide_enable(struct device_node *node, long param, long value)
266 {
267 switch(param) {
268 case 0:
269 /* For some reason, setting the bit in set_initial_features()
270 * doesn't stick. I'm still investigating... --BenH.
271 */
272 if (value)
273 simple_feature_tweak(node, macio_ohare,
274 OHARE_FCR, OH_IOBUS_ENABLE, 1);
275 return simple_feature_tweak(node, macio_ohare,
276 OHARE_FCR, OH_IDE0_ENABLE, value);
277 case 1:
278 return simple_feature_tweak(node, macio_ohare,
279 OHARE_FCR, OH_BAY_IDE_ENABLE, value);
280 default:
281 return -ENODEV;
282 }
283 }
284
ohare_ide_reset(struct device_node * node,long param,long value)285 static long ohare_ide_reset(struct device_node *node, long param, long value)
286 {
287 switch(param) {
288 case 0:
289 return simple_feature_tweak(node, macio_ohare,
290 OHARE_FCR, OH_IDE0_RESET_N, !value);
291 case 1:
292 return simple_feature_tweak(node, macio_ohare,
293 OHARE_FCR, OH_IDE1_RESET_N, !value);
294 default:
295 return -ENODEV;
296 }
297 }
298
ohare_sleep_state(struct device_node * node,long param,long value)299 static long ohare_sleep_state(struct device_node *node, long param, long value)
300 {
301 struct macio_chip* macio = &macio_chips[0];
302
303 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
304 return -EPERM;
305 if (value == 1) {
306 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
307 } else if (value == 0) {
308 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
309 }
310
311 return 0;
312 }
313
heathrow_modem_enable(struct device_node * node,long param,long value)314 static long heathrow_modem_enable(struct device_node *node, long param,
315 long value)
316 {
317 struct macio_chip* macio;
318 u8 gpio;
319 unsigned long flags;
320
321 macio = macio_find(node, macio_unknown);
322 if (!macio)
323 return -ENODEV;
324 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
325 if (!value) {
326 LOCK(flags);
327 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
328 UNLOCK(flags);
329 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
330 mdelay(250);
331 }
332 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
333 pmac_mb.model_id != PMAC_TYPE_YIKES) {
334 LOCK(flags);
335 if (value)
336 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
337 else
338 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
339 UNLOCK(flags);
340 (void)MACIO_IN32(HEATHROW_FCR);
341 mdelay(250);
342 }
343 if (value) {
344 LOCK(flags);
345 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
346 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
347 UNLOCK(flags); mdelay(250); LOCK(flags);
348 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
349 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
350 UNLOCK(flags); mdelay(250); LOCK(flags);
351 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
352 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
353 UNLOCK(flags); mdelay(250);
354 }
355 return 0;
356 }
357
heathrow_floppy_enable(struct device_node * node,long param,long value)358 static long heathrow_floppy_enable(struct device_node *node, long param,
359 long value)
360 {
361 return simple_feature_tweak(node, macio_unknown,
362 HEATHROW_FCR,
363 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
364 value);
365 }
366
heathrow_mesh_enable(struct device_node * node,long param,long value)367 static long heathrow_mesh_enable(struct device_node *node, long param,
368 long value)
369 {
370 struct macio_chip* macio;
371 unsigned long flags;
372
373 macio = macio_find(node, macio_unknown);
374 if (!macio)
375 return -ENODEV;
376 LOCK(flags);
377 /* Set clear mesh cell enable */
378 if (value)
379 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
380 else
381 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
382 (void)MACIO_IN32(HEATHROW_FCR);
383 udelay(10);
384 /* Set/Clear termination power */
385 if (value)
386 MACIO_BIC(HEATHROW_MBCR, 0x04000000);
387 else
388 MACIO_BIS(HEATHROW_MBCR, 0x04000000);
389 (void)MACIO_IN32(HEATHROW_MBCR);
390 udelay(10);
391 UNLOCK(flags);
392
393 return 0;
394 }
395
heathrow_ide_enable(struct device_node * node,long param,long value)396 static long heathrow_ide_enable(struct device_node *node, long param,
397 long value)
398 {
399 switch(param) {
400 case 0:
401 return simple_feature_tweak(node, macio_unknown,
402 HEATHROW_FCR, HRW_IDE0_ENABLE, value);
403 case 1:
404 return simple_feature_tweak(node, macio_unknown,
405 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
406 default:
407 return -ENODEV;
408 }
409 }
410
heathrow_ide_reset(struct device_node * node,long param,long value)411 static long heathrow_ide_reset(struct device_node *node, long param,
412 long value)
413 {
414 switch(param) {
415 case 0:
416 return simple_feature_tweak(node, macio_unknown,
417 HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
418 case 1:
419 return simple_feature_tweak(node, macio_unknown,
420 HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
421 default:
422 return -ENODEV;
423 }
424 }
425
heathrow_bmac_enable(struct device_node * node,long param,long value)426 static long heathrow_bmac_enable(struct device_node *node, long param,
427 long value)
428 {
429 struct macio_chip* macio;
430 unsigned long flags;
431
432 macio = macio_find(node, 0);
433 if (!macio)
434 return -ENODEV;
435 if (value) {
436 LOCK(flags);
437 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
438 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
439 UNLOCK(flags);
440 (void)MACIO_IN32(HEATHROW_FCR);
441 mdelay(10);
442 LOCK(flags);
443 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
444 UNLOCK(flags);
445 (void)MACIO_IN32(HEATHROW_FCR);
446 mdelay(10);
447 } else {
448 LOCK(flags);
449 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
450 UNLOCK(flags);
451 }
452 return 0;
453 }
454
heathrow_sound_enable(struct device_node * node,long param,long value)455 static long heathrow_sound_enable(struct device_node *node, long param,
456 long value)
457 {
458 struct macio_chip* macio;
459 unsigned long flags;
460
461 /* B&W G3 and Yikes don't support that properly (the
462 * sound appear to never come back after being shut down).
463 */
464 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
465 pmac_mb.model_id == PMAC_TYPE_YIKES)
466 return 0;
467
468 macio = macio_find(node, 0);
469 if (!macio)
470 return -ENODEV;
471 if (value) {
472 LOCK(flags);
473 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
474 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
475 UNLOCK(flags);
476 (void)MACIO_IN32(HEATHROW_FCR);
477 } else {
478 LOCK(flags);
479 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
480 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
481 UNLOCK(flags);
482 }
483 return 0;
484 }
485
486 static u32 save_fcr[6];
487 static u32 save_mbcr;
488 static struct dbdma_regs save_dbdma[13];
489 static struct dbdma_regs save_alt_dbdma[13];
490
dbdma_save(struct macio_chip * macio,struct dbdma_regs * save)491 static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save)
492 {
493 int i;
494
495 /* Save state & config of DBDMA channels */
496 for (i = 0; i < 13; i++) {
497 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
498 (macio->base + ((0x8000+i*0x100)>>2));
499 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
500 save[i].cmdptr = in_le32(&chan->cmdptr);
501 save[i].intr_sel = in_le32(&chan->intr_sel);
502 save[i].br_sel = in_le32(&chan->br_sel);
503 save[i].wait_sel = in_le32(&chan->wait_sel);
504 }
505 }
506
dbdma_restore(struct macio_chip * macio,struct dbdma_regs * save)507 static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save)
508 {
509 int i;
510
511 /* Save state & config of DBDMA channels */
512 for (i = 0; i < 13; i++) {
513 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
514 (macio->base + ((0x8000+i*0x100)>>2));
515 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
516 while (in_le32(&chan->status) & ACTIVE)
517 mb();
518 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
519 out_le32(&chan->cmdptr, save[i].cmdptr);
520 out_le32(&chan->intr_sel, save[i].intr_sel);
521 out_le32(&chan->br_sel, save[i].br_sel);
522 out_le32(&chan->wait_sel, save[i].wait_sel);
523 }
524 }
525
heathrow_sleep(struct macio_chip * macio,int secondary)526 static void heathrow_sleep(struct macio_chip *macio, int secondary)
527 {
528 if (secondary) {
529 dbdma_save(macio, save_alt_dbdma);
530 save_fcr[2] = MACIO_IN32(0x38);
531 save_fcr[3] = MACIO_IN32(0x3c);
532 } else {
533 dbdma_save(macio, save_dbdma);
534 save_fcr[0] = MACIO_IN32(0x38);
535 save_fcr[1] = MACIO_IN32(0x3c);
536 save_mbcr = MACIO_IN32(0x34);
537 /* Make sure sound is shut down */
538 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
539 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
540 /* This seems to be necessary as well or the fan
541 * keeps coming up and battery drains fast */
542 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
543 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
544 /* Make sure eth is down even if module or sleep
545 * won't work properly */
546 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
547 }
548 /* Make sure modem is shut down */
549 MACIO_OUT8(HRW_GPIO_MODEM_RESET,
550 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
551 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
552 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
553
554 /* Let things settle */
555 (void)MACIO_IN32(HEATHROW_FCR);
556 }
557
heathrow_wakeup(struct macio_chip * macio,int secondary)558 static void heathrow_wakeup(struct macio_chip *macio, int secondary)
559 {
560 if (secondary) {
561 MACIO_OUT32(0x38, save_fcr[2]);
562 (void)MACIO_IN32(0x38);
563 mdelay(1);
564 MACIO_OUT32(0x3c, save_fcr[3]);
565 (void)MACIO_IN32(0x38);
566 mdelay(10);
567 dbdma_restore(macio, save_alt_dbdma);
568 } else {
569 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
570 (void)MACIO_IN32(0x38);
571 mdelay(1);
572 MACIO_OUT32(0x3c, save_fcr[1]);
573 (void)MACIO_IN32(0x38);
574 mdelay(1);
575 MACIO_OUT32(0x34, save_mbcr);
576 (void)MACIO_IN32(0x38);
577 mdelay(10);
578 dbdma_restore(macio, save_dbdma);
579 }
580 }
581
heathrow_sleep_state(struct device_node * node,long param,long value)582 static long heathrow_sleep_state(struct device_node *node, long param,
583 long value)
584 {
585 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
586 return -EPERM;
587 if (value == 1) {
588 if (macio_chips[1].type == macio_gatwick)
589 heathrow_sleep(&macio_chips[0], 1);
590 heathrow_sleep(&macio_chips[0], 0);
591 } else if (value == 0) {
592 heathrow_wakeup(&macio_chips[0], 0);
593 if (macio_chips[1].type == macio_gatwick)
594 heathrow_wakeup(&macio_chips[0], 1);
595 }
596 return 0;
597 }
598
core99_scc_enable(struct device_node * node,long param,long value)599 static long core99_scc_enable(struct device_node *node, long param, long value)
600 {
601 struct macio_chip* macio;
602 unsigned long flags;
603 unsigned long chan_mask;
604 u32 fcr;
605
606 macio = macio_find(node, 0);
607 if (!macio)
608 return -ENODEV;
609 if (of_node_name_eq(node, "ch-a"))
610 chan_mask = MACIO_FLAG_SCCA_ON;
611 else if (of_node_name_eq(node, "ch-b"))
612 chan_mask = MACIO_FLAG_SCCB_ON;
613 else
614 return -ENODEV;
615
616 if (value) {
617 int need_reset_scc = 0;
618 int need_reset_irda = 0;
619
620 LOCK(flags);
621 fcr = MACIO_IN32(KEYLARGO_FCR0);
622 /* Check if scc cell need enabling */
623 if (!(fcr & KL0_SCC_CELL_ENABLE)) {
624 fcr |= KL0_SCC_CELL_ENABLE;
625 need_reset_scc = 1;
626 }
627 if (chan_mask & MACIO_FLAG_SCCA_ON) {
628 fcr |= KL0_SCCA_ENABLE;
629 /* Don't enable line drivers for I2S modem */
630 if ((param & 0xfff) == PMAC_SCC_I2S1)
631 fcr &= ~KL0_SCC_A_INTF_ENABLE;
632 else
633 fcr |= KL0_SCC_A_INTF_ENABLE;
634 }
635 if (chan_mask & MACIO_FLAG_SCCB_ON) {
636 fcr |= KL0_SCCB_ENABLE;
637 /* Perform irda specific inits */
638 if ((param & 0xfff) == PMAC_SCC_IRDA) {
639 fcr &= ~KL0_SCC_B_INTF_ENABLE;
640 fcr |= KL0_IRDA_ENABLE;
641 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
642 fcr |= KL0_IRDA_SOURCE1_SEL;
643 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
644 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
645 need_reset_irda = 1;
646 } else
647 fcr |= KL0_SCC_B_INTF_ENABLE;
648 }
649 MACIO_OUT32(KEYLARGO_FCR0, fcr);
650 macio->flags |= chan_mask;
651 if (need_reset_scc) {
652 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
653 (void)MACIO_IN32(KEYLARGO_FCR0);
654 UNLOCK(flags);
655 mdelay(15);
656 LOCK(flags);
657 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
658 }
659 if (need_reset_irda) {
660 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
661 (void)MACIO_IN32(KEYLARGO_FCR0);
662 UNLOCK(flags);
663 mdelay(15);
664 LOCK(flags);
665 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
666 }
667 UNLOCK(flags);
668 if (param & PMAC_SCC_FLAG_XMON)
669 macio->flags |= MACIO_FLAG_SCC_LOCKED;
670 } else {
671 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
672 return -EPERM;
673 LOCK(flags);
674 fcr = MACIO_IN32(KEYLARGO_FCR0);
675 if (chan_mask & MACIO_FLAG_SCCA_ON)
676 fcr &= ~KL0_SCCA_ENABLE;
677 if (chan_mask & MACIO_FLAG_SCCB_ON) {
678 fcr &= ~KL0_SCCB_ENABLE;
679 /* Perform irda specific clears */
680 if ((param & 0xfff) == PMAC_SCC_IRDA) {
681 fcr &= ~KL0_IRDA_ENABLE;
682 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
683 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
684 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
685 }
686 }
687 MACIO_OUT32(KEYLARGO_FCR0, fcr);
688 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
689 fcr &= ~KL0_SCC_CELL_ENABLE;
690 MACIO_OUT32(KEYLARGO_FCR0, fcr);
691 }
692 macio->flags &= ~(chan_mask);
693 UNLOCK(flags);
694 mdelay(10);
695 }
696 return 0;
697 }
698
699 static long
core99_modem_enable(struct device_node * node,long param,long value)700 core99_modem_enable(struct device_node *node, long param, long value)
701 {
702 struct macio_chip* macio;
703 u8 gpio;
704 unsigned long flags;
705
706 /* Hack for internal USB modem */
707 if (node == NULL) {
708 if (macio_chips[0].type != macio_keylargo)
709 return -ENODEV;
710 node = macio_chips[0].of_node;
711 }
712 macio = macio_find(node, 0);
713 if (!macio)
714 return -ENODEV;
715 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
716 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
717 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
718
719 if (!value) {
720 LOCK(flags);
721 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
722 UNLOCK(flags);
723 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
724 mdelay(250);
725 }
726 LOCK(flags);
727 if (value) {
728 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
729 UNLOCK(flags);
730 (void)MACIO_IN32(KEYLARGO_FCR2);
731 mdelay(250);
732 } else {
733 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
734 UNLOCK(flags);
735 }
736 if (value) {
737 LOCK(flags);
738 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
739 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
740 UNLOCK(flags); mdelay(250); LOCK(flags);
741 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
742 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
743 UNLOCK(flags); mdelay(250); LOCK(flags);
744 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
745 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
746 UNLOCK(flags); mdelay(250);
747 }
748 return 0;
749 }
750
751 static long
pangea_modem_enable(struct device_node * node,long param,long value)752 pangea_modem_enable(struct device_node *node, long param, long value)
753 {
754 struct macio_chip* macio;
755 u8 gpio;
756 unsigned long flags;
757
758 /* Hack for internal USB modem */
759 if (node == NULL) {
760 if (macio_chips[0].type != macio_pangea &&
761 macio_chips[0].type != macio_intrepid)
762 return -ENODEV;
763 node = macio_chips[0].of_node;
764 }
765 macio = macio_find(node, 0);
766 if (!macio)
767 return -ENODEV;
768 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
769 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
770 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
771
772 if (!value) {
773 LOCK(flags);
774 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
775 UNLOCK(flags);
776 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
777 mdelay(250);
778 }
779 LOCK(flags);
780 if (value) {
781 MACIO_OUT8(KL_GPIO_MODEM_POWER,
782 KEYLARGO_GPIO_OUTPUT_ENABLE);
783 UNLOCK(flags);
784 (void)MACIO_IN32(KEYLARGO_FCR2);
785 mdelay(250);
786 } else {
787 MACIO_OUT8(KL_GPIO_MODEM_POWER,
788 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
789 UNLOCK(flags);
790 }
791 if (value) {
792 LOCK(flags);
793 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
794 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
795 UNLOCK(flags); mdelay(250); LOCK(flags);
796 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
797 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
798 UNLOCK(flags); mdelay(250); LOCK(flags);
799 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
800 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
801 UNLOCK(flags); mdelay(250);
802 }
803 return 0;
804 }
805
806 static long
core99_ata100_enable(struct device_node * node,long value)807 core99_ata100_enable(struct device_node *node, long value)
808 {
809 unsigned long flags;
810 struct pci_dev *pdev = NULL;
811 u8 pbus, pid;
812 int rc;
813
814 if (uninorth_rev < 0x24)
815 return -ENODEV;
816
817 LOCK(flags);
818 if (value)
819 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
820 else
821 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
822 (void)UN_IN(UNI_N_CLOCK_CNTL);
823 UNLOCK(flags);
824 udelay(20);
825
826 if (value) {
827 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
828 pdev = pci_get_domain_bus_and_slot(0, pbus, pid);
829 if (pdev == NULL)
830 return 0;
831 rc = pci_enable_device(pdev);
832 if (rc == 0)
833 pci_set_master(pdev);
834 pci_dev_put(pdev);
835 if (rc)
836 return rc;
837 }
838 return 0;
839 }
840
841 static long
core99_ide_enable(struct device_node * node,long param,long value)842 core99_ide_enable(struct device_node *node, long param, long value)
843 {
844 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
845 * based ata-100
846 */
847 switch(param) {
848 case 0:
849 return simple_feature_tweak(node, macio_unknown,
850 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
851 case 1:
852 return simple_feature_tweak(node, macio_unknown,
853 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
854 case 2:
855 return simple_feature_tweak(node, macio_unknown,
856 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
857 case 3:
858 return core99_ata100_enable(node, value);
859 default:
860 return -ENODEV;
861 }
862 }
863
864 static long
core99_ide_reset(struct device_node * node,long param,long value)865 core99_ide_reset(struct device_node *node, long param, long value)
866 {
867 switch(param) {
868 case 0:
869 return simple_feature_tweak(node, macio_unknown,
870 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
871 case 1:
872 return simple_feature_tweak(node, macio_unknown,
873 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
874 case 2:
875 return simple_feature_tweak(node, macio_unknown,
876 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
877 default:
878 return -ENODEV;
879 }
880 }
881
882 static long
core99_gmac_enable(struct device_node * node,long param,long value)883 core99_gmac_enable(struct device_node *node, long param, long value)
884 {
885 unsigned long flags;
886
887 LOCK(flags);
888 if (value)
889 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
890 else
891 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
892 (void)UN_IN(UNI_N_CLOCK_CNTL);
893 UNLOCK(flags);
894 udelay(20);
895
896 return 0;
897 }
898
899 static long
core99_gmac_phy_reset(struct device_node * node,long param,long value)900 core99_gmac_phy_reset(struct device_node *node, long param, long value)
901 {
902 unsigned long flags;
903 struct macio_chip *macio;
904
905 macio = &macio_chips[0];
906 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
907 macio->type != macio_intrepid)
908 return -ENODEV;
909
910 LOCK(flags);
911 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
912 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
913 UNLOCK(flags);
914 mdelay(10);
915 LOCK(flags);
916 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
917 KEYLARGO_GPIO_OUTOUT_DATA);
918 UNLOCK(flags);
919 mdelay(10);
920
921 return 0;
922 }
923
924 static long
core99_sound_chip_enable(struct device_node * node,long param,long value)925 core99_sound_chip_enable(struct device_node *node, long param, long value)
926 {
927 struct macio_chip* macio;
928 unsigned long flags;
929
930 macio = macio_find(node, 0);
931 if (!macio)
932 return -ENODEV;
933
934 /* Do a better probe code, screamer G4 desktops &
935 * iMacs can do that too, add a recalibrate in
936 * the driver as well
937 */
938 if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
939 pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
940 LOCK(flags);
941 if (value)
942 MACIO_OUT8(KL_GPIO_SOUND_POWER,
943 KEYLARGO_GPIO_OUTPUT_ENABLE |
944 KEYLARGO_GPIO_OUTOUT_DATA);
945 else
946 MACIO_OUT8(KL_GPIO_SOUND_POWER,
947 KEYLARGO_GPIO_OUTPUT_ENABLE);
948 (void)MACIO_IN8(KL_GPIO_SOUND_POWER);
949 UNLOCK(flags);
950 }
951 return 0;
952 }
953
954 static long
core99_airport_enable(struct device_node * node,long param,long value)955 core99_airport_enable(struct device_node *node, long param, long value)
956 {
957 struct macio_chip* macio;
958 unsigned long flags;
959 int state;
960
961 macio = macio_find(node, 0);
962 if (!macio)
963 return -ENODEV;
964
965 /* Hint: we allow passing of macio itself for the sake of the
966 * sleep code
967 */
968 if (node != macio->of_node &&
969 (!node->parent || node->parent != macio->of_node))
970 return -ENODEV;
971 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
972 if (value == state)
973 return 0;
974 if (value) {
975 /* This code is a reproduction of OF enable-cardslot
976 * and init-wireless methods, slightly hacked until
977 * I got it working.
978 */
979 LOCK(flags);
980 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
981 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
982 UNLOCK(flags);
983 mdelay(10);
984 LOCK(flags);
985 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
986 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
987 UNLOCK(flags);
988
989 mdelay(10);
990
991 LOCK(flags);
992 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
993 (void)MACIO_IN32(KEYLARGO_FCR2);
994 udelay(10);
995 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
996 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
997 udelay(10);
998 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
999 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
1000 udelay(10);
1001 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
1002 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
1003 udelay(10);
1004 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
1005 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
1006 udelay(10);
1007 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
1008 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
1009 UNLOCK(flags);
1010 udelay(10);
1011 MACIO_OUT32(0x1c000, 0);
1012 mdelay(1);
1013 MACIO_OUT8(0x1a3e0, 0x41);
1014 (void)MACIO_IN8(0x1a3e0);
1015 udelay(10);
1016 LOCK(flags);
1017 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
1018 (void)MACIO_IN32(KEYLARGO_FCR2);
1019 UNLOCK(flags);
1020 mdelay(100);
1021
1022 macio->flags |= MACIO_FLAG_AIRPORT_ON;
1023 } else {
1024 LOCK(flags);
1025 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1026 (void)MACIO_IN32(KEYLARGO_FCR2);
1027 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
1028 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
1029 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
1030 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
1031 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
1032 (void)MACIO_IN8(KL_GPIO_AIRPORT_4);
1033 UNLOCK(flags);
1034
1035 macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
1036 }
1037 return 0;
1038 }
1039
1040 #ifdef CONFIG_SMP
1041 static long
core99_reset_cpu(struct device_node * node,long param,long value)1042 core99_reset_cpu(struct device_node *node, long param, long value)
1043 {
1044 unsigned int reset_io = 0;
1045 unsigned long flags;
1046 struct macio_chip *macio;
1047 struct device_node *np;
1048 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0,
1049 KL_GPIO_RESET_CPU1,
1050 KL_GPIO_RESET_CPU2,
1051 KL_GPIO_RESET_CPU3 };
1052
1053 macio = &macio_chips[0];
1054 if (macio->type != macio_keylargo)
1055 return -ENODEV;
1056
1057 for_each_of_cpu_node(np) {
1058 const u32 *rst = of_get_property(np, "soft-reset", NULL);
1059 if (!rst)
1060 continue;
1061 if (param == of_get_cpu_hwid(np, 0)) {
1062 of_node_put(np);
1063 reset_io = *rst;
1064 break;
1065 }
1066 }
1067 if (np == NULL || reset_io == 0)
1068 reset_io = dflt_reset_lines[param];
1069
1070 LOCK(flags);
1071 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1072 (void)MACIO_IN8(reset_io);
1073 udelay(1);
1074 MACIO_OUT8(reset_io, 0);
1075 (void)MACIO_IN8(reset_io);
1076 UNLOCK(flags);
1077
1078 return 0;
1079 }
1080 #endif /* CONFIG_SMP */
1081
1082 static long
core99_usb_enable(struct device_node * node,long param,long value)1083 core99_usb_enable(struct device_node *node, long param, long value)
1084 {
1085 struct macio_chip *macio;
1086 unsigned long flags;
1087 const char *prop;
1088 int number;
1089 u32 reg;
1090
1091 macio = &macio_chips[0];
1092 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1093 macio->type != macio_intrepid)
1094 return -ENODEV;
1095
1096 prop = of_get_property(node, "AAPL,clock-id", NULL);
1097 if (!prop)
1098 return -ENODEV;
1099 if (strncmp(prop, "usb0u048", 8) == 0)
1100 number = 0;
1101 else if (strncmp(prop, "usb1u148", 8) == 0)
1102 number = 2;
1103 else if (strncmp(prop, "usb2u248", 8) == 0)
1104 number = 4;
1105 else
1106 return -ENODEV;
1107
1108 /* Sorry for the brute-force locking, but this is only used during
1109 * sleep and the timing seem to be critical
1110 */
1111 LOCK(flags);
1112 if (value) {
1113 /* Turn ON */
1114 if (number == 0) {
1115 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1116 (void)MACIO_IN32(KEYLARGO_FCR0);
1117 UNLOCK(flags);
1118 mdelay(1);
1119 LOCK(flags);
1120 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1121 } else if (number == 2) {
1122 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1123 UNLOCK(flags);
1124 (void)MACIO_IN32(KEYLARGO_FCR0);
1125 mdelay(1);
1126 LOCK(flags);
1127 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1128 } else if (number == 4) {
1129 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1130 UNLOCK(flags);
1131 (void)MACIO_IN32(KEYLARGO_FCR1);
1132 mdelay(1);
1133 LOCK(flags);
1134 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1135 }
1136 if (number < 4) {
1137 reg = MACIO_IN32(KEYLARGO_FCR4);
1138 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1139 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
1140 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1141 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
1142 MACIO_OUT32(KEYLARGO_FCR4, reg);
1143 (void)MACIO_IN32(KEYLARGO_FCR4);
1144 udelay(10);
1145 } else {
1146 reg = MACIO_IN32(KEYLARGO_FCR3);
1147 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1148 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1149 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1150 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1151 MACIO_OUT32(KEYLARGO_FCR3, reg);
1152 (void)MACIO_IN32(KEYLARGO_FCR3);
1153 udelay(10);
1154 }
1155 if (macio->type == macio_intrepid) {
1156 /* wait for clock stopped bits to clear */
1157 u32 test0 = 0, test1 = 0;
1158 u32 status0, status1;
1159 int timeout = 1000;
1160
1161 UNLOCK(flags);
1162 switch (number) {
1163 case 0:
1164 test0 = UNI_N_CLOCK_STOPPED_USB0;
1165 test1 = UNI_N_CLOCK_STOPPED_USB0PCI;
1166 break;
1167 case 2:
1168 test0 = UNI_N_CLOCK_STOPPED_USB1;
1169 test1 = UNI_N_CLOCK_STOPPED_USB1PCI;
1170 break;
1171 case 4:
1172 test0 = UNI_N_CLOCK_STOPPED_USB2;
1173 test1 = UNI_N_CLOCK_STOPPED_USB2PCI;
1174 break;
1175 }
1176 do {
1177 if (--timeout <= 0) {
1178 printk(KERN_ERR "core99_usb_enable: "
1179 "Timeout waiting for clocks\n");
1180 break;
1181 }
1182 mdelay(1);
1183 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0);
1184 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1);
1185 } while ((status0 & test0) | (status1 & test1));
1186 LOCK(flags);
1187 }
1188 } else {
1189 /* Turn OFF */
1190 if (number < 4) {
1191 reg = MACIO_IN32(KEYLARGO_FCR4);
1192 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1193 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
1194 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1195 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
1196 MACIO_OUT32(KEYLARGO_FCR4, reg);
1197 (void)MACIO_IN32(KEYLARGO_FCR4);
1198 udelay(1);
1199 } else {
1200 reg = MACIO_IN32(KEYLARGO_FCR3);
1201 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1202 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1203 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1204 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1205 MACIO_OUT32(KEYLARGO_FCR3, reg);
1206 (void)MACIO_IN32(KEYLARGO_FCR3);
1207 udelay(1);
1208 }
1209 if (number == 0) {
1210 if (macio->type != macio_intrepid)
1211 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1212 (void)MACIO_IN32(KEYLARGO_FCR0);
1213 udelay(1);
1214 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1215 (void)MACIO_IN32(KEYLARGO_FCR0);
1216 } else if (number == 2) {
1217 if (macio->type != macio_intrepid)
1218 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1219 (void)MACIO_IN32(KEYLARGO_FCR0);
1220 udelay(1);
1221 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1222 (void)MACIO_IN32(KEYLARGO_FCR0);
1223 } else if (number == 4) {
1224 udelay(1);
1225 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1226 (void)MACIO_IN32(KEYLARGO_FCR1);
1227 }
1228 udelay(1);
1229 }
1230 UNLOCK(flags);
1231
1232 return 0;
1233 }
1234
1235 static long
core99_firewire_enable(struct device_node * node,long param,long value)1236 core99_firewire_enable(struct device_node *node, long param, long value)
1237 {
1238 unsigned long flags;
1239 struct macio_chip *macio;
1240
1241 macio = &macio_chips[0];
1242 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1243 macio->type != macio_intrepid)
1244 return -ENODEV;
1245 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1246 return -ENODEV;
1247
1248 LOCK(flags);
1249 if (value) {
1250 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1251 (void)UN_IN(UNI_N_CLOCK_CNTL);
1252 } else {
1253 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1254 (void)UN_IN(UNI_N_CLOCK_CNTL);
1255 }
1256 UNLOCK(flags);
1257 mdelay(1);
1258
1259 return 0;
1260 }
1261
1262 static long
core99_firewire_cable_power(struct device_node * node,long param,long value)1263 core99_firewire_cable_power(struct device_node *node, long param, long value)
1264 {
1265 unsigned long flags;
1266 struct macio_chip *macio;
1267
1268 /* Trick: we allow NULL node */
1269 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
1270 return -ENODEV;
1271 macio = &macio_chips[0];
1272 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1273 macio->type != macio_intrepid)
1274 return -ENODEV;
1275 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1276 return -ENODEV;
1277
1278 LOCK(flags);
1279 if (value) {
1280 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
1281 MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
1282 udelay(10);
1283 } else {
1284 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
1285 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
1286 }
1287 UNLOCK(flags);
1288 mdelay(1);
1289
1290 return 0;
1291 }
1292
1293 static long
intrepid_aack_delay_enable(struct device_node * node,long param,long value)1294 intrepid_aack_delay_enable(struct device_node *node, long param, long value)
1295 {
1296 unsigned long flags;
1297
1298 if (uninorth_rev < 0xd2)
1299 return -ENODEV;
1300
1301 LOCK(flags);
1302 if (param)
1303 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1304 else
1305 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1306 UNLOCK(flags);
1307
1308 return 0;
1309 }
1310
1311
1312 #endif /* CONFIG_PPC64 */
1313
1314 static long
core99_read_gpio(struct device_node * node,long param,long value)1315 core99_read_gpio(struct device_node *node, long param, long value)
1316 {
1317 struct macio_chip *macio = &macio_chips[0];
1318
1319 return MACIO_IN8(param);
1320 }
1321
1322
1323 static long
core99_write_gpio(struct device_node * node,long param,long value)1324 core99_write_gpio(struct device_node *node, long param, long value)
1325 {
1326 struct macio_chip *macio = &macio_chips[0];
1327
1328 MACIO_OUT8(param, (u8)(value & 0xff));
1329 return 0;
1330 }
1331
1332 #ifdef CONFIG_PPC64
g5_gmac_enable(struct device_node * node,long param,long value)1333 static long g5_gmac_enable(struct device_node *node, long param, long value)
1334 {
1335 struct macio_chip *macio = &macio_chips[0];
1336 unsigned long flags;
1337
1338 if (node == NULL)
1339 return -ENODEV;
1340
1341 LOCK(flags);
1342 if (value) {
1343 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1344 mb();
1345 k2_skiplist[0] = NULL;
1346 } else {
1347 k2_skiplist[0] = node;
1348 mb();
1349 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1350 }
1351
1352 UNLOCK(flags);
1353 mdelay(1);
1354
1355 return 0;
1356 }
1357
g5_fw_enable(struct device_node * node,long param,long value)1358 static long g5_fw_enable(struct device_node *node, long param, long value)
1359 {
1360 struct macio_chip *macio = &macio_chips[0];
1361 unsigned long flags;
1362
1363 if (node == NULL)
1364 return -ENODEV;
1365
1366 LOCK(flags);
1367 if (value) {
1368 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1369 mb();
1370 k2_skiplist[1] = NULL;
1371 } else {
1372 k2_skiplist[1] = node;
1373 mb();
1374 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1375 }
1376
1377 UNLOCK(flags);
1378 mdelay(1);
1379
1380 return 0;
1381 }
1382
g5_mpic_enable(struct device_node * node,long param,long value)1383 static long g5_mpic_enable(struct device_node *node, long param, long value)
1384 {
1385 unsigned long flags;
1386 struct device_node *parent = of_get_parent(node);
1387 int is_u3;
1388
1389 if (parent == NULL)
1390 return 0;
1391 is_u3 = of_node_name_eq(parent, "u3") || of_node_name_eq(parent, "u4");
1392 of_node_put(parent);
1393 if (!is_u3)
1394 return 0;
1395
1396 LOCK(flags);
1397 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
1398 UNLOCK(flags);
1399
1400 return 0;
1401 }
1402
g5_eth_phy_reset(struct device_node * node,long param,long value)1403 static long g5_eth_phy_reset(struct device_node *node, long param, long value)
1404 {
1405 struct macio_chip *macio = &macio_chips[0];
1406 struct device_node *phy;
1407 int need_reset;
1408
1409 /*
1410 * We must not reset the combo PHYs, only the BCM5221 found in
1411 * the iMac G5.
1412 */
1413 phy = of_get_next_child(node, NULL);
1414 if (!phy)
1415 return -ENODEV;
1416 need_reset = of_device_is_compatible(phy, "B5221");
1417 of_node_put(phy);
1418 if (!need_reset)
1419 return 0;
1420
1421 /* PHY reset is GPIO 29, not in device-tree unfortunately */
1422 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29,
1423 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
1424 /* Thankfully, this is now always called at a time when we can
1425 * schedule by sungem.
1426 */
1427 msleep(10);
1428 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0);
1429
1430 return 0;
1431 }
1432
g5_i2s_enable(struct device_node * node,long param,long value)1433 static long g5_i2s_enable(struct device_node *node, long param, long value)
1434 {
1435 /* Very crude implementation for now */
1436 struct macio_chip *macio = &macio_chips[0];
1437 unsigned long flags;
1438 int cell;
1439 u32 fcrs[3][3] = {
1440 { 0,
1441 K2_FCR1_I2S0_CELL_ENABLE |
1442 K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE,
1443 KL3_I2S0_CLK18_ENABLE
1444 },
1445 { KL0_SCC_A_INTF_ENABLE,
1446 K2_FCR1_I2S1_CELL_ENABLE |
1447 K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE,
1448 KL3_I2S1_CLK18_ENABLE
1449 },
1450 { KL0_SCC_B_INTF_ENABLE,
1451 SH_FCR1_I2S2_CELL_ENABLE |
1452 SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE,
1453 SH_FCR3_I2S2_CLK18_ENABLE
1454 },
1455 };
1456
1457 if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
1458 return -ENODEV;
1459 if (strncmp(node->name, "i2s-", 4))
1460 return -ENODEV;
1461 cell = node->name[4] - 'a';
1462 switch(cell) {
1463 case 0:
1464 case 1:
1465 break;
1466 case 2:
1467 if (macio->type == macio_shasta)
1468 break;
1469 fallthrough;
1470 default:
1471 return -ENODEV;
1472 }
1473
1474 LOCK(flags);
1475 if (value) {
1476 MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]);
1477 MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]);
1478 MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]);
1479 } else {
1480 MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]);
1481 MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]);
1482 MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]);
1483 }
1484 udelay(10);
1485 UNLOCK(flags);
1486
1487 return 0;
1488 }
1489
1490
1491 #ifdef CONFIG_SMP
g5_reset_cpu(struct device_node * node,long param,long value)1492 static long g5_reset_cpu(struct device_node *node, long param, long value)
1493 {
1494 unsigned int reset_io = 0;
1495 unsigned long flags;
1496 struct macio_chip *macio;
1497 struct device_node *np;
1498
1499 macio = &macio_chips[0];
1500 if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
1501 return -ENODEV;
1502
1503 for_each_of_cpu_node(np) {
1504 const u32 *rst = of_get_property(np, "soft-reset", NULL);
1505 if (!rst)
1506 continue;
1507 if (param == of_get_cpu_hwid(np, 0)) {
1508 of_node_put(np);
1509 reset_io = *rst;
1510 break;
1511 }
1512 }
1513 if (np == NULL || reset_io == 0)
1514 return -ENODEV;
1515
1516 LOCK(flags);
1517 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1518 (void)MACIO_IN8(reset_io);
1519 udelay(1);
1520 MACIO_OUT8(reset_io, 0);
1521 (void)MACIO_IN8(reset_io);
1522 UNLOCK(flags);
1523
1524 return 0;
1525 }
1526 #endif /* CONFIG_SMP */
1527
1528 /*
1529 * This can be called from pmac_smp so isn't static
1530 *
1531 * This takes the second CPU off the bus on dual CPU machines
1532 * running UP
1533 */
g5_phy_disable_cpu1(void)1534 void __init g5_phy_disable_cpu1(void)
1535 {
1536 if (uninorth_maj == 3)
1537 UN_OUT(U3_API_PHY_CONFIG_1, 0);
1538 }
1539 #endif /* CONFIG_PPC64 */
1540
1541 #ifndef CONFIG_PPC64
1542
1543
1544 #ifdef CONFIG_PM
1545 static u32 save_gpio_levels[2];
1546 static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
1547 static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
1548 static u32 save_unin_clock_ctl;
1549
keylargo_shutdown(struct macio_chip * macio,int sleep_mode)1550 static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode)
1551 {
1552 u32 temp;
1553
1554 if (sleep_mode) {
1555 mdelay(1);
1556 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
1557 (void)MACIO_IN32(KEYLARGO_FCR0);
1558 mdelay(1);
1559 }
1560
1561 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1562 KL0_SCC_CELL_ENABLE |
1563 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
1564 KL0_IRDA_CLK19_ENABLE);
1565
1566 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
1567 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
1568
1569 MACIO_BIC(KEYLARGO_FCR1,
1570 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1571 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1572 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1573 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1574 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1575 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
1576 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
1577 KL1_UIDE_ENABLE);
1578
1579 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1580 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
1581
1582 temp = MACIO_IN32(KEYLARGO_FCR3);
1583 if (macio->rev >= 2) {
1584 temp |= KL3_SHUTDOWN_PLL2X;
1585 if (sleep_mode)
1586 temp |= KL3_SHUTDOWN_PLL_TOTAL;
1587 }
1588
1589 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1590 KL3_SHUTDOWN_PLLKW35;
1591 if (sleep_mode)
1592 temp |= KL3_SHUTDOWN_PLLKW12;
1593 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
1594 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1595 if (sleep_mode)
1596 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
1597 MACIO_OUT32(KEYLARGO_FCR3, temp);
1598
1599 /* Flush posted writes & wait a bit */
1600 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1601 }
1602
pangea_shutdown(struct macio_chip * macio,int sleep_mode)1603 static void pangea_shutdown(struct macio_chip *macio, int sleep_mode)
1604 {
1605 u32 temp;
1606
1607 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1608 KL0_SCC_CELL_ENABLE |
1609 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1610
1611 MACIO_BIC(KEYLARGO_FCR1,
1612 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1613 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1614 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1615 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1616 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1617 KL1_UIDE_ENABLE);
1618 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1619 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1620
1621 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1622
1623 temp = MACIO_IN32(KEYLARGO_FCR3);
1624 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1625 KL3_SHUTDOWN_PLLKW35;
1626 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
1627 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
1628 if (sleep_mode)
1629 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
1630 MACIO_OUT32(KEYLARGO_FCR3, temp);
1631
1632 /* Flush posted writes & wait a bit */
1633 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1634 }
1635
intrepid_shutdown(struct macio_chip * macio,int sleep_mode)1636 static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode)
1637 {
1638 u32 temp;
1639
1640 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1641 KL0_SCC_CELL_ENABLE);
1642
1643 MACIO_BIC(KEYLARGO_FCR1,
1644 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1645 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1646 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1647 KL1_EIDE0_ENABLE);
1648 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1649 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1650
1651 temp = MACIO_IN32(KEYLARGO_FCR3);
1652 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
1653 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1654 if (sleep_mode)
1655 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
1656 MACIO_OUT32(KEYLARGO_FCR3, temp);
1657
1658 /* Flush posted writes & wait a bit */
1659 (void)MACIO_IN32(KEYLARGO_FCR0);
1660 mdelay(10);
1661 }
1662
1663
1664 static int
core99_sleep(void)1665 core99_sleep(void)
1666 {
1667 struct macio_chip *macio;
1668 int i;
1669
1670 macio = &macio_chips[0];
1671 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1672 macio->type != macio_intrepid)
1673 return -ENODEV;
1674
1675 /* We power off the wireless slot in case it was not done
1676 * by the driver. We don't power it on automatically however
1677 */
1678 if (macio->flags & MACIO_FLAG_AIRPORT_ON)
1679 core99_airport_enable(macio->of_node, 0, 0);
1680
1681 /* We power off the FW cable. Should be done by the driver... */
1682 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
1683 core99_firewire_enable(NULL, 0, 0);
1684 core99_firewire_cable_power(NULL, 0, 0);
1685 }
1686
1687 /* We make sure int. modem is off (in case driver lost it) */
1688 if (macio->type == macio_keylargo)
1689 core99_modem_enable(macio->of_node, 0, 0);
1690 else
1691 pangea_modem_enable(macio->of_node, 0, 0);
1692
1693 /* We make sure the sound is off as well */
1694 core99_sound_chip_enable(macio->of_node, 0, 0);
1695
1696 /*
1697 * Save various bits of KeyLargo
1698 */
1699
1700 /* Save the state of the various GPIOs */
1701 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
1702 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
1703 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1704 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
1705 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1706 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
1707
1708 /* Save the FCRs */
1709 if (macio->type == macio_keylargo)
1710 save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
1711 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
1712 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
1713 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
1714 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
1715 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
1716 if (macio->type == macio_pangea || macio->type == macio_intrepid)
1717 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
1718
1719 /* Save state & config of DBDMA channels */
1720 dbdma_save(macio, save_dbdma);
1721
1722 /*
1723 * Turn off as much as we can
1724 */
1725 if (macio->type == macio_pangea)
1726 pangea_shutdown(macio, 1);
1727 else if (macio->type == macio_intrepid)
1728 intrepid_shutdown(macio, 1);
1729 else if (macio->type == macio_keylargo)
1730 keylargo_shutdown(macio, 1);
1731
1732 /*
1733 * Put the host bridge to sleep
1734 */
1735
1736 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
1737 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
1738 * enabled !
1739 */
1740 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
1741 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
1742 udelay(100);
1743 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1744 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
1745 mdelay(10);
1746
1747 /*
1748 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
1749 */
1750 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1751 MACIO_BIS(0x506e0, 0x00400000);
1752 MACIO_BIS(0x506e0, 0x80000000);
1753 }
1754 return 0;
1755 }
1756
1757 static int
core99_wake_up(void)1758 core99_wake_up(void)
1759 {
1760 struct macio_chip *macio;
1761 int i;
1762
1763 macio = &macio_chips[0];
1764 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1765 macio->type != macio_intrepid)
1766 return -ENODEV;
1767
1768 /*
1769 * Wakeup the host bridge
1770 */
1771 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1772 udelay(10);
1773 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1774 udelay(10);
1775
1776 /*
1777 * Restore KeyLargo
1778 */
1779
1780 if (macio->type == macio_keylargo) {
1781 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
1782 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
1783 }
1784 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
1785 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
1786 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
1787 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
1788 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
1789 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
1790 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
1791 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
1792 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
1793 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
1794 if (macio->type == macio_pangea || macio->type == macio_intrepid) {
1795 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
1796 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
1797 }
1798
1799 dbdma_restore(macio, save_dbdma);
1800
1801 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
1802 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
1803 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1804 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
1805 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1806 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
1807
1808 /* FIXME more black magic with OpenPIC ... */
1809 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1810 MACIO_BIC(0x506e0, 0x00400000);
1811 MACIO_BIC(0x506e0, 0x80000000);
1812 }
1813
1814 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1815 udelay(100);
1816
1817 return 0;
1818 }
1819
1820 #endif /* CONFIG_PM */
1821
1822 static long
core99_sleep_state(struct device_node * node,long param,long value)1823 core99_sleep_state(struct device_node *node, long param, long value)
1824 {
1825 /* Param == 1 means to enter the "fake sleep" mode that is
1826 * used for CPU speed switch
1827 */
1828 if (param == 1) {
1829 if (value == 1) {
1830 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1831 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
1832 } else {
1833 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1834 udelay(10);
1835 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1836 udelay(10);
1837 }
1838 return 0;
1839 }
1840 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
1841 return -EPERM;
1842
1843 #ifdef CONFIG_PM
1844 if (value == 1)
1845 return core99_sleep();
1846 else if (value == 0)
1847 return core99_wake_up();
1848
1849 #endif /* CONFIG_PM */
1850 return 0;
1851 }
1852
1853 #endif /* CONFIG_PPC64 */
1854
1855 static long
generic_dev_can_wake(struct device_node * node,long param,long value)1856 generic_dev_can_wake(struct device_node *node, long param, long value)
1857 {
1858 /* Todo: eventually check we are really dealing with on-board
1859 * video device ...
1860 */
1861
1862 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
1863 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
1864 return 0;
1865 }
1866
generic_get_mb_info(struct device_node * node,long param,long value)1867 static long generic_get_mb_info(struct device_node *node, long param, long value)
1868 {
1869 switch(param) {
1870 case PMAC_MB_INFO_MODEL:
1871 return pmac_mb.model_id;
1872 case PMAC_MB_INFO_FLAGS:
1873 return pmac_mb.board_flags;
1874 case PMAC_MB_INFO_NAME:
1875 /* hack hack hack... but should work */
1876 *((const char **)value) = pmac_mb.model_name;
1877 return 0;
1878 }
1879 return -EINVAL;
1880 }
1881
1882
1883 /*
1884 * Table definitions
1885 */
1886
1887 /* Used on any machine
1888 */
1889 static struct feature_table_entry any_features[] = {
1890 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
1891 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake },
1892 { 0, NULL }
1893 };
1894
1895 #ifndef CONFIG_PPC64
1896
1897 /* OHare based motherboards. Currently, we only use these on the
1898 * 2400,3400 and 3500 series powerbooks. Some older desktops seem
1899 * to have issues with turning on/off those asic cells
1900 */
1901 static struct feature_table_entry ohare_features[] = {
1902 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1903 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
1904 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
1905 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable},
1906 { PMAC_FTR_IDE_RESET, ohare_ide_reset},
1907 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state },
1908 { 0, NULL }
1909 };
1910
1911 /* Heathrow desktop machines (Beige G3).
1912 * Separated as some features couldn't be properly tested
1913 * and the serial port control bits appear to confuse it.
1914 */
1915 static struct feature_table_entry heathrow_desktop_features[] = {
1916 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1917 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1918 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1919 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1920 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1921 { 0, NULL }
1922 };
1923
1924 /* Heathrow based laptop, that is the Wallstreet and mainstreet
1925 * powerbooks.
1926 */
1927 static struct feature_table_entry heathrow_laptop_features[] = {
1928 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1929 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1930 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1931 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1932 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1933 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1934 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1935 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1936 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1937 { 0, NULL }
1938 };
1939
1940 /* Paddington based machines
1941 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
1942 */
1943 static struct feature_table_entry paddington_features[] = {
1944 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1945 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1946 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1947 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1948 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1949 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1950 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1951 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1952 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1953 { 0, NULL }
1954 };
1955
1956 /* Core99 & MacRISC 2 machines (all machines released since the
1957 * iBook (included), that is all AGP machines, except pangea
1958 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
1959 * used on iBook2 & iMac "flow power".
1960 */
1961 static struct feature_table_entry core99_features[] = {
1962 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1963 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
1964 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1965 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1966 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
1967 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
1968 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
1969 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
1970 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
1971 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
1972 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
1973 #ifdef CONFIG_PM
1974 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
1975 #endif
1976 #ifdef CONFIG_SMP
1977 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
1978 #endif /* CONFIG_SMP */
1979 { PMAC_FTR_READ_GPIO, core99_read_gpio },
1980 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
1981 { 0, NULL }
1982 };
1983
1984 /* RackMac
1985 */
1986 static struct feature_table_entry rackmac_features[] = {
1987 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1988 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1989 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1990 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
1991 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
1992 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
1993 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
1994 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
1995 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
1996 #ifdef CONFIG_SMP
1997 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
1998 #endif /* CONFIG_SMP */
1999 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2000 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2001 { 0, NULL }
2002 };
2003
2004 /* Pangea features
2005 */
2006 static struct feature_table_entry pangea_features[] = {
2007 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2008 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2009 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2010 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2011 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2012 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2013 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2014 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2015 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2016 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2017 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2018 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2019 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2020 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2021 { 0, NULL }
2022 };
2023
2024 /* Intrepid features
2025 */
2026 static struct feature_table_entry intrepid_features[] = {
2027 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2028 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2029 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2030 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2031 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2032 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2033 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2034 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2035 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2036 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2037 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2038 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2039 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2040 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2041 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable },
2042 { 0, NULL }
2043 };
2044
2045 #else /* CONFIG_PPC64 */
2046
2047 /* G5 features
2048 */
2049 static struct feature_table_entry g5_features[] = {
2050 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
2051 { PMAC_FTR_1394_ENABLE, g5_fw_enable },
2052 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
2053 { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset },
2054 { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable },
2055 #ifdef CONFIG_SMP
2056 { PMAC_FTR_RESET_CPU, g5_reset_cpu },
2057 #endif /* CONFIG_SMP */
2058 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2059 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2060 { 0, NULL }
2061 };
2062
2063 #endif /* CONFIG_PPC64 */
2064
2065 static struct pmac_mb_def pmac_mb_defs[] = {
2066 #ifndef CONFIG_PPC64
2067 /*
2068 * Desktops
2069 */
2070
2071 { "AAPL,8500", "PowerMac 8500/8600",
2072 PMAC_TYPE_PSURGE, NULL,
2073 0
2074 },
2075 { "AAPL,9500", "PowerMac 9500/9600",
2076 PMAC_TYPE_PSURGE, NULL,
2077 0
2078 },
2079 { "AAPL,7200", "PowerMac 7200",
2080 PMAC_TYPE_PSURGE, NULL,
2081 0
2082 },
2083 { "AAPL,7300", "PowerMac 7200/7300",
2084 PMAC_TYPE_PSURGE, NULL,
2085 0
2086 },
2087 { "AAPL,7500", "PowerMac 7500",
2088 PMAC_TYPE_PSURGE, NULL,
2089 0
2090 },
2091 { "AAPL,ShinerESB", "Apple Network Server",
2092 PMAC_TYPE_ANS, NULL,
2093 0
2094 },
2095 { "AAPL,e407", "Alchemy",
2096 PMAC_TYPE_ALCHEMY, NULL,
2097 0
2098 },
2099 { "AAPL,e411", "Gazelle",
2100 PMAC_TYPE_GAZELLE, NULL,
2101 0
2102 },
2103 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
2104 PMAC_TYPE_GOSSAMER, heathrow_desktop_features,
2105 0
2106 },
2107 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
2108 PMAC_TYPE_SILK, heathrow_desktop_features,
2109 0
2110 },
2111 { "PowerMac1,1", "Blue&White G3",
2112 PMAC_TYPE_YOSEMITE, paddington_features,
2113 0
2114 },
2115 { "PowerMac1,2", "PowerMac G4 PCI Graphics",
2116 PMAC_TYPE_YIKES, paddington_features,
2117 0
2118 },
2119 { "PowerMac2,1", "iMac FireWire",
2120 PMAC_TYPE_FW_IMAC, core99_features,
2121 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2122 },
2123 { "PowerMac2,2", "iMac FireWire",
2124 PMAC_TYPE_FW_IMAC, core99_features,
2125 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2126 },
2127 { "PowerMac3,1", "PowerMac G4 AGP Graphics",
2128 PMAC_TYPE_SAWTOOTH, core99_features,
2129 PMAC_MB_OLD_CORE99
2130 },
2131 { "PowerMac3,2", "PowerMac G4 AGP Graphics",
2132 PMAC_TYPE_SAWTOOTH, core99_features,
2133 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2134 },
2135 { "PowerMac3,3", "PowerMac G4 AGP Graphics",
2136 PMAC_TYPE_SAWTOOTH, core99_features,
2137 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2138 },
2139 { "PowerMac3,4", "PowerMac G4 Silver",
2140 PMAC_TYPE_QUICKSILVER, core99_features,
2141 PMAC_MB_MAY_SLEEP
2142 },
2143 { "PowerMac3,5", "PowerMac G4 Silver",
2144 PMAC_TYPE_QUICKSILVER, core99_features,
2145 PMAC_MB_MAY_SLEEP
2146 },
2147 { "PowerMac3,6", "PowerMac G4 Windtunnel",
2148 PMAC_TYPE_WINDTUNNEL, core99_features,
2149 PMAC_MB_MAY_SLEEP,
2150 },
2151 { "PowerMac4,1", "iMac \"Flower Power\"",
2152 PMAC_TYPE_PANGEA_IMAC, pangea_features,
2153 PMAC_MB_MAY_SLEEP
2154 },
2155 { "PowerMac4,2", "Flat panel iMac",
2156 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features,
2157 PMAC_MB_CAN_SLEEP
2158 },
2159 { "PowerMac4,4", "eMac",
2160 PMAC_TYPE_EMAC, core99_features,
2161 PMAC_MB_MAY_SLEEP
2162 },
2163 { "PowerMac5,1", "PowerMac G4 Cube",
2164 PMAC_TYPE_CUBE, core99_features,
2165 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2166 },
2167 { "PowerMac6,1", "Flat panel iMac",
2168 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2169 PMAC_MB_MAY_SLEEP,
2170 },
2171 { "PowerMac6,3", "Flat panel iMac",
2172 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2173 PMAC_MB_MAY_SLEEP,
2174 },
2175 { "PowerMac6,4", "eMac",
2176 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2177 PMAC_MB_MAY_SLEEP,
2178 },
2179 { "PowerMac10,1", "Mac mini",
2180 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2181 PMAC_MB_MAY_SLEEP,
2182 },
2183 { "PowerMac10,2", "Mac mini (Late 2005)",
2184 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2185 PMAC_MB_MAY_SLEEP,
2186 },
2187 { "iMac,1", "iMac (first generation)",
2188 PMAC_TYPE_ORIG_IMAC, paddington_features,
2189 0
2190 },
2191
2192 /*
2193 * Xserve's
2194 */
2195
2196 { "RackMac1,1", "XServe",
2197 PMAC_TYPE_RACKMAC, rackmac_features,
2198 0,
2199 },
2200 { "RackMac1,2", "XServe rev. 2",
2201 PMAC_TYPE_RACKMAC, rackmac_features,
2202 0,
2203 },
2204
2205 /*
2206 * Laptops
2207 */
2208
2209 { "AAPL,3400/2400", "PowerBook 3400",
2210 PMAC_TYPE_HOOPER, ohare_features,
2211 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2212 },
2213 { "AAPL,3500", "PowerBook 3500",
2214 PMAC_TYPE_KANGA, ohare_features,
2215 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2216 },
2217 { "AAPL,PowerBook1998", "PowerBook Wallstreet",
2218 PMAC_TYPE_WALLSTREET, heathrow_laptop_features,
2219 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2220 },
2221 { "PowerBook1,1", "PowerBook 101 (Lombard)",
2222 PMAC_TYPE_101_PBOOK, paddington_features,
2223 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2224 },
2225 { "PowerBook2,1", "iBook (first generation)",
2226 PMAC_TYPE_ORIG_IBOOK, core99_features,
2227 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2228 },
2229 { "PowerBook2,2", "iBook FireWire",
2230 PMAC_TYPE_FW_IBOOK, core99_features,
2231 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2232 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2233 },
2234 { "PowerBook3,1", "PowerBook Pismo",
2235 PMAC_TYPE_PISMO, core99_features,
2236 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2237 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2238 },
2239 { "PowerBook3,2", "PowerBook Titanium",
2240 PMAC_TYPE_TITANIUM, core99_features,
2241 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2242 },
2243 { "PowerBook3,3", "PowerBook Titanium II",
2244 PMAC_TYPE_TITANIUM2, core99_features,
2245 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2246 },
2247 { "PowerBook3,4", "PowerBook Titanium III",
2248 PMAC_TYPE_TITANIUM3, core99_features,
2249 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2250 },
2251 { "PowerBook3,5", "PowerBook Titanium IV",
2252 PMAC_TYPE_TITANIUM4, core99_features,
2253 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2254 },
2255 { "PowerBook4,1", "iBook 2",
2256 PMAC_TYPE_IBOOK2, pangea_features,
2257 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2258 },
2259 { "PowerBook4,2", "iBook 2",
2260 PMAC_TYPE_IBOOK2, pangea_features,
2261 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2262 },
2263 { "PowerBook4,3", "iBook 2 rev. 2",
2264 PMAC_TYPE_IBOOK2, pangea_features,
2265 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2266 },
2267 { "PowerBook5,1", "PowerBook G4 17\"",
2268 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2269 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2270 },
2271 { "PowerBook5,2", "PowerBook G4 15\"",
2272 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2273 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2274 },
2275 { "PowerBook5,3", "PowerBook G4 17\"",
2276 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2277 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2278 },
2279 { "PowerBook5,4", "PowerBook G4 15\"",
2280 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2281 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2282 },
2283 { "PowerBook5,5", "PowerBook G4 17\"",
2284 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2285 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2286 },
2287 { "PowerBook5,6", "PowerBook G4 15\"",
2288 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2289 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2290 },
2291 { "PowerBook5,7", "PowerBook G4 17\"",
2292 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2293 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2294 },
2295 { "PowerBook5,8", "PowerBook G4 15\"",
2296 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2297 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE,
2298 },
2299 { "PowerBook5,9", "PowerBook G4 17\"",
2300 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2301 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE,
2302 },
2303 { "PowerBook6,1", "PowerBook G4 12\"",
2304 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2305 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2306 },
2307 { "PowerBook6,2", "PowerBook G4",
2308 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2309 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2310 },
2311 { "PowerBook6,3", "iBook G4",
2312 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2313 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2314 },
2315 { "PowerBook6,4", "PowerBook G4 12\"",
2316 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2317 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2318 },
2319 { "PowerBook6,5", "iBook G4",
2320 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2321 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2322 },
2323 { "PowerBook6,7", "iBook G4",
2324 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2325 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2326 },
2327 { "PowerBook6,8", "PowerBook G4 12\"",
2328 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2329 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2330 },
2331 #else /* CONFIG_PPC64 */
2332 { "PowerMac7,2", "PowerMac G5",
2333 PMAC_TYPE_POWERMAC_G5, g5_features,
2334 0,
2335 },
2336 { "PowerMac7,3", "PowerMac G5",
2337 PMAC_TYPE_POWERMAC_G5, g5_features,
2338 0,
2339 },
2340 { "PowerMac8,1", "iMac G5",
2341 PMAC_TYPE_IMAC_G5, g5_features,
2342 0,
2343 },
2344 { "PowerMac9,1", "PowerMac G5",
2345 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2346 0,
2347 },
2348 { "PowerMac11,2", "PowerMac G5 Dual Core",
2349 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2350 0,
2351 },
2352 { "PowerMac12,1", "iMac G5 (iSight)",
2353 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2354 0,
2355 },
2356 { "RackMac3,1", "XServe G5",
2357 PMAC_TYPE_XSERVE_G5, g5_features,
2358 0,
2359 },
2360 #endif /* CONFIG_PPC64 */
2361 };
2362
2363 /*
2364 * The toplevel feature_call callback
2365 */
pmac_do_feature_call(unsigned int selector,...)2366 long pmac_do_feature_call(unsigned int selector, ...)
2367 {
2368 struct device_node *node;
2369 long param, value;
2370 int i;
2371 feature_call func = NULL;
2372 va_list args;
2373
2374 if (pmac_mb.features)
2375 for (i=0; pmac_mb.features[i].function; i++)
2376 if (pmac_mb.features[i].selector == selector) {
2377 func = pmac_mb.features[i].function;
2378 break;
2379 }
2380 if (!func)
2381 for (i=0; any_features[i].function; i++)
2382 if (any_features[i].selector == selector) {
2383 func = any_features[i].function;
2384 break;
2385 }
2386 if (!func)
2387 return -ENODEV;
2388
2389 va_start(args, selector);
2390 node = (struct device_node*)va_arg(args, void*);
2391 param = va_arg(args, long);
2392 value = va_arg(args, long);
2393 va_end(args);
2394
2395 return func(node, param, value);
2396 }
2397
probe_motherboard(void)2398 static int __init probe_motherboard(void)
2399 {
2400 int i;
2401 struct macio_chip *macio = &macio_chips[0];
2402 const char *model = NULL;
2403 struct device_node *dt;
2404 int ret = 0;
2405
2406 /* Lookup known motherboard type in device-tree. First try an
2407 * exact match on the "model" property, then try a "compatible"
2408 * match is none is found.
2409 */
2410 dt = of_find_node_by_name(NULL, "device-tree");
2411 if (dt != NULL)
2412 model = of_get_property(dt, "model", NULL);
2413 for(i=0; model && i<ARRAY_SIZE(pmac_mb_defs); i++) {
2414 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
2415 pmac_mb = pmac_mb_defs[i];
2416 goto found;
2417 }
2418 }
2419 for(i=0; i<ARRAY_SIZE(pmac_mb_defs); i++) {
2420 if (of_machine_is_compatible(pmac_mb_defs[i].model_string)) {
2421 pmac_mb = pmac_mb_defs[i];
2422 goto found;
2423 }
2424 }
2425
2426 /* Fallback to selection depending on mac-io chip type */
2427 switch(macio->type) {
2428 #ifndef CONFIG_PPC64
2429 case macio_grand_central:
2430 pmac_mb.model_id = PMAC_TYPE_PSURGE;
2431 pmac_mb.model_name = "Unknown PowerSurge";
2432 break;
2433 case macio_ohare:
2434 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
2435 pmac_mb.model_name = "Unknown OHare-based";
2436 break;
2437 case macio_heathrow:
2438 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
2439 pmac_mb.model_name = "Unknown Heathrow-based";
2440 pmac_mb.features = heathrow_desktop_features;
2441 break;
2442 case macio_paddington:
2443 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
2444 pmac_mb.model_name = "Unknown Paddington-based";
2445 pmac_mb.features = paddington_features;
2446 break;
2447 case macio_keylargo:
2448 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
2449 pmac_mb.model_name = "Unknown Keylargo-based";
2450 pmac_mb.features = core99_features;
2451 break;
2452 case macio_pangea:
2453 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
2454 pmac_mb.model_name = "Unknown Pangea-based";
2455 pmac_mb.features = pangea_features;
2456 break;
2457 case macio_intrepid:
2458 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
2459 pmac_mb.model_name = "Unknown Intrepid-based";
2460 pmac_mb.features = intrepid_features;
2461 break;
2462 #else /* CONFIG_PPC64 */
2463 case macio_keylargo2:
2464 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
2465 pmac_mb.model_name = "Unknown K2-based";
2466 pmac_mb.features = g5_features;
2467 break;
2468 case macio_shasta:
2469 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA;
2470 pmac_mb.model_name = "Unknown Shasta-based";
2471 pmac_mb.features = g5_features;
2472 break;
2473 #endif /* CONFIG_PPC64 */
2474 default:
2475 ret = -ENODEV;
2476 goto done;
2477 }
2478 found:
2479 #ifndef CONFIG_PPC64
2480 /* Fixup Hooper vs. Comet */
2481 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
2482 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4);
2483 if (!mach_id_ptr) {
2484 ret = -ENODEV;
2485 goto done;
2486 }
2487 /* Here, I used to disable the media-bay on comet. It
2488 * appears this is wrong, the floppy connector is actually
2489 * a kind of media-bay and works with the current driver.
2490 */
2491 if (__raw_readl(mach_id_ptr) & 0x20000000UL)
2492 pmac_mb.model_id = PMAC_TYPE_COMET;
2493 iounmap(mach_id_ptr);
2494 }
2495
2496 /* Set default value of powersave_nap on machines that support it.
2497 * It appears that uninorth rev 3 has a problem with it, we don't
2498 * enable it on those. In theory, the flush-on-lock property is
2499 * supposed to be set when not supported, but I'm not very confident
2500 * that all Apple OF revs did it properly, I do it the paranoid way.
2501 */
2502 if (uninorth_base && uninorth_rev > 3) {
2503 struct device_node *np;
2504
2505 for_each_of_cpu_node(np) {
2506 int cpu_count = 1;
2507
2508 /* Nap mode not supported on SMP */
2509 if (of_property_read_bool(np, "flush-on-lock") ||
2510 (cpu_count > 1)) {
2511 powersave_nap = 0;
2512 of_node_put(np);
2513 break;
2514 }
2515
2516 cpu_count++;
2517 powersave_nap = 1;
2518 }
2519 }
2520 if (powersave_nap)
2521 printk(KERN_DEBUG "Processor NAP mode on idle enabled.\n");
2522
2523 /* On CPUs that support it (750FX), lowspeed by default during
2524 * NAP mode
2525 */
2526 powersave_lowspeed = 1;
2527
2528 #else /* CONFIG_PPC64 */
2529 powersave_nap = 1;
2530 #endif /* CONFIG_PPC64 */
2531
2532 /* Check for "mobile" machine */
2533 if (model && (strncmp(model, "PowerBook", 9) == 0
2534 || strncmp(model, "iBook", 5) == 0))
2535 pmac_mb.board_flags |= PMAC_MB_MOBILE;
2536
2537
2538 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
2539 done:
2540 of_node_put(dt);
2541 return ret;
2542 }
2543
2544 /* Initialize the Core99 UniNorth host bridge and memory controller
2545 */
probe_uninorth(void)2546 static void __init probe_uninorth(void)
2547 {
2548 struct resource res;
2549 unsigned long actrl;
2550
2551 /* Locate core99 Uni-N */
2552 uninorth_node = of_find_node_by_name(NULL, "uni-n");
2553 uninorth_maj = 1;
2554
2555 /* Locate G5 u3 */
2556 if (uninorth_node == NULL) {
2557 uninorth_node = of_find_node_by_name(NULL, "u3");
2558 uninorth_maj = 3;
2559 }
2560 /* Locate G5 u4 */
2561 if (uninorth_node == NULL) {
2562 uninorth_node = of_find_node_by_name(NULL, "u4");
2563 uninorth_maj = 4;
2564 }
2565 if (uninorth_node == NULL) {
2566 uninorth_maj = 0;
2567 return;
2568 }
2569
2570 if (of_address_to_resource(uninorth_node, 0, &res))
2571 return;
2572
2573 uninorth_base = ioremap(res.start, 0x40000);
2574 if (uninorth_base == NULL)
2575 return;
2576 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
2577 if (uninorth_maj == 3 || uninorth_maj == 4) {
2578 u3_ht_base = ioremap(res.start + U3_HT_CONFIG_BASE, 0x1000);
2579 if (u3_ht_base == NULL) {
2580 iounmap(uninorth_base);
2581 return;
2582 }
2583 }
2584
2585 printk(KERN_INFO "Found %s memory controller & host bridge"
2586 " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
2587 uninorth_maj == 4 ? "U4" : "UniNorth",
2588 (unsigned int)res.start, uninorth_rev);
2589 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2590
2591 /* Set the arbitrer QAck delay according to what Apple does
2592 */
2593 if (uninorth_rev < 0x11) {
2594 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
2595 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
2596 UNI_N_ARB_CTRL_QACK_DELAY) <<
2597 UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
2598 UN_OUT(UNI_N_ARB_CTRL, actrl);
2599 }
2600
2601 /* Some more magic as done by them in recent MacOS X on UniNorth
2602 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
2603 * memory timeout
2604 */
2605 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) ||
2606 uninorth_rev == 0xc0)
2607 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2608 }
2609
probe_one_macio(const char * name,const char * compat,int type)2610 static void __init probe_one_macio(const char *name, const char *compat, int type)
2611 {
2612 struct device_node* node;
2613 int i;
2614 volatile u32 __iomem *base;
2615 const __be32 *addrp;
2616 const u32 *revp;
2617 phys_addr_t addr;
2618 u64 size;
2619
2620 for_each_node_by_name(node, name) {
2621 if (!compat)
2622 break;
2623 if (of_device_is_compatible(node, compat))
2624 break;
2625 }
2626 if (!node)
2627 return;
2628 for(i=0; i<MAX_MACIO_CHIPS; i++) {
2629 if (!macio_chips[i].of_node)
2630 break;
2631 if (macio_chips[i].of_node == node)
2632 goto out_put;
2633 }
2634
2635 if (i >= MAX_MACIO_CHIPS) {
2636 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2637 printk(KERN_ERR "pmac_feature: %pOF skipped\n", node);
2638 goto out_put;
2639 }
2640 addrp = of_get_pci_address(node, 0, &size, NULL);
2641 if (addrp == NULL) {
2642 printk(KERN_ERR "pmac_feature: %pOF: can't find base !\n",
2643 node);
2644 goto out_put;
2645 }
2646 addr = of_translate_address(node, addrp);
2647 if (addr == 0) {
2648 printk(KERN_ERR "pmac_feature: %pOF, can't translate base !\n",
2649 node);
2650 goto out_put;
2651 }
2652 base = ioremap(addr, (unsigned long)size);
2653 if (!base) {
2654 printk(KERN_ERR "pmac_feature: %pOF, can't map mac-io chip !\n",
2655 node);
2656 goto out_put;
2657 }
2658 if (type == macio_keylargo || type == macio_keylargo2) {
2659 const u32 *did = of_get_property(node, "device-id", NULL);
2660 if (*did == 0x00000025)
2661 type = macio_pangea;
2662 if (*did == 0x0000003e)
2663 type = macio_intrepid;
2664 if (*did == 0x0000004f)
2665 type = macio_shasta;
2666 }
2667 macio_chips[i].of_node = node;
2668 macio_chips[i].type = type;
2669 macio_chips[i].base = base;
2670 macio_chips[i].flags = MACIO_FLAG_SCCA_ON | MACIO_FLAG_SCCB_ON;
2671 macio_chips[i].name = macio_names[type];
2672 revp = of_get_property(node, "revision-id", NULL);
2673 if (revp)
2674 macio_chips[i].rev = *revp;
2675 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2676 macio_names[type], macio_chips[i].rev, macio_chips[i].base);
2677
2678 return;
2679
2680 out_put:
2681 of_node_put(node);
2682 }
2683
2684 static int __init
probe_macios(void)2685 probe_macios(void)
2686 {
2687 /* Warning, ordering is important */
2688 probe_one_macio("gc", NULL, macio_grand_central);
2689 probe_one_macio("ohare", NULL, macio_ohare);
2690 probe_one_macio("pci106b,7", NULL, macio_ohareII);
2691 probe_one_macio("mac-io", "keylargo", macio_keylargo);
2692 probe_one_macio("mac-io", "paddington", macio_paddington);
2693 probe_one_macio("mac-io", "gatwick", macio_gatwick);
2694 probe_one_macio("mac-io", "heathrow", macio_heathrow);
2695 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
2696
2697 /* Make sure the "main" macio chip appear first */
2698 if (macio_chips[0].type == macio_gatwick
2699 && macio_chips[1].type == macio_heathrow) {
2700 struct macio_chip temp = macio_chips[0];
2701 macio_chips[0] = macio_chips[1];
2702 macio_chips[1] = temp;
2703 }
2704 if (macio_chips[0].type == macio_ohareII
2705 && macio_chips[1].type == macio_ohare) {
2706 struct macio_chip temp = macio_chips[0];
2707 macio_chips[0] = macio_chips[1];
2708 macio_chips[1] = temp;
2709 }
2710 macio_chips[0].lbus.index = 0;
2711 macio_chips[1].lbus.index = 1;
2712
2713 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
2714 }
2715
2716 static void __init
initial_serial_shutdown(struct device_node * np)2717 initial_serial_shutdown(struct device_node *np)
2718 {
2719 int len;
2720 const struct slot_names_prop {
2721 int count;
2722 char name[1];
2723 } *slots;
2724 const char *conn;
2725 int port_type = PMAC_SCC_ASYNC;
2726 int modem = 0;
2727
2728 slots = of_get_property(np, "slot-names", &len);
2729 conn = of_get_property(np, "AAPL,connector", &len);
2730 if (conn && (strcmp(conn, "infrared") == 0))
2731 port_type = PMAC_SCC_IRDA;
2732 else if (of_device_is_compatible(np, "cobalt"))
2733 modem = 1;
2734 else if (slots && slots->count > 0) {
2735 if (strcmp(slots->name, "IrDA") == 0)
2736 port_type = PMAC_SCC_IRDA;
2737 else if (strcmp(slots->name, "Modem") == 0)
2738 modem = 1;
2739 }
2740 if (modem)
2741 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
2742 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
2743 }
2744
2745 static void __init
set_initial_features(void)2746 set_initial_features(void)
2747 {
2748 struct device_node *np;
2749
2750 /* That hack appears to be necessary for some StarMax motherboards
2751 * but I'm not too sure it was audited for side-effects on other
2752 * ohare based machines...
2753 * Since I still have difficulties figuring the right way to
2754 * differentiate them all and since that hack was there for a long
2755 * time, I'll keep it around
2756 */
2757 if (macio_chips[0].type == macio_ohare) {
2758 struct macio_chip *macio = &macio_chips[0];
2759 np = of_find_node_by_name(NULL, "via-pmu");
2760 if (np)
2761 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2762 else
2763 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
2764 of_node_put(np);
2765 } else if (macio_chips[1].type == macio_ohare) {
2766 struct macio_chip *macio = &macio_chips[1];
2767 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2768 }
2769
2770 #ifdef CONFIG_PPC64
2771 if (macio_chips[0].type == macio_keylargo2 ||
2772 macio_chips[0].type == macio_shasta) {
2773 #ifndef CONFIG_SMP
2774 /* On SMP machines running UP, we have the second CPU eating
2775 * bus cycles. We need to take it off the bus. This is done
2776 * from pmac_smp for SMP kernels running on one CPU
2777 */
2778 np = of_find_node_by_type(NULL, "cpu");
2779 if (np != NULL)
2780 np = of_find_node_by_type(np, "cpu");
2781 if (np != NULL) {
2782 g5_phy_disable_cpu1();
2783 of_node_put(np);
2784 }
2785 #endif /* CONFIG_SMP */
2786 /* Enable GMAC for now for PCI probing. It will be disabled
2787 * later on after PCI probe
2788 */
2789 for_each_node_by_name(np, "ethernet")
2790 if (of_device_is_compatible(np, "K2-GMAC"))
2791 g5_gmac_enable(np, 0, 1);
2792
2793 /* Enable FW before PCI probe. Will be disabled later on
2794 * Note: We should have a batter way to check that we are
2795 * dealing with uninorth internal cell and not a PCI cell
2796 * on the external PCI. The code below works though.
2797 */
2798 for_each_node_by_name(np, "firewire") {
2799 if (of_device_is_compatible(np, "pci106b,5811")) {
2800 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2801 g5_fw_enable(np, 0, 1);
2802 }
2803 }
2804 }
2805 #else /* CONFIG_PPC64 */
2806
2807 if (macio_chips[0].type == macio_keylargo ||
2808 macio_chips[0].type == macio_pangea ||
2809 macio_chips[0].type == macio_intrepid) {
2810 /* Enable GMAC for now for PCI probing. It will be disabled
2811 * later on after PCI probe
2812 */
2813 for_each_node_by_name(np, "ethernet") {
2814 if (np->parent
2815 && of_device_is_compatible(np->parent, "uni-north")
2816 && of_device_is_compatible(np, "gmac"))
2817 core99_gmac_enable(np, 0, 1);
2818 }
2819
2820 /* Enable FW before PCI probe. Will be disabled later on
2821 * Note: We should have a batter way to check that we are
2822 * dealing with uninorth internal cell and not a PCI cell
2823 * on the external PCI. The code below works though.
2824 */
2825 for_each_node_by_name(np, "firewire") {
2826 if (np->parent
2827 && of_device_is_compatible(np->parent, "uni-north")
2828 && (of_device_is_compatible(np, "pci106b,18") ||
2829 of_device_is_compatible(np, "pci106b,30") ||
2830 of_device_is_compatible(np, "pci11c1,5811"))) {
2831 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2832 core99_firewire_enable(np, 0, 1);
2833 }
2834 }
2835
2836 /* Enable ATA-100 before PCI probe. */
2837 for_each_node_by_name(np, "ata-6") {
2838 if (np->parent
2839 && of_device_is_compatible(np->parent, "uni-north")
2840 && of_device_is_compatible(np, "kauai-ata")) {
2841 core99_ata100_enable(np, 1);
2842 }
2843 }
2844
2845 /* Switch airport off */
2846 for_each_node_by_name(np, "radio") {
2847 if (np->parent == macio_chips[0].of_node) {
2848 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
2849 core99_airport_enable(np, 0, 0);
2850 }
2851 }
2852 }
2853
2854 /* On all machines that support sound PM, switch sound off */
2855 if (macio_chips[0].of_node)
2856 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
2857 macio_chips[0].of_node, 0, 0);
2858
2859 /* While on some desktop G3s, we turn it back on */
2860 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
2861 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
2862 pmac_mb.model_id == PMAC_TYPE_SILK)) {
2863 struct macio_chip *macio = &macio_chips[0];
2864 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
2865 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2866 }
2867
2868 #endif /* CONFIG_PPC64 */
2869
2870 /* On all machines, switch modem & serial ports off */
2871 for_each_node_by_name(np, "ch-a")
2872 initial_serial_shutdown(np);
2873 for_each_node_by_name(np, "ch-b")
2874 initial_serial_shutdown(np);
2875 }
2876
2877 void __init
pmac_feature_init(void)2878 pmac_feature_init(void)
2879 {
2880 /* Detect the UniNorth memory controller */
2881 probe_uninorth();
2882
2883 /* Probe mac-io controllers */
2884 if (probe_macios()) {
2885 printk(KERN_WARNING "No mac-io chip found\n");
2886 return;
2887 }
2888
2889 /* Probe machine type */
2890 if (probe_motherboard())
2891 printk(KERN_WARNING "Unknown PowerMac !\n");
2892
2893 /* Set some initial features (turn off some chips that will
2894 * be later turned on)
2895 */
2896 set_initial_features();
2897 }
2898
2899 #if 0
2900 static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
2901 {
2902 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
2903 int bits[8] = { 8,16,0,32,2,4,0,0 };
2904 int freq = (frq >> 8) & 0xf;
2905
2906 if (freqs[freq] == 0)
2907 printk("%s: Unknown HT link frequency %x\n", name, freq);
2908 else
2909 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
2910 name, freqs[freq],
2911 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
2912 }
2913
2914 void __init pmac_check_ht_link(void)
2915 {
2916 u32 ufreq, freq, ucfg, cfg;
2917 struct device_node *pcix_node;
2918 u8 px_bus, px_devfn;
2919 struct pci_controller *px_hose;
2920
2921 (void)in_be32(u3_ht_base + U3_HT_LINK_COMMAND);
2922 ucfg = cfg = in_be32(u3_ht_base + U3_HT_LINK_CONFIG);
2923 ufreq = freq = in_be32(u3_ht_base + U3_HT_LINK_FREQ);
2924 dump_HT_speeds("U3 HyperTransport", cfg, freq);
2925
2926 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
2927 if (pcix_node == NULL) {
2928 printk("No PCI-X bridge found\n");
2929 return;
2930 }
2931 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
2932 printk("PCI-X bridge found but not matched to pci\n");
2933 return;
2934 }
2935 px_hose = pci_find_hose_for_OF_device(pcix_node);
2936 if (px_hose == NULL) {
2937 printk("PCI-X bridge found but not matched to host\n");
2938 return;
2939 }
2940 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
2941 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
2942 dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
2943 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
2944 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
2945 dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
2946 }
2947 #endif /* 0 */
2948
2949 /*
2950 * Early video resume hook
2951 */
2952
2953 static void (*pmac_early_vresume_proc)(void *data);
2954 static void *pmac_early_vresume_data;
2955
pmac_set_early_video_resume(void (* proc)(void * data),void * data)2956 void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
2957 {
2958 if (!machine_is(powermac))
2959 return;
2960 preempt_disable();
2961 pmac_early_vresume_proc = proc;
2962 pmac_early_vresume_data = data;
2963 preempt_enable();
2964 }
2965 EXPORT_SYMBOL(pmac_set_early_video_resume);
2966
pmac_call_early_video_resume(void)2967 void pmac_call_early_video_resume(void)
2968 {
2969 if (pmac_early_vresume_proc)
2970 pmac_early_vresume_proc(pmac_early_vresume_data);
2971 }
2972
2973 /*
2974 * AGP related suspend/resume code
2975 */
2976
2977 static struct pci_dev *pmac_agp_bridge;
2978 static int (*pmac_agp_suspend)(struct pci_dev *bridge);
2979 static int (*pmac_agp_resume)(struct pci_dev *bridge);
2980
pmac_register_agp_pm(struct pci_dev * bridge,int (* suspend)(struct pci_dev * bridge),int (* resume)(struct pci_dev * bridge))2981 void pmac_register_agp_pm(struct pci_dev *bridge,
2982 int (*suspend)(struct pci_dev *bridge),
2983 int (*resume)(struct pci_dev *bridge))
2984 {
2985 if (suspend || resume) {
2986 pmac_agp_bridge = bridge;
2987 pmac_agp_suspend = suspend;
2988 pmac_agp_resume = resume;
2989 return;
2990 }
2991 if (bridge != pmac_agp_bridge)
2992 return;
2993 pmac_agp_suspend = pmac_agp_resume = NULL;
2994 return;
2995 }
2996 EXPORT_SYMBOL(pmac_register_agp_pm);
2997
pmac_suspend_agp_for_card(struct pci_dev * dev)2998 void pmac_suspend_agp_for_card(struct pci_dev *dev)
2999 {
3000 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
3001 return;
3002 if (pmac_agp_bridge->bus != dev->bus)
3003 return;
3004 pmac_agp_suspend(pmac_agp_bridge);
3005 }
3006 EXPORT_SYMBOL(pmac_suspend_agp_for_card);
3007
pmac_resume_agp_for_card(struct pci_dev * dev)3008 void pmac_resume_agp_for_card(struct pci_dev *dev)
3009 {
3010 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
3011 return;
3012 if (pmac_agp_bridge->bus != dev->bus)
3013 return;
3014 pmac_agp_resume(pmac_agp_bridge);
3015 }
3016 EXPORT_SYMBOL(pmac_resume_agp_for_card);
3017
pmac_get_uninorth_variant(void)3018 int pmac_get_uninorth_variant(void)
3019 {
3020 return uninorth_maj;
3021 }
3022