1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _osssys_7_0_0_SH_MASK_HEADER 24 #define _osssys_7_0_0_SH_MASK_HEADER 25 26 27 // addressBlock: osssys_osssysdec 28 //IH_VMID_0_LUT 29 #define IH_VMID_0_LUT__PASID__SHIFT 0x0 30 #define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL 31 //IH_VMID_1_LUT 32 #define IH_VMID_1_LUT__PASID__SHIFT 0x0 33 #define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL 34 //IH_VMID_2_LUT 35 #define IH_VMID_2_LUT__PASID__SHIFT 0x0 36 #define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL 37 //IH_VMID_3_LUT 38 #define IH_VMID_3_LUT__PASID__SHIFT 0x0 39 #define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL 40 //IH_VMID_4_LUT 41 #define IH_VMID_4_LUT__PASID__SHIFT 0x0 42 #define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL 43 //IH_VMID_5_LUT 44 #define IH_VMID_5_LUT__PASID__SHIFT 0x0 45 #define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL 46 //IH_VMID_6_LUT 47 #define IH_VMID_6_LUT__PASID__SHIFT 0x0 48 #define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL 49 //IH_VMID_7_LUT 50 #define IH_VMID_7_LUT__PASID__SHIFT 0x0 51 #define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL 52 //IH_VMID_8_LUT 53 #define IH_VMID_8_LUT__PASID__SHIFT 0x0 54 #define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL 55 //IH_VMID_9_LUT 56 #define IH_VMID_9_LUT__PASID__SHIFT 0x0 57 #define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL 58 //IH_VMID_10_LUT 59 #define IH_VMID_10_LUT__PASID__SHIFT 0x0 60 #define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL 61 //IH_VMID_11_LUT 62 #define IH_VMID_11_LUT__PASID__SHIFT 0x0 63 #define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL 64 //IH_VMID_12_LUT 65 #define IH_VMID_12_LUT__PASID__SHIFT 0x0 66 #define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL 67 //IH_VMID_13_LUT 68 #define IH_VMID_13_LUT__PASID__SHIFT 0x0 69 #define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL 70 //IH_VMID_14_LUT 71 #define IH_VMID_14_LUT__PASID__SHIFT 0x0 72 #define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL 73 //IH_VMID_15_LUT 74 #define IH_VMID_15_LUT__PASID__SHIFT 0x0 75 #define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL 76 //IH_VMID_0_LUT_MM 77 #define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 78 #define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL 79 //IH_VMID_1_LUT_MM 80 #define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 81 #define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL 82 //IH_VMID_2_LUT_MM 83 #define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 84 #define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL 85 //IH_VMID_3_LUT_MM 86 #define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 87 #define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL 88 //IH_VMID_4_LUT_MM 89 #define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 90 #define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL 91 //IH_VMID_5_LUT_MM 92 #define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 93 #define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL 94 //IH_VMID_6_LUT_MM 95 #define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 96 #define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL 97 //IH_VMID_7_LUT_MM 98 #define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 99 #define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL 100 //IH_VMID_8_LUT_MM 101 #define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 102 #define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL 103 //IH_VMID_9_LUT_MM 104 #define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 105 #define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL 106 //IH_VMID_10_LUT_MM 107 #define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 108 #define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL 109 //IH_VMID_11_LUT_MM 110 #define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 111 #define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL 112 //IH_VMID_12_LUT_MM 113 #define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 114 #define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL 115 //IH_VMID_13_LUT_MM 116 #define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 117 #define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL 118 //IH_VMID_14_LUT_MM 119 #define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 120 #define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL 121 //IH_VMID_15_LUT_MM 122 #define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 123 #define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL 124 //IH_COOKIE_0 125 #define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 126 #define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 127 #define IH_COOKIE_0__RING_ID__SHIFT 0x10 128 #define IH_COOKIE_0__VM_ID__SHIFT 0x18 129 #define IH_COOKIE_0__RESERVED__SHIFT 0x1c 130 #define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f 131 #define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL 132 #define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L 133 #define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L 134 #define IH_COOKIE_0__VM_ID_MASK 0x0F000000L 135 #define IH_COOKIE_0__RESERVED_MASK 0x70000000L 136 #define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L 137 //IH_COOKIE_1 138 #define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 139 #define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL 140 //IH_COOKIE_2 141 #define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 142 #define IH_COOKIE_2__RESERVED__SHIFT 0x10 143 #define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f 144 #define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL 145 #define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L 146 #define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L 147 //IH_COOKIE_3 148 #define IH_COOKIE_3__PAS_ID__SHIFT 0x0 149 #define IH_COOKIE_3__RESERVED__SHIFT 0x10 150 #define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f 151 #define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL 152 #define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L 153 #define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L 154 //IH_COOKIE_4 155 #define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 156 #define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL 157 //IH_COOKIE_5 158 #define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 159 #define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL 160 //IH_COOKIE_6 161 #define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 162 #define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL 163 //IH_COOKIE_7 164 #define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 165 #define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL 166 //IH_REGISTER_LAST_PART0 167 #define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 168 #define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL 169 //IH_RB_CNTL 170 #define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 171 #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 172 #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 173 #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 174 #define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa 175 #define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb 176 #define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc 177 #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 178 #define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 179 #define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 180 #define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 181 #define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 182 #define IH_RB_CNTL__MC_RO__SHIFT 0x16 183 #define IH_RB_CNTL__MC_VMID__SHIFT 0x18 184 #define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c 185 #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 186 #define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L 187 #define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL 188 #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L 189 #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 190 #define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L 191 #define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L 192 #define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 193 #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 194 #define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L 195 #define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L 196 #define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L 197 #define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L 198 #define IH_RB_CNTL__MC_RO_MASK 0x00400000L 199 #define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L 200 #define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L 201 #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 202 //IH_RB_RPTR 203 #define IH_RB_RPTR__OFFSET__SHIFT 0x2 204 #define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL 205 //IH_RB_WPTR 206 #define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 207 #define IH_RB_WPTR__OFFSET__SHIFT 0x2 208 #define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 209 #define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 210 #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L 211 #define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL 212 #define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L 213 #define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L 214 //IH_RB_BASE 215 #define IH_RB_BASE__ADDR__SHIFT 0x0 216 #define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL 217 //IH_RB_BASE_HI 218 #define IH_RB_BASE_HI__ADDR__SHIFT 0x0 219 #define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL 220 //IH_RB_WPTR_ADDR_HI 221 #define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 222 #define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL 223 //IH_RB_WPTR_ADDR_LO 224 #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 225 #define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 226 //IH_DOORBELL_RPTR 227 #define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 228 #define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c 229 #define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL 230 #define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L 231 //IH_DOORBELL_RETRY_CAM 232 #define IH_DOORBELL_RETRY_CAM__OFFSET__SHIFT 0x0 233 #define IH_DOORBELL_RETRY_CAM__ENABLE__SHIFT 0x1c 234 #define IH_DOORBELL_RETRY_CAM__OFFSET_MASK 0x03FFFFFFL 235 #define IH_DOORBELL_RETRY_CAM__ENABLE_MASK 0x10000000L 236 //IH_RB_CNTL_RING1 237 #define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 238 #define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 239 #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 240 #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa 241 #define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb 242 #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc 243 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 244 #define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 245 #define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 246 #define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 247 #define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 248 #define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c 249 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 250 #define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L 251 #define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL 252 #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 253 #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L 254 #define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L 255 #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 256 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 257 #define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L 258 #define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L 259 #define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L 260 #define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L 261 #define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L 262 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 263 //IH_RB_RPTR_RING1 264 #define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 265 #define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL 266 //IH_RB_WPTR_RING1 267 #define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 268 #define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 269 #define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 270 #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 271 #define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L 272 #define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL 273 #define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L 274 #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L 275 //IH_RB_BASE_RING1 276 #define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 277 #define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL 278 //IH_RB_BASE_HI_RING1 279 #define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 280 #define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL 281 //IH_DOORBELL_RPTR_RING1 282 #define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 283 #define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c 284 #define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL 285 #define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L 286 //IH_RETRY_CAM_ACK 287 #define IH_RETRY_CAM_ACK__INDEX__SHIFT 0x0 288 #define IH_RETRY_CAM_ACK__INDEX_MASK 0x000003FFL 289 //IH_VERSION 290 #define IH_VERSION__MINVER__SHIFT 0x0 291 #define IH_VERSION__MAJVER__SHIFT 0x8 292 #define IH_VERSION__REV__SHIFT 0x10 293 #define IH_VERSION__MINVER_MASK 0x0000007FL 294 #define IH_VERSION__MAJVER_MASK 0x00007F00L 295 #define IH_VERSION__REV_MASK 0x003F0000L 296 //IH_CNTL 297 #define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 298 #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 299 #define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 300 #define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 301 #define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL 302 #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L 303 #define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L 304 #define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L 305 //IH_CLK_CTRL 306 #define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x17 307 #define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE__SHIFT 0x18 308 #define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x19 309 #define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 310 #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b 311 #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c 312 #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 313 #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e 314 #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 315 #define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE_MASK 0x00800000L 316 #define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE_MASK 0x01000000L 317 #define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK 0x02000000L 318 #define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 319 #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L 320 #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L 321 #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 322 #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L 323 #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 324 //IH_STORM_CLIENT_LIST_CNTL 325 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 326 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 327 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 328 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 329 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 330 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 331 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 332 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 333 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 334 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa 335 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb 336 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc 337 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd 338 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe 339 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf 340 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 341 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 342 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 343 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 344 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 345 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 346 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 347 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 348 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 349 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 350 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a 351 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b 352 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c 353 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d 354 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e 355 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f 356 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L 357 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L 358 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L 359 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L 360 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L 361 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L 362 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L 363 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L 364 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L 365 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L 366 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L 367 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L 368 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L 369 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L 370 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L 371 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L 372 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L 373 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L 374 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L 375 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L 376 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L 377 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L 378 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L 379 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L 380 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L 381 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L 382 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L 383 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L 384 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L 385 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L 386 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L 387 //IH_LIMIT_INT_RATE_CNTL 388 #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 389 #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 390 #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 391 #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 392 #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 393 #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L 394 #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL 395 #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L 396 #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L 397 #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L 398 //IH_RETRY_INT_CAM_CNTL 399 #define IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT 0x0 400 #define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT 0x8 401 #define IH_RETRY_INT_CAM_CNTL__ENABLE__SHIFT 0x10 402 #define IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE__SHIFT 0x11 403 #define IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE__SHIFT 0x12 404 #define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT 0x14 405 #define IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK 0x0000001FL 406 #define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK 0x00003F00L 407 #define IH_RETRY_INT_CAM_CNTL__ENABLE_MASK 0x00010000L 408 #define IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE_MASK 0x00020000L 409 #define IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE_MASK 0x00040000L 410 #define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK 0x00300000L 411 //IH_MEM_POWER_CTRL 412 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT 0x0 413 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT 0x1 414 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT 0x2 415 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT 0x3 416 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT 0x4 417 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 418 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe 419 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN__SHIFT 0x10 420 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN__SHIFT 0x11 421 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN__SHIFT 0x12 422 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN__SHIFT 0x13 423 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS__SHIFT 0x14 424 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 425 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e 426 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK 0x00000001L 427 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK 0x00000002L 428 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK 0x00000004L 429 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK 0x00000008L 430 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK 0x00000070L 431 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 432 #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L 433 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN_MASK 0x00010000L 434 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN_MASK 0x00020000L 435 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN_MASK 0x00040000L 436 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN_MASK 0x00080000L 437 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS_MASK 0x00700000L 438 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L 439 #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L 440 //IH_MEM_POWER_CTRL2 441 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN__SHIFT 0x0 442 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN__SHIFT 0x1 443 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN__SHIFT 0x2 444 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN__SHIFT 0x3 445 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS__SHIFT 0x4 446 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 447 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe 448 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN_MASK 0x00000001L 449 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN_MASK 0x00000002L 450 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN_MASK 0x00000004L 451 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN_MASK 0x00000008L 452 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS_MASK 0x00000070L 453 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 454 #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L 455 //IH_CNTL2 456 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 457 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 458 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL 459 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L 460 //IH_STATUS 461 #define IH_STATUS__IDLE__SHIFT 0x0 462 #define IH_STATUS__INPUT_IDLE__SHIFT 0x1 463 #define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 464 #define IH_STATUS__RB_FULL__SHIFT 0x3 465 #define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 466 #define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 467 #define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 468 #define IH_STATUS__MC_WR_STALL__SHIFT 0x7 469 #define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 470 #define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 471 #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa 472 #define IH_STATUS__SWITCH_READY__SHIFT 0xb 473 #define IH_STATUS__RB1_FULL__SHIFT 0xc 474 #define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd 475 #define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe 476 #define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 477 #define IH_STATUS__RETRY_INT_CAM_IDLE__SHIFT 0x13 478 #define IH_STATUS__ZSTATES_FENCE__SHIFT 0x14 479 #define IH_STATUS__IH_BUFFER_MEM_POWER_GATED__SHIFT 0x15 480 #define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED__SHIFT 0x16 481 #define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED__SHIFT 0x17 482 #define IH_STATUS__IDLE_MASK 0x00000001L 483 #define IH_STATUS__INPUT_IDLE_MASK 0x00000002L 484 #define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L 485 #define IH_STATUS__RB_FULL_MASK 0x00000008L 486 #define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L 487 #define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L 488 #define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L 489 #define IH_STATUS__MC_WR_STALL_MASK 0x00000080L 490 #define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L 491 #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L 492 #define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L 493 #define IH_STATUS__SWITCH_READY_MASK 0x00000800L 494 #define IH_STATUS__RB1_FULL_MASK 0x00001000L 495 #define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L 496 #define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L 497 #define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L 498 #define IH_STATUS__RETRY_INT_CAM_IDLE_MASK 0x00080000L 499 #define IH_STATUS__ZSTATES_FENCE_MASK 0x00100000L 500 #define IH_STATUS__IH_BUFFER_MEM_POWER_GATED_MASK 0x00200000L 501 #define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED_MASK 0x00400000L 502 #define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED_MASK 0x00800000L 503 //IH_PERFMON_CNTL 504 #define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 505 #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 506 #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 507 #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 508 #define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 509 #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 510 #define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L 511 #define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L 512 #define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x00000FFCL 513 #define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L 514 #define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L 515 #define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0FFC0000L 516 //IH_PERFCOUNTER0_RESULT 517 #define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 518 #define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 519 //IH_PERFCOUNTER1_RESULT 520 #define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 521 #define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 522 //IH_DSM_MATCH_VALUE_BIT_31_0 523 #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 524 #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL 525 //IH_DSM_MATCH_VALUE_BIT_63_32 526 #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 527 #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL 528 //IH_DSM_MATCH_VALUE_BIT_95_64 529 #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 530 #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL 531 //IH_DSM_MATCH_FIELD_CONTROL 532 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 533 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 534 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 535 #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 536 #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 537 #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 538 #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 539 #define IH_DSM_MATCH_FIELD_CONTROL__DIEID_EN__SHIFT 0x7 540 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L 541 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L 542 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L 543 #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L 544 #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L 545 #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L 546 #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L 547 #define IH_DSM_MATCH_FIELD_CONTROL__DIEID_EN_MASK 0x00000080L 548 //IH_DSM_MATCH_DATA_CONTROL 549 #define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 550 #define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL 551 //IH_DSM_MATCH_FCN_ID 552 #define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x0 553 #define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x7 554 #define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001FL 555 #define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000080L 556 //IH_VF_RB_STATUS 557 #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 558 #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x00FFFFFFL 559 //IH_VF_RB_STATUS2 560 #define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 561 #define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x00FFFFFFL 562 //IH_VF_RB1_STATUS 563 #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 564 #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x00FFFFFFL 565 //IH_VF_RB1_STATUS2 566 #define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 567 #define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x00FFFFFFL 568 //IH_RB_STATUS 569 #define IH_RB_STATUS__RB_FULL__SHIFT 0x0 570 #define IH_RB_STATUS__RB_FULL_DRAIN__SHIFT 0x1 571 #define IH_RB_STATUS__RB_OVERFLOW__SHIFT 0x2 572 #define IH_RB_STATUS__RB1_FULL__SHIFT 0x4 573 #define IH_RB_STATUS__RB1_FULL_DRAIN__SHIFT 0x5 574 #define IH_RB_STATUS__RB1_OVERFLOW__SHIFT 0x6 575 #define IH_RB_STATUS__RB_FULL_MASK 0x00000001L 576 #define IH_RB_STATUS__RB_FULL_DRAIN_MASK 0x00000002L 577 #define IH_RB_STATUS__RB_OVERFLOW_MASK 0x00000004L 578 #define IH_RB_STATUS__RB1_FULL_MASK 0x00000010L 579 #define IH_RB_STATUS__RB1_FULL_DRAIN_MASK 0x00000020L 580 #define IH_RB_STATUS__RB1_OVERFLOW_MASK 0x00000040L 581 //IH_INT_FLOOD_CNTL 582 #define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 583 #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 584 #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4 585 #define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L 586 #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L 587 #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L 588 //IH_RB0_INT_FLOOD_STATUS 589 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 590 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 591 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x00FFFFFFL 592 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 593 //IH_RB1_INT_FLOOD_STATUS 594 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 595 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 596 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x00FFFFFFL 597 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 598 //IH_INT_FLOOD_STATUS 599 #define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 600 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 601 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 602 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 603 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1d 604 #define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e 605 #define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL 606 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L 607 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L 608 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x1F000000L 609 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x20000000L 610 #define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L 611 //IH_INT_FLAGS 612 #define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 613 #define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 614 #define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 615 #define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 616 #define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 617 #define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 618 #define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 619 #define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 620 #define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 621 #define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 622 #define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa 623 #define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb 624 #define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc 625 #define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd 626 #define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe 627 #define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf 628 #define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 629 #define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 630 #define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 631 #define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 632 #define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 633 #define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 634 #define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 635 #define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 636 #define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 637 #define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 638 #define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a 639 #define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b 640 #define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c 641 #define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d 642 #define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e 643 #define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f 644 #define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L 645 #define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L 646 #define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L 647 #define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L 648 #define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L 649 #define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L 650 #define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L 651 #define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L 652 #define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L 653 #define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L 654 #define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L 655 #define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L 656 #define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L 657 #define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L 658 #define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L 659 #define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L 660 #define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L 661 #define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L 662 #define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L 663 #define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L 664 #define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L 665 #define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L 666 #define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L 667 #define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L 668 #define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L 669 #define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L 670 #define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L 671 #define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L 672 #define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L 673 #define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L 674 #define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L 675 #define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L 676 //IH_SCRATCH 677 #define IH_SCRATCH__DATA__SHIFT 0x0 678 #define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL 679 //IH_CLIENT_CREDIT_ERROR 680 #define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 681 #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 682 #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 683 #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 684 #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 685 #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 686 #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 687 #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 688 #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 689 #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 690 #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa 691 #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb 692 #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc 693 #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd 694 #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe 695 #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf 696 #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 697 #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 698 #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 699 #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 700 #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 701 #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 702 #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 703 #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 704 #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 705 #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 706 #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a 707 #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b 708 #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c 709 #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d 710 #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e 711 #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f 712 #define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L 713 #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L 714 #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L 715 #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L 716 #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L 717 #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L 718 #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L 719 #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L 720 #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L 721 #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L 722 #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L 723 #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L 724 #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L 725 #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L 726 #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L 727 #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L 728 #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L 729 #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L 730 #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L 731 #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L 732 #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L 733 #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L 734 #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L 735 #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L 736 #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L 737 #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L 738 #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L 739 #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L 740 #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L 741 #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L 742 #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L 743 #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L 744 //IH_GPU_IOV_VIOLATION_LOG 745 #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 746 #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 747 #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 748 #define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x16 749 #define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x17 750 #define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x18 751 #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 752 #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 753 #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL 754 #define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00400000L 755 #define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00800000L 756 #define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x1F000000L 757 //IH_GPU_IOV_VIOLATION_LOG2 758 #define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 759 #define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL 760 //IH_COOKIE_REC_VIOLATION_LOG 761 #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 762 #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x8 763 #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x10 764 #define IH_COOKIE_REC_VIOLATION_LOG__DIE_ID__SHIFT 0x1a 765 #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 766 #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x0000FF00L 767 #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0x03FF0000L 768 #define IH_COOKIE_REC_VIOLATION_LOG__DIE_ID_MASK 0x3C000000L 769 //IH_CREDIT_STATUS 770 #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 771 #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 772 #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 773 #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 774 #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 775 #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 776 #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 777 #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 778 #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 779 #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa 780 #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb 781 #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc 782 #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd 783 #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe 784 #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf 785 #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 786 #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 787 #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 788 #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 789 #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 790 #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 791 #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 792 #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 793 #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 794 #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 795 #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a 796 #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b 797 #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c 798 #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d 799 #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e 800 #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f 801 #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L 802 #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L 803 #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L 804 #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L 805 #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L 806 #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L 807 #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L 808 #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L 809 #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L 810 #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L 811 #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L 812 #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L 813 #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L 814 #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L 815 #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L 816 #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L 817 #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L 818 #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L 819 #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L 820 #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L 821 #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L 822 #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L 823 #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L 824 #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L 825 #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L 826 #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L 827 #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L 828 #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L 829 #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L 830 #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L 831 #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L 832 //IH_MMHUB_ERROR 833 #define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 834 #define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 835 #define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 836 #define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 837 #define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 838 #define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 839 #define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L 840 #define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L 841 #define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L 842 #define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L 843 #define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L 844 #define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L 845 //IH_VF_RB_STATUS3 846 #define IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 847 #define IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK 0x00FFFFFFL 848 //IH_VF_RB_STATUS4 849 #define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT 0x0 850 #define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK 0x00FFFFFFL 851 //IH_VF_RB1_STATUS3 852 #define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 853 #define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK 0x00FFFFFFL 854 //IH_MSI_STORM_CTRL 855 #define IH_MSI_STORM_CTRL__DELAY__SHIFT 0x0 856 #define IH_MSI_STORM_CTRL__DELAY_MASK 0x00000FFFL 857 //IH_MSI_STORM_CLIENT_INDEX 858 #define IH_MSI_STORM_CLIENT_INDEX__INDEX__SHIFT 0x0 859 #define IH_MSI_STORM_CLIENT_INDEX__INDEX_MASK 0x00000007L 860 //IH_MSI_STORM_CLIENT_DATA 861 #define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID__SHIFT 0x0 862 #define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID__SHIFT 0x8 863 #define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10 864 #define IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE__SHIFT 0x11 865 #define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID__SHIFT 0x1f 866 #define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID_MASK 0x000000FFL 867 #define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MASK 0x0000FF00L 868 #define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L 869 #define IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE_MASK 0x00020000L 870 #define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID_MASK 0x80000000L 871 //IH_LAST_INT_INFO0 872 #define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 873 #define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 874 #define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 875 #define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 876 #define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f 877 #define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL 878 #define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L 879 #define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L 880 #define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L 881 #define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L 882 //IH_LAST_INT_INFO1 883 #define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 884 #define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL 885 //IH_LAST_INT_INFO2 886 #define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 887 #define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 888 #define IH_LAST_INT_INFO2__VF__SHIFT 0x17 889 #define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL 890 #define IH_LAST_INT_INFO2__VF_ID_MASK 0x001F0000L 891 #define IH_LAST_INT_INFO2__VF_MASK 0x00800000L 892 //IH_REGISTER_LAST_PART2 893 #define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 894 #define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL 895 //SEM_MAILBOX 896 #define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 897 #define SEM_MAILBOX__RESERVED__SHIFT 0x10 898 #define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL 899 #define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L 900 //SEM_MAILBOX_CLEAR 901 #define SEM_MAILBOX_CLEAR__CLEAR__SHIFT 0x0 902 #define SEM_MAILBOX_CLEAR__RESERVED__SHIFT 0x10 903 #define SEM_MAILBOX_CLEAR__CLEAR_MASK 0x0000FFFFL 904 #define SEM_MAILBOX_CLEAR__RESERVED_MASK 0xFFFF0000L 905 //SEM_REGISTER_LAST_PART2 906 #define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 907 #define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL 908 //IH_ACTIVE_FCN_ID 909 #define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 910 #define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 911 #define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 912 #define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000001FL 913 #define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L 914 #define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 915 //IH_VIRT_RESET_REQ 916 #define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 917 #define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f 918 #define IH_VIRT_RESET_REQ__VF_MASK 0x00FFFFFFL 919 #define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L 920 //IH_CLIENT_CFG 921 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 922 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001FL 923 //IH_RING1_CLIENT_CFG_INDEX 924 #define IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 925 #define IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK 0x00000007L 926 //IH_RING1_CLIENT_CFG_DATA 927 #define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT 0x0 928 #define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT 0x8 929 #define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10 930 #define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK 0x000000FFL 931 #define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK 0x0000FF00L 932 #define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L 933 //IH_CLIENT_CFG_INDEX 934 #define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 935 #define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL 936 //IH_CLIENT_CFG_DATA 937 #define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12 938 #define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 939 #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18 940 #define IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT 0x19 941 #define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L 942 #define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L 943 #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L 944 #define IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK 0x02000000L 945 //IH_CLIENT_CFG_DATA2 946 #define IH_CLIENT_CFG_DATA2__CREDIT_RETURN_ADDR__SHIFT 0x0 947 #define IH_CLIENT_CFG_DATA2__CREDIT_RETURN_ADDR_MASK 0xFFFFFFFFL 948 //IH_CID_REMAP_INDEX 949 #define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 950 #define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L 951 //IH_CID_REMAP_DATA 952 #define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 953 #define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 954 #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18 955 #define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL 956 #define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L 957 #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L 958 //IH_CHICKEN 959 #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 960 #define IH_CHICKEN__DBGU_TRIGGER_ENABLE__SHIFT 0x1 961 #define IH_CHICKEN__CROSS_TRIGGER_ENABLE__SHIFT 0x2 962 #define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 963 #define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 964 #define IH_CHICKEN__REG_FIREWALL_ENABLE__SHIFT 0x5 965 #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L 966 #define IH_CHICKEN__DBGU_TRIGGER_ENABLE_MASK 0x00000002L 967 #define IH_CHICKEN__CROSS_TRIGGER_ENABLE_MASK 0x00000004L 968 #define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L 969 #define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L 970 #define IH_CHICKEN__REG_FIREWALL_ENABLE_MASK 0x00000020L 971 //IH_INT_DROP_CNTL 972 #define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0 973 #define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1 974 #define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2 975 #define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3 976 #define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4 977 #define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5 978 #define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6 979 #define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8 980 #define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10 981 #define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L 982 #define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L 983 #define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L 984 #define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L 985 #define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L 986 #define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L 987 #define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L 988 #define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L 989 #define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L 990 //IH_INT_DROP_MATCH_VALUE0 991 #define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0 992 #define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8 993 #define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10 994 #define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17 995 #define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18 996 #define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL 997 #define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L 998 #define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x001F0000L 999 #define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L 1000 #define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L 1001 //IH_INT_DROP_MATCH_VALUE1 1002 #define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0 1003 #define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL 1004 //IH_INT_DROP_MATCH_MASK0 1005 #define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0 1006 #define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8 1007 #define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10 1008 #define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17 1009 #define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18 1010 #define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL 1011 #define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L 1012 #define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x001F0000L 1013 #define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L 1014 #define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L 1015 //IH_INT_DROP_MATCH_MASK1 1016 #define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0 1017 #define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL 1018 //IH_MMHUB_CNTL 1019 #define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 1020 #define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 1021 #define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc 1022 #define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL 1023 #define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000F00L 1024 #define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x0000F000L 1025 //IH_REGISTER_LAST_PART1 1026 #define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 1027 #define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL 1028 1029 #endif 1030