1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16 #ifndef __INPUT_SYSTEM_2401_PRIVATE_H_INCLUDED__
17 #define __INPUT_SYSTEM_2401_PRIVATE_H_INCLUDED__
18
19 #include "input_system_public.h"
20
21 #include "device_access.h" /* ia_css_device_load_uint32 */
22
23 #include "assert_support.h" /* assert */
24 #include "print_support.h" /* print */
25
26 /* Load the register value */
ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID,const hrt_address reg)27 static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID,
28 const hrt_address reg)
29 {
30 assert(ID < N_IBUF_CTRL_ID);
31 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
32 return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data));
33 }
34
35 /* Store a value to the register */
ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID,const hrt_address reg,const hrt_data value)36 static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID,
37 const hrt_address reg,
38 const hrt_data value)
39 {
40 assert(ID < N_IBUF_CTRL_ID);
41 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
42
43 ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
44 }
45
46 /* Get the state of the ibuf-controller process */
ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID,const u32 proc_id,ibuf_ctrl_proc_state_t * state)47 static inline void ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID,
48 const u32 proc_id,
49 ibuf_ctrl_proc_state_t *state)
50 {
51 hrt_address reg_bank_offset;
52
53 reg_bank_offset =
54 _IBUF_CNTRL_PROC_REG_ALIGN * (1 + proc_id);
55
56 state->num_items =
57 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE);
58
59 state->num_stores =
60 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_STORES_PER_FRAME);
61
62 state->dma_channel =
63 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CHANNEL);
64
65 state->dma_command =
66 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CMD);
67
68 state->ibuf_st_addr =
69 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_START_ADDRESS);
70
71 state->ibuf_stride =
72 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_STRIDE);
73
74 state->ibuf_end_addr =
75 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_END_ADDRESS);
76
77 state->dest_st_addr =
78 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_START_ADDRESS);
79
80 state->dest_stride =
81 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_STRIDE);
82
83 state->dest_end_addr =
84 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_END_ADDRESS);
85
86 state->sync_frame =
87 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SYNC_FRAME);
88
89 state->sync_command =
90 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_SYNC_CMD);
91
92 state->store_command =
93 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_STORE_CMD);
94
95 state->shift_returned_items =
96 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SHIFT_ITEMS);
97
98 state->elems_ibuf =
99 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_IBUF);
100
101 state->elems_dest =
102 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_DEST);
103
104 state->cur_stores =
105 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_STORES);
106
107 state->cur_acks =
108 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ACKS);
109
110 state->cur_s2m_ibuf_addr =
111 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_S2M_IBUF_ADDR);
112
113 state->cur_dma_ibuf_addr =
114 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_IBUF_ADDR);
115
116 state->cur_dma_dest_addr =
117 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_DEST_ADDR);
118
119 state->cur_isp_dest_addr =
120 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ISP_DEST_ADDR);
121
122 state->dma_cmds_send =
123 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND);
124
125 state->main_cntrl_state =
126 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_MAIN_CNTRL_STATE);
127
128 state->dma_sync_state =
129 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_SYNC_STATE);
130
131 state->isp_sync_state =
132 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ISP_SYNC_STATE);
133 }
134
135 /* Get the ibuf-controller state. */
ibuf_ctrl_get_state(const ibuf_ctrl_ID_t ID,ibuf_ctrl_state_t * state)136 static inline void ibuf_ctrl_get_state(const ibuf_ctrl_ID_t ID,
137 ibuf_ctrl_state_t *state)
138 {
139 u32 i;
140
141 state->recalc_words =
142 ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_RECALC_WORDS_STATUS);
143 state->arbiters =
144 ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_ARBITERS_STATUS);
145
146 /*
147 * Get the values of the register-set per
148 * ibuf-controller process.
149 */
150 for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) {
151 ibuf_ctrl_get_proc_state(
152 ID,
153 i,
154 &state->proc_state[i]);
155 }
156 }
157
158 /* Dump the ibuf-controller state */
ibuf_ctrl_dump_state(const ibuf_ctrl_ID_t ID,ibuf_ctrl_state_t * state)159 static inline void ibuf_ctrl_dump_state(const ibuf_ctrl_ID_t ID,
160 ibuf_ctrl_state_t *state)
161 {
162 u32 i;
163
164 ia_css_print("IBUF controller ID %d recalculate words 0x%x\n", ID,
165 state->recalc_words);
166 ia_css_print("IBUF controller ID %d arbiters 0x%x\n", ID, state->arbiters);
167
168 /*
169 * Dump the values of the register-set per
170 * ibuf-controller process.
171 */
172 for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) {
173 ia_css_print("IBUF controller ID %d Process ID %d num_items 0x%x\n", ID, i,
174 state->proc_state[i].num_items);
175 ia_css_print("IBUF controller ID %d Process ID %d num_stores 0x%x\n", ID, i,
176 state->proc_state[i].num_stores);
177 ia_css_print("IBUF controller ID %d Process ID %d dma_channel 0x%x\n", ID, i,
178 state->proc_state[i].dma_channel);
179 ia_css_print("IBUF controller ID %d Process ID %d dma_command 0x%x\n", ID, i,
180 state->proc_state[i].dma_command);
181 ia_css_print("IBUF controller ID %d Process ID %d ibuf_st_addr 0x%x\n", ID, i,
182 state->proc_state[i].ibuf_st_addr);
183 ia_css_print("IBUF controller ID %d Process ID %d ibuf_stride 0x%x\n", ID, i,
184 state->proc_state[i].ibuf_stride);
185 ia_css_print("IBUF controller ID %d Process ID %d ibuf_end_addr 0x%x\n", ID, i,
186 state->proc_state[i].ibuf_end_addr);
187 ia_css_print("IBUF controller ID %d Process ID %d dest_st_addr 0x%x\n", ID, i,
188 state->proc_state[i].dest_st_addr);
189 ia_css_print("IBUF controller ID %d Process ID %d dest_stride 0x%x\n", ID, i,
190 state->proc_state[i].dest_stride);
191 ia_css_print("IBUF controller ID %d Process ID %d dest_end_addr 0x%x\n", ID, i,
192 state->proc_state[i].dest_end_addr);
193 ia_css_print("IBUF controller ID %d Process ID %d sync_frame 0x%x\n", ID, i,
194 state->proc_state[i].sync_frame);
195 ia_css_print("IBUF controller ID %d Process ID %d sync_command 0x%x\n", ID, i,
196 state->proc_state[i].sync_command);
197 ia_css_print("IBUF controller ID %d Process ID %d store_command 0x%x\n", ID, i,
198 state->proc_state[i].store_command);
199 ia_css_print("IBUF controller ID %d Process ID %d shift_returned_items 0x%x\n",
200 ID, i,
201 state->proc_state[i].shift_returned_items);
202 ia_css_print("IBUF controller ID %d Process ID %d elems_ibuf 0x%x\n", ID, i,
203 state->proc_state[i].elems_ibuf);
204 ia_css_print("IBUF controller ID %d Process ID %d elems_dest 0x%x\n", ID, i,
205 state->proc_state[i].elems_dest);
206 ia_css_print("IBUF controller ID %d Process ID %d cur_stores 0x%x\n", ID, i,
207 state->proc_state[i].cur_stores);
208 ia_css_print("IBUF controller ID %d Process ID %d cur_acks 0x%x\n", ID, i,
209 state->proc_state[i].cur_acks);
210 ia_css_print("IBUF controller ID %d Process ID %d cur_s2m_ibuf_addr 0x%x\n", ID,
211 i,
212 state->proc_state[i].cur_s2m_ibuf_addr);
213 ia_css_print("IBUF controller ID %d Process ID %d cur_dma_ibuf_addr 0x%x\n", ID,
214 i,
215 state->proc_state[i].cur_dma_ibuf_addr);
216 ia_css_print("IBUF controller ID %d Process ID %d cur_dma_dest_addr 0x%x\n", ID,
217 i,
218 state->proc_state[i].cur_dma_dest_addr);
219 ia_css_print("IBUF controller ID %d Process ID %d cur_isp_dest_addr 0x%x\n", ID,
220 i,
221 state->proc_state[i].cur_isp_dest_addr);
222 ia_css_print("IBUF controller ID %d Process ID %d dma_cmds_send 0x%x\n", ID, i,
223 state->proc_state[i].dma_cmds_send);
224 ia_css_print("IBUF controller ID %d Process ID %d main_cntrl_state 0x%x\n", ID,
225 i,
226 state->proc_state[i].main_cntrl_state);
227 ia_css_print("IBUF controller ID %d Process ID %d dma_sync_state 0x%x\n", ID, i,
228 state->proc_state[i].dma_sync_state);
229 ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i,
230 state->proc_state[i].isp_sync_state);
231 }
232 }
233
234 #endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */
235