1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Analog Devices ADP5585 I/O expander, PWM controller and keypad controller 4 * 5 * Copyright 2022 NXP 6 * Copyright 2024 Ideas on Board Oy 7 */ 8 9 #ifndef __MFD_ADP5585_H_ 10 #define __MFD_ADP5585_H_ 11 12 #include <linux/bits.h> 13 14 #define ADP5585_ID 0x00 15 #define ADP5585_MAN_ID_VALUE 0x20 16 #define ADP5585_MAN_ID_MASK GENMASK(7, 4) 17 #define ADP5585_INT_STATUS 0x01 18 #define ADP5585_STATUS 0x02 19 #define ADP5585_FIFO_1 0x03 20 #define ADP5585_FIFO_2 0x04 21 #define ADP5585_FIFO_3 0x05 22 #define ADP5585_FIFO_4 0x06 23 #define ADP5585_FIFO_5 0x07 24 #define ADP5585_FIFO_6 0x08 25 #define ADP5585_FIFO_7 0x09 26 #define ADP5585_FIFO_8 0x0a 27 #define ADP5585_FIFO_9 0x0b 28 #define ADP5585_FIFO_10 0x0c 29 #define ADP5585_FIFO_11 0x0d 30 #define ADP5585_FIFO_12 0x0e 31 #define ADP5585_FIFO_13 0x0f 32 #define ADP5585_FIFO_14 0x10 33 #define ADP5585_FIFO_15 0x11 34 #define ADP5585_FIFO_16 0x12 35 #define ADP5585_GPI_INT_STAT_A 0x13 36 #define ADP5585_GPI_INT_STAT_B 0x14 37 #define ADP5585_GPI_STATUS_A 0x15 38 #define ADP5585_GPI_STATUS_B 0x16 39 #define ADP5585_RPULL_CONFIG_A 0x17 40 #define ADP5585_RPULL_CONFIG_B 0x18 41 #define ADP5585_RPULL_CONFIG_C 0x19 42 #define ADP5585_RPULL_CONFIG_D 0x1a 43 #define ADP5585_Rx_PULL_CFG_PU_300K 0 44 #define ADP5585_Rx_PULL_CFG_PD_300K 1 45 #define ADP5585_Rx_PULL_CFG_PU_100K 2 46 #define ADP5585_Rx_PULL_CFG_DISABLE 3 47 #define ADP5585_Rx_PULL_CFG_MASK 3 48 #define ADP5585_GPI_INT_LEVEL_A 0x1b 49 #define ADP5585_GPI_INT_LEVEL_B 0x1c 50 #define ADP5585_GPI_EVENT_EN_A 0x1d 51 #define ADP5585_GPI_EVENT_EN_B 0x1e 52 #define ADP5585_GPI_INTERRUPT_EN_A 0x1f 53 #define ADP5585_GPI_INTERRUPT_EN_B 0x20 54 #define ADP5585_DEBOUNCE_DIS_A 0x21 55 #define ADP5585_DEBOUNCE_DIS_B 0x22 56 #define ADP5585_GPO_DATA_OUT_A 0x23 57 #define ADP5585_GPO_DATA_OUT_B 0x24 58 #define ADP5585_GPO_OUT_MODE_A 0x25 59 #define ADP5585_GPO_OUT_MODE_B 0x26 60 #define ADP5585_GPIO_DIRECTION_A 0x27 61 #define ADP5585_GPIO_DIRECTION_B 0x28 62 #define ADP5585_RESET1_EVENT_A 0x29 63 #define ADP5585_RESET1_EVENT_B 0x2a 64 #define ADP5585_RESET1_EVENT_C 0x2b 65 #define ADP5585_RESET2_EVENT_A 0x2c 66 #define ADP5585_RESET2_EVENT_B 0x2d 67 #define ADP5585_RESET_CFG 0x2e 68 #define ADP5585_PWM_OFFT_LOW 0x2f 69 #define ADP5585_PWM_OFFT_HIGH 0x30 70 #define ADP5585_PWM_ONT_LOW 0x31 71 #define ADP5585_PWM_ONT_HIGH 0x32 72 #define ADP5585_PWM_CFG 0x33 73 #define ADP5585_PWM_IN_AND BIT(2) 74 #define ADP5585_PWM_MODE BIT(1) 75 #define ADP5585_PWM_EN BIT(0) 76 #define ADP5585_LOGIC_CFG 0x34 77 #define ADP5585_LOGIC_FF_CFG 0x35 78 #define ADP5585_LOGIC_INT_EVENT_EN 0x36 79 #define ADP5585_POLL_PTIME_CFG 0x37 80 #define ADP5585_PIN_CONFIG_A 0x38 81 #define ADP5585_PIN_CONFIG_B 0x39 82 #define ADP5585_PIN_CONFIG_C 0x3a 83 #define ADP5585_PULL_SELECT BIT(7) 84 #define ADP5585_C4_EXTEND_CFG_GPIO11 (0U << 6) 85 #define ADP5585_C4_EXTEND_CFG_RESET2 (1U << 6) 86 #define ADP5585_C4_EXTEND_CFG_MASK GENMASK(6, 6) 87 #define ADP5585_R4_EXTEND_CFG_GPIO5 (0U << 5) 88 #define ADP5585_R4_EXTEND_CFG_RESET1 (1U << 5) 89 #define ADP5585_R4_EXTEND_CFG_MASK GENMASK(5, 5) 90 #define ADP5585_R3_EXTEND_CFG_GPIO4 (0U << 2) 91 #define ADP5585_R3_EXTEND_CFG_LC (1U << 2) 92 #define ADP5585_R3_EXTEND_CFG_PWM_OUT (2U << 2) 93 #define ADP5585_R3_EXTEND_CFG_MASK GENMASK(3, 2) 94 #define ADP5585_R0_EXTEND_CFG_GPIO1 (0U << 0) 95 #define ADP5585_R0_EXTEND_CFG_LY (1U << 0) 96 #define ADP5585_R0_EXTEND_CFG_MASK GENMASK(0, 0) 97 #define ADP5585_GENERAL_CFG 0x3b 98 #define ADP5585_OSC_EN BIT(7) 99 #define ADP5585_OSC_FREQ_50KHZ (0U << 5) 100 #define ADP5585_OSC_FREQ_100KHZ (1U << 5) 101 #define ADP5585_OSC_FREQ_200KHZ (2U << 5) 102 #define ADP5585_OSC_FREQ_500KHZ (3U << 5) 103 #define ADP5585_OSC_FREQ_MASK GENMASK(6, 5) 104 #define ADP5585_INT_CFG BIT(1) 105 #define ADP5585_RST_CFG BIT(0) 106 #define ADP5585_INT_EN 0x3c 107 108 #define ADP5585_MAX_REG ADP5585_INT_EN 109 110 /* 111 * Bank 0 covers pins "GPIO 1/R0" to "GPIO 6/R5", numbered 0 to 5 by the 112 * driver, and bank 1 covers pins "GPIO 7/C0" to "GPIO 11/C4", numbered 6 to 113 * 10. Some variants of the ADP5585 don't support "GPIO 6/R5". As the driver 114 * uses identical GPIO numbering for all variants to avoid confusion, GPIO 5 is 115 * marked as reserved in the device tree for variants that don't support it. 116 */ 117 #define ADP5585_BANK(n) ((n) >= 6 ? 1 : 0) 118 #define ADP5585_BIT(n) ((n) >= 6 ? BIT((n) - 6) : BIT(n)) 119 120 struct regmap; 121 122 struct adp5585_dev { 123 struct regmap *regmap; 124 }; 125 126 #endif 127