1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/clock/imx6ul-clock.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include "imx6ul-pinfunc.h" 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 /* 15 * The decompressor and also some bootloaders rely on a 16 * pre-existing /chosen node to be available to insert the 17 * command line and merge other ATAGS info. 18 */ 19 chosen {}; 20 21 aliases { 22 ethernet0 = &fec1; 23 ethernet1 = &fec2; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 i2c0 = &i2c1; 30 i2c1 = &i2c2; 31 i2c2 = &i2c3; 32 i2c3 = &i2c4; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 serial4 = &uart5; 40 serial5 = &uart6; 41 serial6 = &uart7; 42 serial7 = &uart8; 43 sai1 = &sai1; 44 sai2 = &sai2; 45 sai3 = &sai3; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbotg2; 52 usbphy0 = &usbphy1; 53 usbphy1 = &usbphy2; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a7"; 62 device_type = "cpu"; 63 reg = <0>; 64 clock-frequency = <696000000>; 65 clock-latency = <61036>; /* two CLK32 periods */ 66 #cooling-cells = <2>; 67 operating-points = 68 /* kHz uV */ 69 <696000 1275000>, 70 <528000 1175000>, 71 <396000 1025000>, 72 <198000 950000>; 73 fsl,soc-operating-points = 74 /* KHz uV */ 75 <696000 1275000>, 76 <528000 1175000>, 77 <396000 1175000>, 78 <198000 1175000>; 79 clocks = <&clks IMX6UL_CLK_ARM>, 80 <&clks IMX6UL_CLK_PLL2_BUS>, 81 <&clks IMX6UL_CLK_PLL2_PFD2>, 82 <&clks IMX6UL_CA7_SECONDARY_SEL>, 83 <&clks IMX6UL_CLK_STEP>, 84 <&clks IMX6UL_CLK_PLL1_SW>, 85 <&clks IMX6UL_CLK_PLL1_SYS>; 86 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", 87 "secondary_sel", "step", "pll1_sw", 88 "pll1_sys"; 89 arm-supply = <®_arm>; 90 soc-supply = <®_soc>; 91 nvmem-cells = <&cpu_speed_grade>; 92 nvmem-cell-names = "speed_grade"; 93 }; 94 }; 95 96 timer { 97 compatible = "arm,armv7-timer"; 98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 102 interrupt-parent = <&intc>; 103 status = "disabled"; 104 }; 105 106 ckil: clock-cli { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 clock-frequency = <32768>; 110 clock-output-names = "ckil"; 111 }; 112 113 osc: clock-osc { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <24000000>; 117 clock-output-names = "osc"; 118 }; 119 120 ipp_di0: clock-di0 { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <0>; 124 clock-output-names = "ipp_di0"; 125 }; 126 127 ipp_di1: clock-di1 { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <0>; 131 clock-output-names = "ipp_di1"; 132 }; 133 134 pmu { 135 compatible = "arm,cortex-a7-pmu"; 136 interrupt-parent = <&gpc>; 137 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 138 }; 139 140 soc: soc { 141 #address-cells = <1>; 142 #size-cells = <1>; 143 compatible = "simple-bus"; 144 interrupt-parent = <&gpc>; 145 ranges; 146 147 ocram: sram@900000 { 148 compatible = "mmio-sram"; 149 reg = <0x00900000 0x20000>; 150 ranges = <0 0x00900000 0x20000>; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 }; 154 155 intc: interrupt-controller@a01000 { 156 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 157 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 158 #interrupt-cells = <3>; 159 interrupt-controller; 160 interrupt-parent = <&intc>; 161 reg = <0x00a01000 0x1000>, 162 <0x00a02000 0x2000>, 163 <0x00a04000 0x2000>, 164 <0x00a06000 0x2000>; 165 }; 166 167 dma_apbh: dma-controller@1804000 { 168 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 169 reg = <0x01804000 0x2000>; 170 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 171 <0 13 IRQ_TYPE_LEVEL_HIGH>, 172 <0 13 IRQ_TYPE_LEVEL_HIGH>, 173 <0 13 IRQ_TYPE_LEVEL_HIGH>; 174 #dma-cells = <1>; 175 dma-channels = <4>; 176 clocks = <&clks IMX6UL_CLK_APBHDMA>; 177 }; 178 179 gpmi: nand-controller@1806000 { 180 compatible = "fsl,imx6q-gpmi-nand"; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 reg = <0x01806000 0x2000>, <0x01808000 0x2000>; 184 reg-names = "gpmi-nand", "bch"; 185 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "bch"; 187 clocks = <&clks IMX6UL_CLK_GPMI_IO>, 188 <&clks IMX6UL_CLK_GPMI_APB>, 189 <&clks IMX6UL_CLK_GPMI_BCH>, 190 <&clks IMX6UL_CLK_GPMI_BCH_APB>, 191 <&clks IMX6UL_CLK_PER_BCH>; 192 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 193 "gpmi_bch_apb", "per1_bch"; 194 dmas = <&dma_apbh 0>; 195 dma-names = "rx-tx"; 196 status = "disabled"; 197 }; 198 199 aips1: bus@2000000 { 200 compatible = "fsl,aips-bus", "simple-bus"; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 reg = <0x02000000 0x100000>; 204 ranges; 205 206 spba-bus@2000000 { 207 compatible = "fsl,spba-bus", "simple-bus"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 reg = <0x02000000 0x40000>; 211 ranges; 212 213 ecspi1: spi@2008000 { 214 #address-cells = <1>; 215 #size-cells = <0>; 216 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 217 reg = <0x02008000 0x4000>; 218 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&clks IMX6UL_CLK_ECSPI1>, 220 <&clks IMX6UL_CLK_ECSPI1>; 221 clock-names = "ipg", "per"; 222 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 223 dma-names = "rx", "tx"; 224 status = "disabled"; 225 }; 226 227 ecspi2: spi@200c000 { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 231 reg = <0x0200c000 0x4000>; 232 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&clks IMX6UL_CLK_ECSPI2>, 234 <&clks IMX6UL_CLK_ECSPI2>; 235 clock-names = "ipg", "per"; 236 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 237 dma-names = "rx", "tx"; 238 status = "disabled"; 239 }; 240 241 ecspi3: spi@2010000 { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 245 reg = <0x02010000 0x4000>; 246 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clks IMX6UL_CLK_ECSPI3>, 248 <&clks IMX6UL_CLK_ECSPI3>; 249 clock-names = "ipg", "per"; 250 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 251 dma-names = "rx", "tx"; 252 status = "disabled"; 253 }; 254 255 ecspi4: spi@2014000 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 259 reg = <0x02014000 0x4000>; 260 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&clks IMX6UL_CLK_ECSPI4>, 262 <&clks IMX6UL_CLK_ECSPI4>; 263 clock-names = "ipg", "per"; 264 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 265 dma-names = "rx", "tx"; 266 status = "disabled"; 267 }; 268 269 uart7: serial@2018000 { 270 compatible = "fsl,imx6ul-uart", 271 "fsl,imx6q-uart"; 272 reg = <0x02018000 0x4000>; 273 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&clks IMX6UL_CLK_UART7_IPG>, 275 <&clks IMX6UL_CLK_UART7_SERIAL>; 276 clock-names = "ipg", "per"; 277 status = "disabled"; 278 }; 279 280 uart1: serial@2020000 { 281 compatible = "fsl,imx6ul-uart", 282 "fsl,imx6q-uart"; 283 reg = <0x02020000 0x4000>; 284 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&clks IMX6UL_CLK_UART1_IPG>, 286 <&clks IMX6UL_CLK_UART1_SERIAL>; 287 clock-names = "ipg", "per"; 288 status = "disabled"; 289 }; 290 291 uart8: serial@2024000 { 292 compatible = "fsl,imx6ul-uart", 293 "fsl,imx6q-uart"; 294 reg = <0x02024000 0x4000>; 295 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&clks IMX6UL_CLK_UART8_IPG>, 297 <&clks IMX6UL_CLK_UART8_SERIAL>; 298 clock-names = "ipg", "per"; 299 status = "disabled"; 300 }; 301 302 sai1: sai@2028000 { 303 #sound-dai-cells = <0>; 304 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 305 reg = <0x02028000 0x4000>; 306 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&clks IMX6UL_CLK_SAI1_IPG>, 308 <&clks IMX6UL_CLK_SAI1>, 309 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 310 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 311 dmas = <&sdma 35 24 0>, 312 <&sdma 36 24 0>; 313 dma-names = "rx", "tx"; 314 status = "disabled"; 315 }; 316 317 sai2: sai@202c000 { 318 #sound-dai-cells = <0>; 319 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 320 reg = <0x0202c000 0x4000>; 321 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&clks IMX6UL_CLK_SAI2_IPG>, 323 <&clks IMX6UL_CLK_SAI2>, 324 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 325 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 326 dmas = <&sdma 37 24 0>, 327 <&sdma 38 24 0>; 328 dma-names = "rx", "tx"; 329 status = "disabled"; 330 }; 331 332 sai3: sai@2030000 { 333 #sound-dai-cells = <0>; 334 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 335 reg = <0x02030000 0x4000>; 336 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&clks IMX6UL_CLK_SAI3_IPG>, 338 <&clks IMX6UL_CLK_SAI3>, 339 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 340 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 341 dmas = <&sdma 39 24 0>, 342 <&sdma 40 24 0>; 343 dma-names = "rx", "tx"; 344 status = "disabled"; 345 }; 346 347 asrc: asrc@2034000 { 348 compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc"; 349 reg = <0x2034000 0x4000>; 350 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clks IMX6UL_CLK_ASRC_IPG>, 352 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, 353 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 354 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 355 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 356 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, 357 <&clks IMX6UL_CLK_SPBA>; 358 clock-names = "mem", "ipg", "asrck_0", 359 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 360 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 361 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 362 "asrck_d", "asrck_e", "asrck_f", "spba"; 363 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 364 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 365 dma-names = "rxa", "rxb", "rxc", 366 "txa", "txb", "txc"; 367 fsl,asrc-rate = <48000>; 368 fsl,asrc-width = <16>; 369 status = "okay"; 370 }; 371 }; 372 373 tsc: touchscreen@2040000 { 374 compatible = "fsl,imx6ul-tsc"; 375 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; 376 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clks IMX6UL_CLK_IPG>, 379 <&clks IMX6UL_CLK_ADC2>; 380 clock-names = "tsc", "adc"; 381 status = "disabled"; 382 }; 383 384 pwm1: pwm@2080000 { 385 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 386 reg = <0x02080000 0x4000>; 387 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&clks IMX6UL_CLK_PWM1>, 389 <&clks IMX6UL_CLK_PWM1>; 390 clock-names = "ipg", "per"; 391 #pwm-cells = <3>; 392 status = "disabled"; 393 }; 394 395 pwm2: pwm@2084000 { 396 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 397 reg = <0x02084000 0x4000>; 398 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&clks IMX6UL_CLK_PWM2>, 400 <&clks IMX6UL_CLK_PWM2>; 401 clock-names = "ipg", "per"; 402 #pwm-cells = <3>; 403 status = "disabled"; 404 }; 405 406 pwm3: pwm@2088000 { 407 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 408 reg = <0x02088000 0x4000>; 409 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clks IMX6UL_CLK_PWM3>, 411 <&clks IMX6UL_CLK_PWM3>; 412 clock-names = "ipg", "per"; 413 #pwm-cells = <3>; 414 status = "disabled"; 415 }; 416 417 pwm4: pwm@208c000 { 418 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 419 reg = <0x0208c000 0x4000>; 420 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clks IMX6UL_CLK_PWM4>, 422 <&clks IMX6UL_CLK_PWM4>; 423 clock-names = "ipg", "per"; 424 #pwm-cells = <3>; 425 status = "disabled"; 426 }; 427 428 can1: can@2090000 { 429 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 430 reg = <0x02090000 0x4000>; 431 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clks IMX6UL_CLK_CAN1_IPG>, 433 <&clks IMX6UL_CLK_CAN1_SERIAL>; 434 clock-names = "ipg", "per"; 435 fsl,stop-mode = <&gpr 0x10 1>; 436 status = "disabled"; 437 }; 438 439 can2: can@2094000 { 440 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 441 reg = <0x02094000 0x4000>; 442 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&clks IMX6UL_CLK_CAN2_IPG>, 444 <&clks IMX6UL_CLK_CAN2_SERIAL>; 445 clock-names = "ipg", "per"; 446 fsl,stop-mode = <&gpr 0x10 2>; 447 status = "disabled"; 448 }; 449 450 gpt1: timer@2098000 { 451 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 452 reg = <0x02098000 0x4000>; 453 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&clks IMX6UL_CLK_GPT1_BUS>, 455 <&clks IMX6UL_CLK_GPT1_SERIAL>; 456 clock-names = "ipg", "per"; 457 }; 458 459 gpio1: gpio@209c000 { 460 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 461 reg = <0x0209c000 0x4000>; 462 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&clks IMX6UL_CLK_GPIO1>; 465 gpio-controller; 466 #gpio-cells = <2>; 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, 470 <&iomuxc 16 33 16>; 471 }; 472 473 gpio2: gpio@20a0000 { 474 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 475 reg = <0x020a0000 0x4000>; 476 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clks IMX6UL_CLK_GPIO2>; 479 gpio-controller; 480 #gpio-cells = <2>; 481 interrupt-controller; 482 #interrupt-cells = <2>; 483 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; 484 }; 485 486 gpio3: gpio@20a4000 { 487 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 488 reg = <0x020a4000 0x4000>; 489 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clks IMX6UL_CLK_GPIO3>; 492 gpio-controller; 493 #gpio-cells = <2>; 494 interrupt-controller; 495 #interrupt-cells = <2>; 496 gpio-ranges = <&iomuxc 0 65 29>; 497 }; 498 499 gpio4: gpio@20a8000 { 500 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 501 reg = <0x020a8000 0x4000>; 502 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&clks IMX6UL_CLK_GPIO4>; 505 gpio-controller; 506 #gpio-cells = <2>; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; 510 }; 511 512 gpio5: gpio@20ac000 { 513 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 514 reg = <0x020ac000 0x4000>; 515 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clks IMX6UL_CLK_GPIO5>; 518 gpio-controller; 519 #gpio-cells = <2>; 520 interrupt-controller; 521 #interrupt-cells = <2>; 522 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; 523 }; 524 525 fec2: ethernet@20b4000 { 526 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 527 reg = <0x020b4000 0x4000>; 528 interrupt-names = "int0", "pps"; 529 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&clks IMX6UL_CLK_ENET>, 532 <&clks IMX6UL_CLK_ENET_AHB>, 533 <&clks IMX6UL_CLK_ENET_PTP>, 534 <&clks IMX6UL_CLK_ENET2_REF_SEL>; 535 clock-names = "ipg", "ahb", "ptp", 536 "enet_clk_ref"; 537 fsl,num-tx-queues = <1>; 538 fsl,num-rx-queues = <1>; 539 fsl,stop-mode = <&gpr 0x10 4>; 540 fsl,magic-packet; 541 nvmem-cells = <&fec2_mac_addr>; 542 nvmem-cell-names = "mac-address"; 543 status = "disabled"; 544 }; 545 546 kpp: keypad@20b8000 { 547 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; 548 reg = <0x020b8000 0x4000>; 549 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&clks IMX6UL_CLK_KPP>; 551 status = "disabled"; 552 }; 553 554 wdog1: watchdog@20bc000 { 555 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 556 reg = <0x020bc000 0x4000>; 557 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&clks IMX6UL_CLK_WDOG1>; 559 }; 560 561 wdog2: watchdog@20c0000 { 562 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 563 reg = <0x020c0000 0x4000>; 564 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&clks IMX6UL_CLK_WDOG2>; 566 status = "disabled"; 567 }; 568 569 clks: clock-controller@20c4000 { 570 compatible = "fsl,imx6ul-ccm"; 571 reg = <0x020c4000 0x4000>; 572 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 574 #clock-cells = <1>; 575 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 576 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 577 }; 578 579 anatop: anatop@20c8000 { 580 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", 581 "syscon", "simple-mfd"; 582 reg = <0x020c8000 0x1000>; 583 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 586 587 reg_3p0: regulator-3p0 { 588 compatible = "fsl,anatop-regulator"; 589 regulator-name = "vdd3p0"; 590 regulator-min-microvolt = <2625000>; 591 regulator-max-microvolt = <3400000>; 592 anatop-reg-offset = <0x120>; 593 anatop-vol-bit-shift = <8>; 594 anatop-vol-bit-width = <5>; 595 anatop-min-bit-val = <0>; 596 anatop-min-voltage = <2625000>; 597 anatop-max-voltage = <3400000>; 598 anatop-enable-bit = <0>; 599 }; 600 601 reg_arm: regulator-vddcore { 602 compatible = "fsl,anatop-regulator"; 603 regulator-name = "cpu"; 604 regulator-min-microvolt = <725000>; 605 regulator-max-microvolt = <1450000>; 606 regulator-always-on; 607 anatop-reg-offset = <0x140>; 608 anatop-vol-bit-shift = <0>; 609 anatop-vol-bit-width = <5>; 610 anatop-delay-reg-offset = <0x170>; 611 anatop-delay-bit-shift = <24>; 612 anatop-delay-bit-width = <2>; 613 anatop-min-bit-val = <1>; 614 anatop-min-voltage = <725000>; 615 anatop-max-voltage = <1450000>; 616 }; 617 618 reg_soc: regulator-vddsoc { 619 compatible = "fsl,anatop-regulator"; 620 regulator-name = "vddsoc"; 621 regulator-min-microvolt = <725000>; 622 regulator-max-microvolt = <1450000>; 623 regulator-always-on; 624 anatop-reg-offset = <0x140>; 625 anatop-vol-bit-shift = <18>; 626 anatop-vol-bit-width = <5>; 627 anatop-delay-reg-offset = <0x170>; 628 anatop-delay-bit-shift = <28>; 629 anatop-delay-bit-width = <2>; 630 anatop-min-bit-val = <1>; 631 anatop-min-voltage = <725000>; 632 anatop-max-voltage = <1450000>; 633 }; 634 635 tempmon: tempmon { 636 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; 637 interrupt-parent = <&gpc>; 638 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 639 fsl,tempmon = <&anatop>; 640 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 641 nvmem-cell-names = "calib", "temp_grade"; 642 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; 643 #thermal-sensor-cells = <0>; 644 }; 645 }; 646 647 usbphy1: usbphy@20c9000 { 648 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 649 reg = <0x020c9000 0x1000>; 650 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&clks IMX6UL_CLK_USBPHY1>; 652 phy-3p0-supply = <®_3p0>; 653 fsl,anatop = <&anatop>; 654 }; 655 656 usbphy2: usbphy@20ca000 { 657 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 658 reg = <0x020ca000 0x1000>; 659 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&clks IMX6UL_CLK_USBPHY2>; 661 phy-3p0-supply = <®_3p0>; 662 fsl,anatop = <&anatop>; 663 }; 664 665 snvs: snvs@20cc000 { 666 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 667 reg = <0x020cc000 0x4000>; 668 669 snvs_rtc: snvs-rtc-lp { 670 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 671 regmap = <&snvs>; 672 offset = <0x34>; 673 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 675 }; 676 677 snvs_poweroff: snvs-poweroff { 678 compatible = "syscon-poweroff"; 679 regmap = <&snvs>; 680 offset = <0x38>; 681 value = <0x60>; 682 mask = <0x60>; 683 status = "disabled"; 684 }; 685 686 snvs_pwrkey: snvs-powerkey { 687 compatible = "fsl,sec-v4.0-pwrkey"; 688 regmap = <&snvs>; 689 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 690 linux,keycode = <KEY_POWER>; 691 wakeup-source; 692 status = "disabled"; 693 }; 694 695 snvs_lpgpr: snvs-lpgpr { 696 compatible = "fsl,imx6ul-snvs-lpgpr"; 697 }; 698 }; 699 700 epit1: epit@20d0000 { 701 reg = <0x020d0000 0x4000>; 702 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 703 }; 704 705 epit2: epit@20d4000 { 706 reg = <0x020d4000 0x4000>; 707 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 708 }; 709 710 src: reset-controller@20d8000 { 711 compatible = "fsl,imx6ul-src", "fsl,imx51-src"; 712 reg = <0x020d8000 0x4000>; 713 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 715 #reset-cells = <1>; 716 }; 717 718 gpc: gpc@20dc000 { 719 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; 720 reg = <0x020dc000 0x4000>; 721 interrupt-controller; 722 #interrupt-cells = <3>; 723 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 724 interrupt-parent = <&intc>; 725 clocks = <&clks IMX6UL_CLK_IPG>; 726 clock-names = "ipg"; 727 728 pgc { 729 #address-cells = <1>; 730 #size-cells = <0>; 731 732 power-domain@0 { 733 reg = <0>; 734 #power-domain-cells = <0>; 735 }; 736 }; 737 }; 738 739 iomuxc: pinctrl@20e0000 { 740 compatible = "fsl,imx6ul-iomuxc"; 741 reg = <0x020e0000 0x4000>; 742 }; 743 744 gpr: iomuxc-gpr@20e4000 { 745 compatible = "fsl,imx6ul-iomuxc-gpr", 746 "fsl,imx6q-iomuxc-gpr", "syscon"; 747 reg = <0x020e4000 0x4000>; 748 }; 749 750 gpt2: timer@20e8000 { 751 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 752 reg = <0x020e8000 0x4000>; 753 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&clks IMX6UL_CLK_GPT2_BUS>, 755 <&clks IMX6UL_CLK_GPT2_SERIAL>; 756 clock-names = "ipg", "per"; 757 status = "disabled"; 758 }; 759 760 sdma: dma-controller@20ec000 { 761 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", 762 "fsl,imx35-sdma"; 763 reg = <0x020ec000 0x4000>; 764 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&clks IMX6UL_CLK_IPG>, 766 <&clks IMX6UL_CLK_SDMA>; 767 clock-names = "ipg", "ahb"; 768 #dma-cells = <3>; 769 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 770 }; 771 772 pwm5: pwm@20f0000 { 773 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 774 reg = <0x020f0000 0x4000>; 775 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&clks IMX6UL_CLK_PWM5>, 777 <&clks IMX6UL_CLK_PWM5>; 778 clock-names = "ipg", "per"; 779 #pwm-cells = <3>; 780 status = "disabled"; 781 }; 782 783 pwm6: pwm@20f4000 { 784 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 785 reg = <0x020f4000 0x4000>; 786 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&clks IMX6UL_CLK_PWM6>, 788 <&clks IMX6UL_CLK_PWM6>; 789 clock-names = "ipg", "per"; 790 #pwm-cells = <3>; 791 status = "disabled"; 792 }; 793 794 pwm7: pwm@20f8000 { 795 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 796 reg = <0x020f8000 0x4000>; 797 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&clks IMX6UL_CLK_PWM7>, 799 <&clks IMX6UL_CLK_PWM7>; 800 clock-names = "ipg", "per"; 801 #pwm-cells = <3>; 802 status = "disabled"; 803 }; 804 805 pwm8: pwm@20fc000 { 806 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 807 reg = <0x020fc000 0x4000>; 808 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&clks IMX6UL_CLK_PWM8>, 810 <&clks IMX6UL_CLK_PWM8>; 811 clock-names = "ipg", "per"; 812 #pwm-cells = <3>; 813 status = "disabled"; 814 }; 815 }; 816 817 aips2: bus@2100000 { 818 compatible = "fsl,aips-bus", "simple-bus"; 819 #address-cells = <1>; 820 #size-cells = <1>; 821 reg = <0x02100000 0x100000>; 822 ranges; 823 824 crypto: crypto@2140000 { 825 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; 826 #address-cells = <1>; 827 #size-cells = <1>; 828 reg = <0x2140000 0x3c000>; 829 ranges = <0 0x2140000 0x3c000>; 830 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, 832 <&clks IMX6UL_CLK_CAAM_MEM>; 833 clock-names = "ipg", "aclk", "mem"; 834 835 sec_jr0: jr@1000 { 836 compatible = "fsl,sec-v4.0-job-ring"; 837 reg = <0x1000 0x1000>; 838 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 839 }; 840 841 sec_jr1: jr@2000 { 842 compatible = "fsl,sec-v4.0-job-ring"; 843 reg = <0x2000 0x1000>; 844 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 845 }; 846 847 sec_jr2: jr@3000 { 848 compatible = "fsl,sec-v4.0-job-ring"; 849 reg = <0x3000 0x1000>; 850 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 851 }; 852 }; 853 854 usbotg1: usb@2184000 { 855 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 856 reg = <0x02184000 0x200>; 857 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&clks IMX6UL_CLK_USBOH3>; 859 fsl,usbphy = <&usbphy1>; 860 fsl,usbmisc = <&usbmisc 0>; 861 ahb-burst-config = <0x0>; 862 tx-burst-size-dword = <0x10>; 863 rx-burst-size-dword = <0x10>; 864 status = "disabled"; 865 }; 866 867 usbotg2: usb@2184200 { 868 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 869 reg = <0x02184200 0x200>; 870 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&clks IMX6UL_CLK_USBOH3>; 872 fsl,usbphy = <&usbphy2>; 873 fsl,usbmisc = <&usbmisc 1>; 874 ahb-burst-config = <0x0>; 875 tx-burst-size-dword = <0x10>; 876 rx-burst-size-dword = <0x10>; 877 status = "disabled"; 878 }; 879 880 usbmisc: usbmisc@2184800 { 881 #index-cells = <1>; 882 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; 883 reg = <0x02184800 0x200>; 884 }; 885 886 fec1: ethernet@2188000 { 887 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 888 reg = <0x02188000 0x4000>; 889 interrupt-names = "int0", "pps"; 890 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&clks IMX6UL_CLK_ENET>, 893 <&clks IMX6UL_CLK_ENET_AHB>, 894 <&clks IMX6UL_CLK_ENET_PTP>, 895 <&clks IMX6UL_CLK_ENET1_REF_SEL>; 896 clock-names = "ipg", "ahb", "ptp", 897 "enet_clk_ref"; 898 fsl,num-tx-queues = <1>; 899 fsl,num-rx-queues = <1>; 900 fsl,stop-mode = <&gpr 0x10 3>; 901 fsl,magic-packet; 902 nvmem-cells = <&fec1_mac_addr>; 903 nvmem-cell-names = "mac-address"; 904 status = "disabled"; 905 }; 906 907 usdhc1: mmc@2190000 { 908 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 909 reg = <0x02190000 0x4000>; 910 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&clks IMX6UL_CLK_USDHC1>, 912 <&clks IMX6UL_CLK_USDHC1>, 913 <&clks IMX6UL_CLK_USDHC1>; 914 clock-names = "ipg", "ahb", "per"; 915 fsl,tuning-step = <2>; 916 fsl,tuning-start-tap = <20>; 917 bus-width = <4>; 918 status = "disabled"; 919 }; 920 921 usdhc2: mmc@2194000 { 922 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 923 reg = <0x02194000 0x4000>; 924 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&clks IMX6UL_CLK_USDHC2>, 926 <&clks IMX6UL_CLK_USDHC2>, 927 <&clks IMX6UL_CLK_USDHC2>; 928 clock-names = "ipg", "ahb", "per"; 929 bus-width = <4>; 930 fsl,tuning-step = <2>; 931 fsl,tuning-start-tap = <20>; 932 status = "disabled"; 933 }; 934 935 adc1: adc@2198000 { 936 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; 937 reg = <0x02198000 0x4000>; 938 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&clks IMX6UL_CLK_ADC1>; 940 clock-names = "adc"; 941 fsl,adck-max-frequency = <30000000>, <40000000>, 942 <20000000>; 943 status = "disabled"; 944 }; 945 946 i2c1: i2c@21a0000 { 947 #address-cells = <1>; 948 #size-cells = <0>; 949 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 950 reg = <0x021a0000 0x4000>; 951 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&clks IMX6UL_CLK_I2C1>; 953 status = "disabled"; 954 }; 955 956 i2c2: i2c@21a4000 { 957 #address-cells = <1>; 958 #size-cells = <0>; 959 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 960 reg = <0x021a4000 0x4000>; 961 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&clks IMX6UL_CLK_I2C2>; 963 status = "disabled"; 964 }; 965 966 i2c3: i2c@21a8000 { 967 #address-cells = <1>; 968 #size-cells = <0>; 969 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 970 reg = <0x021a8000 0x4000>; 971 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&clks IMX6UL_CLK_I2C3>; 973 status = "disabled"; 974 }; 975 976 memory-controller@21b0000 { 977 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; 978 reg = <0x021b0000 0x4000>; 979 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; 980 }; 981 982 weim: memory-controller@21b8000 { 983 #address-cells = <2>; 984 #size-cells = <1>; 985 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; 986 reg = <0x021b8000 0x4000>; 987 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&clks IMX6UL_CLK_EIM>; 989 fsl,weim-cs-gpr = <&gpr>; 990 status = "disabled"; 991 }; 992 993 ocotp: efuse@21bc000 { 994 #address-cells = <1>; 995 #size-cells = <1>; 996 compatible = "fsl,imx6ul-ocotp", "syscon"; 997 reg = <0x021bc000 0x4000>; 998 clocks = <&clks IMX6UL_CLK_OCOTP>; 999 1000 tempmon_calib: calib@38 { 1001 reg = <0x38 4>; 1002 }; 1003 1004 tempmon_temp_grade: temp-grade@20 { 1005 reg = <0x20 4>; 1006 }; 1007 1008 cpu_speed_grade: speed-grade@10 { 1009 reg = <0x10 4>; 1010 }; 1011 1012 fec1_mac_addr: mac-addr@88 { 1013 reg = <0x88 6>; 1014 }; 1015 1016 fec2_mac_addr: mac-addr@8e { 1017 reg = <0x8e 6>; 1018 }; 1019 }; 1020 1021 csi: csi@21c4000 { 1022 compatible = "fsl,imx6ul-csi"; 1023 reg = <0x021c4000 0x4000>; 1024 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&clks IMX6UL_CLK_CSI>; 1026 clock-names = "mclk"; 1027 status = "disabled"; 1028 }; 1029 1030 lcdif: lcdif@21c8000 { 1031 compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif"; 1032 reg = <0x021c8000 0x4000>; 1033 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, 1035 <&clks IMX6UL_CLK_LCDIF_APB>, 1036 <&clks IMX6UL_CLK_DUMMY>; 1037 clock-names = "pix", "axi", "disp_axi"; 1038 status = "disabled"; 1039 }; 1040 1041 pxp: pxp@21cc000 { 1042 compatible = "fsl,imx6ul-pxp"; 1043 reg = <0x021cc000 0x4000>; 1044 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&clks IMX6UL_CLK_PXP>; 1046 clock-names = "axi"; 1047 }; 1048 1049 qspi: spi@21e0000 { 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 compatible = "fsl,imx6ul-qspi"; 1053 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1054 reg-names = "QuadSPI", "QuadSPI-memory"; 1055 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&clks IMX6UL_CLK_QSPI>, 1057 <&clks IMX6UL_CLK_QSPI>; 1058 clock-names = "qspi_en", "qspi"; 1059 status = "disabled"; 1060 }; 1061 1062 wdog3: watchdog@21e4000 { 1063 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 1064 reg = <0x021e4000 0x4000>; 1065 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&clks IMX6UL_CLK_WDOG3>; 1067 status = "disabled"; 1068 }; 1069 1070 uart2: serial@21e8000 { 1071 compatible = "fsl,imx6ul-uart", 1072 "fsl,imx6q-uart"; 1073 reg = <0x021e8000 0x4000>; 1074 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&clks IMX6UL_CLK_UART2_IPG>, 1076 <&clks IMX6UL_CLK_UART2_SERIAL>; 1077 clock-names = "ipg", "per"; 1078 status = "disabled"; 1079 }; 1080 1081 uart3: serial@21ec000 { 1082 compatible = "fsl,imx6ul-uart", 1083 "fsl,imx6q-uart"; 1084 reg = <0x021ec000 0x4000>; 1085 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&clks IMX6UL_CLK_UART3_IPG>, 1087 <&clks IMX6UL_CLK_UART3_SERIAL>; 1088 clock-names = "ipg", "per"; 1089 status = "disabled"; 1090 }; 1091 1092 uart4: serial@21f0000 { 1093 compatible = "fsl,imx6ul-uart", 1094 "fsl,imx6q-uart"; 1095 reg = <0x021f0000 0x4000>; 1096 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&clks IMX6UL_CLK_UART4_IPG>, 1098 <&clks IMX6UL_CLK_UART4_SERIAL>; 1099 clock-names = "ipg", "per"; 1100 status = "disabled"; 1101 }; 1102 1103 uart5: serial@21f4000 { 1104 compatible = "fsl,imx6ul-uart", 1105 "fsl,imx6q-uart"; 1106 reg = <0x021f4000 0x4000>; 1107 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&clks IMX6UL_CLK_UART5_IPG>, 1109 <&clks IMX6UL_CLK_UART5_SERIAL>; 1110 clock-names = "ipg", "per"; 1111 status = "disabled"; 1112 }; 1113 1114 i2c4: i2c@21f8000 { 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 1118 reg = <0x021f8000 0x4000>; 1119 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&clks IMX6UL_CLK_I2C4>; 1121 status = "disabled"; 1122 }; 1123 1124 uart6: serial@21fc000 { 1125 compatible = "fsl,imx6ul-uart", 1126 "fsl,imx6q-uart"; 1127 reg = <0x021fc000 0x4000>; 1128 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&clks IMX6UL_CLK_UART6_IPG>, 1130 <&clks IMX6UL_CLK_UART6_SERIAL>; 1131 clock-names = "ipg", "per"; 1132 status = "disabled"; 1133 }; 1134 }; 1135 }; 1136}; 1137