1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Maxim MAX96712 Quad GMSL2 Deserializer Driver
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation
6 * Copyright (C) 2021 Niklas Söderlund
7 */
8
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/module.h>
12 #include <linux/of_graph.h>
13 #include <linux/regmap.h>
14
15 #include <media/v4l2-ctrls.h>
16 #include <media/v4l2-fwnode.h>
17 #include <media/v4l2-subdev.h>
18
19 #define MAX96712_ID 0x20
20
21 #define MAX96712_DPLL_FREQ 1000
22
23 enum max96712_pattern {
24 MAX96712_PATTERN_CHECKERBOARD = 0,
25 MAX96712_PATTERN_GRADIENT,
26 };
27
28 struct max96712_priv {
29 struct i2c_client *client;
30 struct regmap *regmap;
31 struct gpio_desc *gpiod_pwdn;
32
33 bool cphy;
34 struct v4l2_mbus_config_mipi_csi2 mipi;
35
36 struct v4l2_subdev sd;
37 struct v4l2_ctrl_handler ctrl_handler;
38 struct media_pad pads[1];
39
40 enum max96712_pattern pattern;
41 };
42
max96712_read(struct max96712_priv * priv,int reg)43 static int max96712_read(struct max96712_priv *priv, int reg)
44 {
45 int ret, val;
46
47 ret = regmap_read(priv->regmap, reg, &val);
48 if (ret) {
49 dev_err(&priv->client->dev, "read 0x%04x failed\n", reg);
50 return ret;
51 }
52
53 return val;
54 }
55
max96712_write(struct max96712_priv * priv,unsigned int reg,u8 val)56 static int max96712_write(struct max96712_priv *priv, unsigned int reg, u8 val)
57 {
58 int ret;
59
60 ret = regmap_write(priv->regmap, reg, val);
61 if (ret)
62 dev_err(&priv->client->dev, "write 0x%04x failed\n", reg);
63
64 return ret;
65 }
66
max96712_update_bits(struct max96712_priv * priv,unsigned int reg,u8 mask,u8 val)67 static int max96712_update_bits(struct max96712_priv *priv, unsigned int reg,
68 u8 mask, u8 val)
69 {
70 int ret;
71
72 ret = regmap_update_bits(priv->regmap, reg, mask, val);
73 if (ret)
74 dev_err(&priv->client->dev, "update 0x%04x failed\n", reg);
75
76 return ret;
77 }
78
max96712_write_bulk(struct max96712_priv * priv,unsigned int reg,const void * val,size_t val_count)79 static int max96712_write_bulk(struct max96712_priv *priv, unsigned int reg,
80 const void *val, size_t val_count)
81 {
82 int ret;
83
84 ret = regmap_bulk_write(priv->regmap, reg, val, val_count);
85 if (ret)
86 dev_err(&priv->client->dev, "bulk write 0x%04x failed\n", reg);
87
88 return ret;
89 }
90
max96712_write_bulk_value(struct max96712_priv * priv,unsigned int reg,unsigned int val,size_t val_count)91 static int max96712_write_bulk_value(struct max96712_priv *priv,
92 unsigned int reg, unsigned int val,
93 size_t val_count)
94 {
95 unsigned int i;
96 u8 values[4];
97
98 for (i = 1; i <= val_count; i++)
99 values[i - 1] = (val >> ((val_count - i) * 8)) & 0xff;
100
101 return max96712_write_bulk(priv, reg, &values, val_count);
102 }
103
max96712_reset(struct max96712_priv * priv)104 static void max96712_reset(struct max96712_priv *priv)
105 {
106 max96712_update_bits(priv, 0x13, 0x40, 0x40);
107 msleep(20);
108 }
109
max96712_mipi_enable(struct max96712_priv * priv,bool enable)110 static void max96712_mipi_enable(struct max96712_priv *priv, bool enable)
111 {
112 if (enable) {
113 max96712_update_bits(priv, 0x40b, 0x02, 0x02);
114 max96712_update_bits(priv, 0x8a0, 0x80, 0x80);
115 } else {
116 max96712_update_bits(priv, 0x8a0, 0x80, 0x00);
117 max96712_update_bits(priv, 0x40b, 0x02, 0x00);
118 }
119 }
120
max96712_mipi_configure(struct max96712_priv * priv)121 static void max96712_mipi_configure(struct max96712_priv *priv)
122 {
123 unsigned int i;
124 u8 phy5 = 0;
125
126 max96712_mipi_enable(priv, false);
127
128 /* Select 2x4 mode. */
129 max96712_write(priv, 0x8a0, 0x04);
130
131 /* TODO: Add support for 2-lane and 1-lane configurations. */
132 if (priv->cphy) {
133 /* Configure a 3-lane C-PHY using PHY0 and PHY1. */
134 max96712_write(priv, 0x94a, 0xa0);
135
136 /* Configure C-PHY timings. */
137 max96712_write(priv, 0x8ad, 0x3f);
138 max96712_write(priv, 0x8ae, 0x7d);
139 } else {
140 /* Configure a 4-lane D-PHY using PHY0 and PHY1. */
141 max96712_write(priv, 0x94a, 0xc0);
142 }
143
144 /* Configure lane mapping for PHY0 and PHY1. */
145 /* TODO: Add support for lane swapping. */
146 max96712_write(priv, 0x8a3, 0xe4);
147
148 /* Configure lane polarity for PHY0 and PHY1. */
149 for (i = 0; i < priv->mipi.num_data_lanes + 1; i++)
150 if (priv->mipi.lane_polarities[i])
151 phy5 |= BIT(i == 0 ? 5 : i < 3 ? i - 1 : i);
152 max96712_write(priv, 0x8a5, phy5);
153
154 /* Set link frequency for PHY0 and PHY1. */
155 max96712_update_bits(priv, 0x415, 0x3f,
156 ((MAX96712_DPLL_FREQ / 100) & 0x1f) | BIT(5));
157 max96712_update_bits(priv, 0x418, 0x3f,
158 ((MAX96712_DPLL_FREQ / 100) & 0x1f) | BIT(5));
159
160 /* Enable PHY0 and PHY1 */
161 max96712_update_bits(priv, 0x8a2, 0xf0, 0x30);
162 }
163
max96712_pattern_enable(struct max96712_priv * priv,bool enable)164 static void max96712_pattern_enable(struct max96712_priv *priv, bool enable)
165 {
166 const u32 h_active = 1920;
167 const u32 h_fp = 88;
168 const u32 h_sw = 44;
169 const u32 h_bp = 148;
170 const u32 h_tot = h_active + h_fp + h_sw + h_bp;
171
172 const u32 v_active = 1080;
173 const u32 v_fp = 4;
174 const u32 v_sw = 5;
175 const u32 v_bp = 36;
176 const u32 v_tot = v_active + v_fp + v_sw + v_bp;
177
178 if (!enable) {
179 max96712_write(priv, 0x1051, 0x00);
180 return;
181 }
182
183 /* PCLK 75MHz. */
184 max96712_write(priv, 0x0009, 0x01);
185
186 /* Configure Video Timing Generator for 1920x1080 @ 30 fps. */
187 max96712_write_bulk_value(priv, 0x1052, 0, 3);
188 max96712_write_bulk_value(priv, 0x1055, v_sw * h_tot, 3);
189 max96712_write_bulk_value(priv, 0x1058,
190 (v_active + v_fp + + v_bp) * h_tot, 3);
191 max96712_write_bulk_value(priv, 0x105b, 0, 3);
192 max96712_write_bulk_value(priv, 0x105e, h_sw, 2);
193 max96712_write_bulk_value(priv, 0x1060, h_active + h_fp + h_bp, 2);
194 max96712_write_bulk_value(priv, 0x1062, v_tot, 2);
195 max96712_write_bulk_value(priv, 0x1064,
196 h_tot * (v_sw + v_bp) + (h_sw + h_bp), 3);
197 max96712_write_bulk_value(priv, 0x1067, h_active, 2);
198 max96712_write_bulk_value(priv, 0x1069, h_fp + h_sw + h_bp, 2);
199 max96712_write_bulk_value(priv, 0x106b, v_active, 2);
200
201 /* Generate VS, HS and DE in free-running mode. */
202 max96712_write(priv, 0x1050, 0xfb);
203
204 /* Configure Video Pattern Generator. */
205 if (priv->pattern == MAX96712_PATTERN_CHECKERBOARD) {
206 /* Set checkerboard pattern size. */
207 max96712_write(priv, 0x1074, 0x3c);
208 max96712_write(priv, 0x1075, 0x3c);
209 max96712_write(priv, 0x1076, 0x3c);
210
211 /* Set checkerboard pattern colors. */
212 max96712_write_bulk_value(priv, 0x106e, 0xfecc00, 3);
213 max96712_write_bulk_value(priv, 0x1071, 0x006aa7, 3);
214
215 /* Generate checkerboard pattern. */
216 max96712_write(priv, 0x1051, 0x10);
217 } else {
218 /* Set gradient increment. */
219 max96712_write(priv, 0x106d, 0x10);
220
221 /* Generate gradient pattern. */
222 max96712_write(priv, 0x1051, 0x20);
223 }
224 }
225
max96712_s_stream(struct v4l2_subdev * sd,int enable)226 static int max96712_s_stream(struct v4l2_subdev *sd, int enable)
227 {
228 struct max96712_priv *priv = v4l2_get_subdevdata(sd);
229
230 if (enable) {
231 max96712_pattern_enable(priv, true);
232 max96712_mipi_enable(priv, true);
233 } else {
234 max96712_mipi_enable(priv, false);
235 max96712_pattern_enable(priv, false);
236 }
237
238 return 0;
239 }
240
241 static const struct v4l2_subdev_video_ops max96712_video_ops = {
242 .s_stream = max96712_s_stream,
243 };
244
max96712_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)245 static int max96712_init_state(struct v4l2_subdev *sd,
246 struct v4l2_subdev_state *state)
247 {
248 static const struct v4l2_mbus_framefmt default_fmt = {
249 .width = 1920,
250 .height = 1080,
251 .code = MEDIA_BUS_FMT_RGB888_1X24,
252 .colorspace = V4L2_COLORSPACE_SRGB,
253 .field = V4L2_FIELD_NONE,
254 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
255 .quantization = V4L2_QUANTIZATION_DEFAULT,
256 .xfer_func = V4L2_XFER_FUNC_DEFAULT,
257 };
258 struct v4l2_mbus_framefmt *fmt;
259
260 fmt = v4l2_subdev_state_get_format(state, 0);
261 *fmt = default_fmt;
262
263 return 0;
264 }
265
266 static const struct v4l2_subdev_internal_ops max96712_internal_ops = {
267 .init_state = max96712_init_state,
268 };
269
270 static const struct v4l2_subdev_pad_ops max96712_pad_ops = {
271 .get_fmt = v4l2_subdev_get_fmt,
272 .set_fmt = v4l2_subdev_get_fmt,
273 };
274
275 static const struct v4l2_subdev_ops max96712_subdev_ops = {
276 .video = &max96712_video_ops,
277 .pad = &max96712_pad_ops,
278 };
279
280 static const char * const max96712_test_pattern[] = {
281 "Checkerboard",
282 "Gradient",
283 };
284
max96712_s_ctrl(struct v4l2_ctrl * ctrl)285 static int max96712_s_ctrl(struct v4l2_ctrl *ctrl)
286 {
287 struct max96712_priv *priv =
288 container_of(ctrl->handler, struct max96712_priv, ctrl_handler);
289
290 switch (ctrl->id) {
291 case V4L2_CID_TEST_PATTERN:
292 priv->pattern = ctrl->val ?
293 MAX96712_PATTERN_GRADIENT :
294 MAX96712_PATTERN_CHECKERBOARD;
295 break;
296 }
297 return 0;
298 }
299
300 static const struct v4l2_ctrl_ops max96712_ctrl_ops = {
301 .s_ctrl = max96712_s_ctrl,
302 };
303
max96712_v4l2_register(struct max96712_priv * priv)304 static int max96712_v4l2_register(struct max96712_priv *priv)
305 {
306 long pixel_rate;
307 int ret;
308
309 priv->sd.internal_ops = &max96712_internal_ops;
310 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96712_subdev_ops);
311 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
312 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
313
314 v4l2_ctrl_handler_init(&priv->ctrl_handler, 2);
315
316 /*
317 * TODO: Once V4L2_CID_LINK_FREQ is changed from a menu control to an
318 * INT64 control it should be used here instead of V4L2_CID_PIXEL_RATE.
319 */
320 pixel_rate = MAX96712_DPLL_FREQ / priv->mipi.num_data_lanes * 1000000;
321 v4l2_ctrl_new_std(&priv->ctrl_handler, NULL, V4L2_CID_PIXEL_RATE,
322 pixel_rate, pixel_rate, 1, pixel_rate);
323
324 v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler, &max96712_ctrl_ops,
325 V4L2_CID_TEST_PATTERN,
326 ARRAY_SIZE(max96712_test_pattern) - 1,
327 0, 0, max96712_test_pattern);
328
329 priv->sd.ctrl_handler = &priv->ctrl_handler;
330 ret = priv->ctrl_handler.error;
331 if (ret)
332 goto error;
333
334 priv->pads[0].flags = MEDIA_PAD_FL_SOURCE;
335 ret = media_entity_pads_init(&priv->sd.entity, 1, priv->pads);
336 if (ret)
337 goto error;
338
339 v4l2_set_subdevdata(&priv->sd, priv);
340
341 priv->sd.state_lock = priv->ctrl_handler.lock;
342 ret = v4l2_subdev_init_finalize(&priv->sd);
343 if (ret)
344 goto error;
345
346 ret = v4l2_async_register_subdev(&priv->sd);
347 if (ret < 0) {
348 dev_err(&priv->client->dev, "Unable to register subdevice\n");
349 goto error;
350 }
351
352 return 0;
353 error:
354 v4l2_ctrl_handler_free(&priv->ctrl_handler);
355
356 return ret;
357 }
358
max96712_parse_dt(struct max96712_priv * priv)359 static int max96712_parse_dt(struct max96712_priv *priv)
360 {
361 struct fwnode_handle *ep;
362 struct v4l2_fwnode_endpoint v4l2_ep = {
363 .bus_type = V4L2_MBUS_UNKNOWN,
364 };
365 unsigned int supported_lanes;
366 int ret;
367
368 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(&priv->client->dev), 4,
369 0, 0);
370 if (!ep) {
371 dev_err(&priv->client->dev, "Not connected to subdevice\n");
372 return -EINVAL;
373 }
374
375 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
376 fwnode_handle_put(ep);
377 if (ret) {
378 dev_err(&priv->client->dev, "Could not parse v4l2 endpoint\n");
379 return -EINVAL;
380 }
381
382 switch (v4l2_ep.bus_type) {
383 case V4L2_MBUS_CSI2_DPHY:
384 supported_lanes = 4;
385 priv->cphy = false;
386 break;
387 case V4L2_MBUS_CSI2_CPHY:
388 supported_lanes = 3;
389 priv->cphy = true;
390 break;
391 default:
392 dev_err(&priv->client->dev, "Unsupported bus-type %u\n",
393 v4l2_ep.bus_type);
394 return -EINVAL;
395 }
396
397 if (v4l2_ep.bus.mipi_csi2.num_data_lanes != supported_lanes) {
398 dev_err(&priv->client->dev, "Only %u data lanes supported\n",
399 supported_lanes);
400 return -EINVAL;
401 }
402
403 priv->mipi = v4l2_ep.bus.mipi_csi2;
404
405 return 0;
406 }
407
408 static const struct regmap_config max96712_i2c_regmap = {
409 .reg_bits = 16,
410 .val_bits = 8,
411 .max_register = 0x1f00,
412 };
413
max96712_probe(struct i2c_client * client)414 static int max96712_probe(struct i2c_client *client)
415 {
416 struct max96712_priv *priv;
417 int ret;
418
419 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
420 if (!priv)
421 return -ENOMEM;
422
423 priv->client = client;
424 i2c_set_clientdata(client, priv);
425
426 priv->regmap = devm_regmap_init_i2c(client, &max96712_i2c_regmap);
427 if (IS_ERR(priv->regmap))
428 return PTR_ERR(priv->regmap);
429
430 priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable",
431 GPIOD_OUT_HIGH);
432 if (IS_ERR(priv->gpiod_pwdn))
433 return PTR_ERR(priv->gpiod_pwdn);
434
435 gpiod_set_consumer_name(priv->gpiod_pwdn, "max96712-pwdn");
436 gpiod_set_value_cansleep(priv->gpiod_pwdn, 1);
437
438 if (priv->gpiod_pwdn)
439 usleep_range(4000, 5000);
440
441 if (max96712_read(priv, 0x4a) != MAX96712_ID)
442 return -ENODEV;
443
444 max96712_reset(priv);
445
446 ret = max96712_parse_dt(priv);
447 if (ret)
448 return ret;
449
450 max96712_mipi_configure(priv);
451
452 return max96712_v4l2_register(priv);
453 }
454
max96712_remove(struct i2c_client * client)455 static void max96712_remove(struct i2c_client *client)
456 {
457 struct max96712_priv *priv = i2c_get_clientdata(client);
458
459 v4l2_async_unregister_subdev(&priv->sd);
460
461 gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
462 }
463
464 static const struct of_device_id max96712_of_table[] = {
465 { .compatible = "maxim,max96712" },
466 { /* sentinel */ },
467 };
468 MODULE_DEVICE_TABLE(of, max96712_of_table);
469
470 static struct i2c_driver max96712_i2c_driver = {
471 .driver = {
472 .name = "max96712",
473 .of_match_table = of_match_ptr(max96712_of_table),
474 },
475 .probe = max96712_probe,
476 .remove = max96712_remove,
477 };
478
479 module_i2c_driver(max96712_i2c_driver);
480
481 MODULE_DESCRIPTION("Maxim MAX96712 Quad GMSL2 Deserializer Driver");
482 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
483 MODULE_LICENSE("GPL");
484