1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2016
4  *
5  * Author: Gerald Baeza <gerald.baeza@st.com>
6  *
7  * Inspired by timer-stm32.c from Maxime Coquelin
8  *             pwm-atmel.c from Bo Shen
9  */
10 
11 #include <linux/bitfield.h>
12 #include <linux/mfd/stm32-timers.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pwm.h>
18 
19 #define CCMR_CHANNEL_SHIFT 8
20 #define CCMR_CHANNEL_MASK  0xFF
21 #define MAX_BREAKINPUT 2
22 
23 struct stm32_breakinput {
24 	u32 index;
25 	u32 level;
26 	u32 filter;
27 };
28 
29 struct stm32_pwm {
30 	struct mutex lock; /* protect pwm config/enable */
31 	struct clk *clk;
32 	struct regmap *regmap;
33 	u32 max_arr;
34 	bool have_complementary_output;
35 	struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
36 	unsigned int num_breakinputs;
37 	u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
38 };
39 
to_stm32_pwm_dev(struct pwm_chip * chip)40 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
41 {
42 	return pwmchip_get_drvdata(chip);
43 }
44 
active_channels(struct stm32_pwm * dev)45 static u32 active_channels(struct stm32_pwm *dev)
46 {
47 	u32 ccer;
48 
49 	regmap_read(dev->regmap, TIM_CCER, &ccer);
50 
51 	return ccer & TIM_CCER_CCXE;
52 }
53 
54 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
55 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
56 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
57 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
58 
59 /*
60  * Capture using PWM input mode:
61  *                              ___          ___
62  * TI[1, 2, 3 or 4]: ........._|   |________|
63  *                             ^0  ^1       ^2
64  *                              .   .        .
65  *                              .   .        XXXXX
66  *                              .   .   XXXXX     |
67  *                              .  XXXXX     .    |
68  *                            XXXXX .        .    |
69  * COUNTER:        ______XXXXX  .   .        .    |_XXX
70  *                 start^       .   .        .        ^stop
71  *                      .       .   .        .
72  *                      v       v   .        v
73  *                                  v
74  * CCR1/CCR3:       tx..........t0...........t2
75  * CCR2/CCR4:       tx..............t1.........
76  *
77  * DMA burst transfer:          |            |
78  *                              v            v
79  * DMA buffer:                  { t0, tx }   { t2, t1 }
80  * DMA done:                                 ^
81  *
82  * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
83  *    + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
84  * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
85  * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
86  *    + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
87  *
88  * DMA done, compute:
89  * - Period     = t2 - t0
90  * - Duty cycle = t1 - t0
91  */
stm32_pwm_raw_capture(struct pwm_chip * chip,struct pwm_device * pwm,unsigned long tmo_ms,u32 * raw_prd,u32 * raw_dty)92 static int stm32_pwm_raw_capture(struct pwm_chip *chip, struct pwm_device *pwm,
93 				 unsigned long tmo_ms, u32 *raw_prd,
94 				 u32 *raw_dty)
95 {
96 	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
97 	struct device *parent = pwmchip_parent(chip)->parent;
98 	enum stm32_timers_dmas dma_id;
99 	u32 ccen, ccr;
100 	int ret;
101 
102 	/* Ensure registers have been updated, enable counter and capture */
103 	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
104 	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
105 
106 	/* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
107 	dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
108 	ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
109 	ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
110 	regmap_set_bits(priv->regmap, TIM_CCER, ccen);
111 
112 	/*
113 	 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
114 	 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
115 	 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
116 	 * or { CCR3, CCR4 }, { CCR3, CCR4 }
117 	 */
118 	ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
119 					  2, tmo_ms);
120 	if (ret)
121 		goto stop;
122 
123 	/* Period: t2 - t0 (take care of counter overflow) */
124 	if (priv->capture[0] <= priv->capture[2])
125 		*raw_prd = priv->capture[2] - priv->capture[0];
126 	else
127 		*raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
128 
129 	/* Duty cycle capture requires at least two capture units */
130 	if (pwm->chip->npwm < 2)
131 		*raw_dty = 0;
132 	else if (priv->capture[0] <= priv->capture[3])
133 		*raw_dty = priv->capture[3] - priv->capture[0];
134 	else
135 		*raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
136 
137 	if (*raw_dty > *raw_prd) {
138 		/*
139 		 * Race beetween PWM input and DMA: it may happen
140 		 * falling edge triggers new capture on TI2/4 before DMA
141 		 * had a chance to read CCR2/4. It means capture[1]
142 		 * contains period + duty_cycle. So, subtract period.
143 		 */
144 		*raw_dty -= *raw_prd;
145 	}
146 
147 stop:
148 	regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
149 	regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
150 
151 	return ret;
152 }
153 
stm32_pwm_capture(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_capture * result,unsigned long tmo_ms)154 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
155 			     struct pwm_capture *result, unsigned long tmo_ms)
156 {
157 	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
158 	unsigned long long prd, div, dty;
159 	unsigned long rate;
160 	unsigned int psc = 0, icpsc, scale;
161 	u32 raw_prd = 0, raw_dty = 0;
162 	int ret = 0;
163 
164 	mutex_lock(&priv->lock);
165 
166 	if (active_channels(priv)) {
167 		ret = -EBUSY;
168 		goto unlock;
169 	}
170 
171 	ret = clk_enable(priv->clk);
172 	if (ret) {
173 		dev_err(pwmchip_parent(chip), "failed to enable counter clock\n");
174 		goto unlock;
175 	}
176 
177 	rate = clk_get_rate(priv->clk);
178 	if (!rate) {
179 		ret = -EINVAL;
180 		goto clk_dis;
181 	}
182 
183 	/* prescaler: fit timeout window provided by upper layer */
184 	div = (unsigned long long)rate * (unsigned long long)tmo_ms;
185 	do_div(div, MSEC_PER_SEC);
186 	prd = div;
187 	while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
188 		psc++;
189 		div = prd;
190 		do_div(div, psc + 1);
191 	}
192 	regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
193 	regmap_write(priv->regmap, TIM_PSC, psc);
194 
195 	/* Reset input selector to its default input and disable slave mode */
196 	regmap_write(priv->regmap, TIM_TISEL, 0x0);
197 	regmap_write(priv->regmap, TIM_SMCR, 0x0);
198 
199 	/* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
200 	regmap_update_bits(priv->regmap,
201 			   pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
202 			   TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
203 			   TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
204 			   TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
205 
206 	/* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
207 	regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
208 			   TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
209 			   TIM_CCER_CC2P : TIM_CCER_CC4P);
210 
211 	ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
212 	if (ret)
213 		goto stop;
214 
215 	/*
216 	 * Got a capture. Try to improve accuracy at high rates:
217 	 * - decrease counter clock prescaler, scale up to max rate.
218 	 * - use input prescaler, capture once every /2 /4 or /8 edges.
219 	 */
220 	if (raw_prd) {
221 		u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
222 
223 		scale = max_arr / min(max_arr, raw_prd);
224 	} else {
225 		scale = priv->max_arr; /* below resolution, use max scale */
226 	}
227 
228 	if (psc && scale > 1) {
229 		/* 2nd measure with new scale */
230 		psc /= scale;
231 		regmap_write(priv->regmap, TIM_PSC, psc);
232 		ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd,
233 					    &raw_dty);
234 		if (ret)
235 			goto stop;
236 	}
237 
238 	/* Compute intermediate period not to exceed timeout at low rates */
239 	prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
240 	do_div(prd, rate);
241 
242 	for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
243 		/* input prescaler: also keep arbitrary margin */
244 		if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
245 			break;
246 		if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
247 			break;
248 	}
249 
250 	if (!icpsc)
251 		goto done;
252 
253 	/* Last chance to improve period accuracy, using input prescaler */
254 	regmap_update_bits(priv->regmap,
255 			   pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
256 			   TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
257 			   FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
258 			   FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
259 
260 	ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
261 	if (ret)
262 		goto stop;
263 
264 	if (raw_dty >= (raw_prd >> icpsc)) {
265 		/*
266 		 * We may fall here using input prescaler, when input
267 		 * capture starts on high side (before falling edge).
268 		 * Example with icpsc to capture on each 4 events:
269 		 *
270 		 *       start   1st capture                     2nd capture
271 		 *         v     v                               v
272 		 *         ___   _____   _____   _____   _____   ____
273 		 * TI1..4     |__|    |__|    |__|    |__|    |__|
274 		 *            v  v    .  .    .  .    .       v  v
275 		 * icpsc1/3:  .  0    .  1    .  2    .  3    .  0
276 		 * icpsc2/4:  0       1       2       3       0
277 		 *            v  v                            v  v
278 		 * CCR1/3  ......t0..............................t2
279 		 * CCR2/4  ..t1..............................t1'...
280 		 *               .                            .  .
281 		 * Capture0:     .<----------------------------->.
282 		 * Capture1:     .<-------------------------->.  .
283 		 *               .                            .  .
284 		 * Period:       .<------>                    .  .
285 		 * Low side:                                  .<>.
286 		 *
287 		 * Result:
288 		 * - Period = Capture0 / icpsc
289 		 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
290 		 */
291 		raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
292 	}
293 
294 done:
295 	prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
296 	result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
297 	dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
298 	result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
299 stop:
300 	regmap_write(priv->regmap, TIM_CCER, 0);
301 	regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
302 	regmap_write(priv->regmap, TIM_PSC, 0);
303 clk_dis:
304 	clk_disable(priv->clk);
305 unlock:
306 	mutex_unlock(&priv->lock);
307 
308 	return ret;
309 }
310 
stm32_pwm_config(struct stm32_pwm * priv,unsigned int ch,u64 duty_ns,u64 period_ns)311 static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch,
312 			    u64 duty_ns, u64 period_ns)
313 {
314 	unsigned long long prd, dty;
315 	unsigned long long prescaler;
316 	u32 ccmr, mask, shift;
317 
318 	/*
319 	 * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so
320 	 * the calculations here won't overflow.
321 	 * First we need to find the minimal value for prescaler such that
322 	 *
323 	 *        period_ns * clkrate
324 	 *   ------------------------------ < max_arr + 1
325 	 *   NSEC_PER_SEC * (prescaler + 1)
326 	 *
327 	 * This equation is equivalent to
328 	 *
329 	 *        period_ns * clkrate
330 	 *   ---------------------------- < prescaler + 1
331 	 *   NSEC_PER_SEC * (max_arr + 1)
332 	 *
333 	 * Using integer division and knowing that the right hand side is
334 	 * integer, this is further equivalent to
335 	 *
336 	 *   (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler
337 	 */
338 
339 	prescaler = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),
340 					(u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));
341 	if (prescaler > MAX_TIM_PSC)
342 		return -EINVAL;
343 
344 	prd = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),
345 				  (u64)NSEC_PER_SEC * (prescaler + 1));
346 	if (!prd)
347 		return -EINVAL;
348 
349 	/*
350 	 * All channels share the same prescaler and counter so when two
351 	 * channels are active at the same time we can't change them
352 	 */
353 	if (active_channels(priv) & ~(1 << ch * 4)) {
354 		u32 psc, arr;
355 
356 		regmap_read(priv->regmap, TIM_PSC, &psc);
357 		regmap_read(priv->regmap, TIM_ARR, &arr);
358 
359 		if ((psc != prescaler) || (arr != prd - 1))
360 			return -EBUSY;
361 	}
362 
363 	regmap_write(priv->regmap, TIM_PSC, prescaler);
364 	regmap_write(priv->regmap, TIM_ARR, prd - 1);
365 	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
366 
367 	/* Calculate the duty cycles */
368 	dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk),
369 				  (u64)NSEC_PER_SEC * (prescaler + 1));
370 
371 	regmap_write(priv->regmap, TIM_CCRx(ch + 1), dty);
372 
373 	/* Configure output mode */
374 	shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
375 	ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
376 	mask = CCMR_CHANNEL_MASK << shift;
377 
378 	if (ch < 2)
379 		regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
380 	else
381 		regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
382 
383 	regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
384 
385 	return 0;
386 }
387 
stm32_pwm_set_polarity(struct stm32_pwm * priv,unsigned int ch,enum pwm_polarity polarity)388 static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch,
389 				  enum pwm_polarity polarity)
390 {
391 	u32 mask;
392 
393 	mask = TIM_CCER_CCxP(ch + 1);
394 	if (priv->have_complementary_output)
395 		mask |= TIM_CCER_CCxNP(ch + 1);
396 
397 	regmap_update_bits(priv->regmap, TIM_CCER, mask,
398 			   polarity == PWM_POLARITY_NORMAL ? 0 : mask);
399 
400 	return 0;
401 }
402 
stm32_pwm_enable(struct stm32_pwm * priv,unsigned int ch)403 static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch)
404 {
405 	u32 mask;
406 	int ret;
407 
408 	ret = clk_enable(priv->clk);
409 	if (ret)
410 		return ret;
411 
412 	/* Enable channel */
413 	mask = TIM_CCER_CCxE(ch + 1);
414 	if (priv->have_complementary_output)
415 		mask |= TIM_CCER_CCxNE(ch + 1);
416 
417 	regmap_set_bits(priv->regmap, TIM_CCER, mask);
418 
419 	/* Make sure that registers are updated */
420 	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
421 
422 	/* Enable controller */
423 	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
424 
425 	return 0;
426 }
427 
stm32_pwm_disable(struct stm32_pwm * priv,unsigned int ch)428 static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch)
429 {
430 	u32 mask;
431 
432 	/* Disable channel */
433 	mask = TIM_CCER_CCxE(ch + 1);
434 	if (priv->have_complementary_output)
435 		mask |= TIM_CCER_CCxNE(ch + 1);
436 
437 	regmap_clear_bits(priv->regmap, TIM_CCER, mask);
438 
439 	/* When all channels are disabled, we can disable the controller */
440 	if (!active_channels(priv))
441 		regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
442 
443 	clk_disable(priv->clk);
444 }
445 
stm32_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)446 static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
447 			   const struct pwm_state *state)
448 {
449 	bool enabled;
450 	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
451 	int ret;
452 
453 	enabled = pwm->state.enabled;
454 
455 	if (!state->enabled) {
456 		if (enabled)
457 			stm32_pwm_disable(priv, pwm->hwpwm);
458 		return 0;
459 	}
460 
461 	if (state->polarity != pwm->state.polarity)
462 		stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
463 
464 	ret = stm32_pwm_config(priv, pwm->hwpwm,
465 			       state->duty_cycle, state->period);
466 	if (ret)
467 		return ret;
468 
469 	if (!enabled && state->enabled)
470 		ret = stm32_pwm_enable(priv, pwm->hwpwm);
471 
472 	return ret;
473 }
474 
stm32_pwm_apply_locked(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)475 static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
476 				  const struct pwm_state *state)
477 {
478 	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
479 	int ret;
480 
481 	/* protect common prescaler for all active channels */
482 	mutex_lock(&priv->lock);
483 	ret = stm32_pwm_apply(chip, pwm, state);
484 	mutex_unlock(&priv->lock);
485 
486 	return ret;
487 }
488 
stm32_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)489 static int stm32_pwm_get_state(struct pwm_chip *chip,
490 			       struct pwm_device *pwm, struct pwm_state *state)
491 {
492 	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
493 	int ch = pwm->hwpwm;
494 	unsigned long rate;
495 	u32 ccer, psc, arr, ccr;
496 	u64 dty, prd;
497 	int ret;
498 
499 	mutex_lock(&priv->lock);
500 
501 	ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
502 	if (ret)
503 		goto out;
504 
505 	state->enabled = ccer & TIM_CCER_CCxE(ch + 1);
506 	state->polarity = (ccer & TIM_CCER_CCxP(ch + 1)) ?
507 			  PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
508 	ret = regmap_read(priv->regmap, TIM_PSC, &psc);
509 	if (ret)
510 		goto out;
511 	ret = regmap_read(priv->regmap, TIM_ARR, &arr);
512 	if (ret)
513 		goto out;
514 	ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &ccr);
515 	if (ret)
516 		goto out;
517 
518 	rate = clk_get_rate(priv->clk);
519 
520 	prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1);
521 	state->period = DIV_ROUND_UP_ULL(prd, rate);
522 	dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr;
523 	state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
524 
525 out:
526 	mutex_unlock(&priv->lock);
527 	return ret;
528 }
529 
530 static const struct pwm_ops stm32pwm_ops = {
531 	.apply = stm32_pwm_apply_locked,
532 	.get_state = stm32_pwm_get_state,
533 	.capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
534 };
535 
stm32_pwm_set_breakinput(struct stm32_pwm * priv,const struct stm32_breakinput * bi)536 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
537 				    const struct stm32_breakinput *bi)
538 {
539 	u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
540 	u32 bke = TIM_BDTR_BKE(bi->index);
541 	u32 bkp = TIM_BDTR_BKP(bi->index);
542 	u32 bkf = TIM_BDTR_BKF(bi->index);
543 	u32 mask = bkf | bkp | bke;
544 	u32 bdtr;
545 
546 	bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
547 
548 	if (bi->level)
549 		bdtr |= bkp;
550 
551 	regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
552 
553 	regmap_read(priv->regmap, TIM_BDTR, &bdtr);
554 
555 	return (bdtr & bke) ? 0 : -EINVAL;
556 }
557 
stm32_pwm_apply_breakinputs(struct stm32_pwm * priv)558 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
559 {
560 	unsigned int i;
561 	int ret;
562 
563 	for (i = 0; i < priv->num_breakinputs; i++) {
564 		ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
565 		if (ret < 0)
566 			return ret;
567 	}
568 
569 	return 0;
570 }
571 
stm32_pwm_probe_breakinputs(struct stm32_pwm * priv,struct device_node * np)572 static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
573 				       struct device_node *np)
574 {
575 	int nb, ret, array_size;
576 	unsigned int i;
577 
578 	nb = of_property_count_elems_of_size(np, "st,breakinput",
579 					     sizeof(struct stm32_breakinput));
580 
581 	/*
582 	 * Because "st,breakinput" parameter is optional do not make probe
583 	 * failed if it doesn't exist.
584 	 */
585 	if (nb <= 0)
586 		return 0;
587 
588 	if (nb > MAX_BREAKINPUT)
589 		return -EINVAL;
590 
591 	priv->num_breakinputs = nb;
592 	array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
593 	ret = of_property_read_u32_array(np, "st,breakinput",
594 					 (u32 *)priv->breakinputs, array_size);
595 	if (ret)
596 		return ret;
597 
598 	for (i = 0; i < priv->num_breakinputs; i++) {
599 		if (priv->breakinputs[i].index > 1 ||
600 		    priv->breakinputs[i].level > 1 ||
601 		    priv->breakinputs[i].filter > 15)
602 			return -EINVAL;
603 	}
604 
605 	return stm32_pwm_apply_breakinputs(priv);
606 }
607 
stm32_pwm_detect_complementary(struct stm32_pwm * priv)608 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
609 {
610 	u32 ccer;
611 
612 	/*
613 	 * If complementary bit doesn't exist writing 1 will have no
614 	 * effect so we can detect it.
615 	 */
616 	regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
617 	regmap_read(priv->regmap, TIM_CCER, &ccer);
618 	regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
619 
620 	priv->have_complementary_output = (ccer != 0);
621 }
622 
stm32_pwm_detect_channels(struct regmap * regmap,unsigned int * num_enabled)623 static unsigned int stm32_pwm_detect_channels(struct regmap *regmap,
624 					      unsigned int *num_enabled)
625 {
626 	u32 ccer, ccer_backup;
627 
628 	/*
629 	 * If channels enable bits don't exist writing 1 will have no
630 	 * effect so we can detect and count them.
631 	 */
632 	regmap_read(regmap, TIM_CCER, &ccer_backup);
633 	regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE);
634 	regmap_read(regmap, TIM_CCER, &ccer);
635 	regmap_write(regmap, TIM_CCER, ccer_backup);
636 
637 	*num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE);
638 
639 	return hweight32(ccer & TIM_CCER_CCXE);
640 }
641 
stm32_pwm_probe(struct platform_device * pdev)642 static int stm32_pwm_probe(struct platform_device *pdev)
643 {
644 	struct device *dev = &pdev->dev;
645 	struct device_node *np = dev->of_node;
646 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
647 	struct pwm_chip *chip;
648 	struct stm32_pwm *priv;
649 	unsigned int npwm, num_enabled;
650 	unsigned int i;
651 	int ret;
652 
653 	npwm = stm32_pwm_detect_channels(ddata->regmap, &num_enabled);
654 
655 	chip = devm_pwmchip_alloc(dev, npwm, sizeof(*priv));
656 	if (IS_ERR(chip))
657 		return PTR_ERR(chip);
658 	priv = to_stm32_pwm_dev(chip);
659 
660 	mutex_init(&priv->lock);
661 	priv->regmap = ddata->regmap;
662 	priv->clk = ddata->clk;
663 	priv->max_arr = ddata->max_arr;
664 
665 	if (!priv->regmap || !priv->clk)
666 		return dev_err_probe(dev, -EINVAL, "Failed to get %s\n",
667 				     priv->regmap ? "clk" : "regmap");
668 
669 	ret = stm32_pwm_probe_breakinputs(priv, np);
670 	if (ret)
671 		return dev_err_probe(dev, ret,
672 				     "Failed to configure breakinputs\n");
673 
674 	stm32_pwm_detect_complementary(priv);
675 
676 	ret = devm_clk_rate_exclusive_get(dev, priv->clk);
677 	if (ret)
678 		return dev_err_probe(dev, ret, "Failed to lock clock\n");
679 
680 	/*
681 	 * With the clk running with not more than 1 GHz the calculations in
682 	 * .apply() won't overflow.
683 	 */
684 	if (clk_get_rate(priv->clk) > 1000000000)
685 		return dev_err_probe(dev, -EINVAL, "Clock freq too high (%lu)\n",
686 				     clk_get_rate(priv->clk));
687 
688 	chip->ops = &stm32pwm_ops;
689 
690 	/* Initialize clock refcount to number of enabled PWM channels. */
691 	for (i = 0; i < num_enabled; i++)
692 		clk_enable(priv->clk);
693 
694 	ret = devm_pwmchip_add(dev, chip);
695 	if (ret < 0)
696 		return dev_err_probe(dev, ret,
697 				     "Failed to register pwmchip\n");
698 
699 	platform_set_drvdata(pdev, chip);
700 
701 	return 0;
702 }
703 
stm32_pwm_suspend(struct device * dev)704 static int stm32_pwm_suspend(struct device *dev)
705 {
706 	struct pwm_chip *chip = dev_get_drvdata(dev);
707 	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
708 	unsigned int i;
709 	u32 ccer, mask;
710 
711 	/* Look for active channels */
712 	ccer = active_channels(priv);
713 
714 	for (i = 0; i < chip->npwm; i++) {
715 		mask = TIM_CCER_CCxE(i + 1);
716 		if (ccer & mask) {
717 			dev_err(dev, "PWM %u still in use by consumer %s\n",
718 				i, chip->pwms[i].label);
719 			return -EBUSY;
720 		}
721 	}
722 
723 	return pinctrl_pm_select_sleep_state(dev);
724 }
725 
stm32_pwm_resume(struct device * dev)726 static int stm32_pwm_resume(struct device *dev)
727 {
728 	struct pwm_chip *chip = dev_get_drvdata(dev);
729 	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
730 	int ret;
731 
732 	ret = pinctrl_pm_select_default_state(dev);
733 	if (ret)
734 		return ret;
735 
736 	/* restore breakinput registers that may have been lost in low power */
737 	return stm32_pwm_apply_breakinputs(priv);
738 }
739 
740 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
741 
742 static const struct of_device_id stm32_pwm_of_match[] = {
743 	{ .compatible = "st,stm32-pwm",	},
744 	{ /* end node */ },
745 };
746 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
747 
748 static struct platform_driver stm32_pwm_driver = {
749 	.probe	= stm32_pwm_probe,
750 	.driver	= {
751 		.name = "stm32-pwm",
752 		.of_match_table = stm32_pwm_of_match,
753 		.pm = pm_ptr(&stm32_pwm_pm_ops),
754 	},
755 };
756 module_platform_driver(stm32_pwm_driver);
757 
758 MODULE_ALIAS("platform:stm32-pwm");
759 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
760 MODULE_LICENSE("GPL v2");
761