1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices ADP5585 PWM driver
4 *
5 * Copyright 2022 NXP
6 * Copyright 2024 Ideas on Board Oy
7 *
8 * Limitations:
9 * - The .apply() operation executes atomically, but may not wait for the
10 * period to complete (this is not documented and would need to be tested).
11 * - Disabling the PWM drives the output pin to a low level immediately.
12 * - The hardware can only generate normal polarity output.
13 */
14
15 #include <asm/byteorder.h>
16
17 #include <linux/device.h>
18 #include <linux/err.h>
19 #include <linux/math64.h>
20 #include <linux/mfd/adp5585.h>
21 #include <linux/minmax.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/pwm.h>
25 #include <linux/regmap.h>
26 #include <linux/time.h>
27 #include <linux/types.h>
28
29 #define ADP5585_PWM_CHAN_NUM 1
30
31 #define ADP5585_PWM_OSC_FREQ_HZ 1000000U
32 #define ADP5585_PWM_MIN_PERIOD_NS (2ULL * NSEC_PER_SEC / ADP5585_PWM_OSC_FREQ_HZ)
33 #define ADP5585_PWM_MAX_PERIOD_NS (2ULL * 0xffff * NSEC_PER_SEC / ADP5585_PWM_OSC_FREQ_HZ)
34
pwm_adp5585_request(struct pwm_chip * chip,struct pwm_device * pwm)35 static int pwm_adp5585_request(struct pwm_chip *chip, struct pwm_device *pwm)
36 {
37 struct regmap *regmap = pwmchip_get_drvdata(chip);
38
39 /* Configure the R3 pin as PWM output. */
40 return regmap_update_bits(regmap, ADP5585_PIN_CONFIG_C,
41 ADP5585_R3_EXTEND_CFG_MASK,
42 ADP5585_R3_EXTEND_CFG_PWM_OUT);
43 }
44
pwm_adp5585_free(struct pwm_chip * chip,struct pwm_device * pwm)45 static void pwm_adp5585_free(struct pwm_chip *chip, struct pwm_device *pwm)
46 {
47 struct regmap *regmap = pwmchip_get_drvdata(chip);
48
49 regmap_update_bits(regmap, ADP5585_PIN_CONFIG_C,
50 ADP5585_R3_EXTEND_CFG_MASK,
51 ADP5585_R3_EXTEND_CFG_GPIO4);
52 }
53
pwm_adp5585_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)54 static int pwm_adp5585_apply(struct pwm_chip *chip,
55 struct pwm_device *pwm,
56 const struct pwm_state *state)
57 {
58 struct regmap *regmap = pwmchip_get_drvdata(chip);
59 u64 period, duty_cycle;
60 u32 on, off;
61 __le16 val;
62 int ret;
63
64 if (!state->enabled) {
65 regmap_clear_bits(regmap, ADP5585_GENERAL_CFG, ADP5585_OSC_EN);
66 regmap_clear_bits(regmap, ADP5585_PWM_CFG, ADP5585_PWM_EN);
67 return 0;
68 }
69
70 if (state->polarity != PWM_POLARITY_NORMAL)
71 return -EINVAL;
72
73 if (state->period < ADP5585_PWM_MIN_PERIOD_NS)
74 return -EINVAL;
75
76 period = min(state->period, ADP5585_PWM_MAX_PERIOD_NS);
77 duty_cycle = min(state->duty_cycle, period);
78
79 /*
80 * Compute the on and off time. As the internal oscillator frequency is
81 * 1MHz, the calculation can be simplified without loss of precision.
82 */
83 on = div_u64(duty_cycle, NSEC_PER_SEC / ADP5585_PWM_OSC_FREQ_HZ);
84 off = div_u64(period, NSEC_PER_SEC / ADP5585_PWM_OSC_FREQ_HZ) - on;
85
86 val = cpu_to_le16(off);
87 ret = regmap_bulk_write(regmap, ADP5585_PWM_OFFT_LOW, &val, 2);
88 if (ret)
89 return ret;
90
91 val = cpu_to_le16(on);
92 ret = regmap_bulk_write(regmap, ADP5585_PWM_ONT_LOW, &val, 2);
93 if (ret)
94 return ret;
95
96 /* Enable PWM in continuous mode and no external AND'ing. */
97 ret = regmap_update_bits(regmap, ADP5585_PWM_CFG,
98 ADP5585_PWM_IN_AND | ADP5585_PWM_MODE |
99 ADP5585_PWM_EN, ADP5585_PWM_EN);
100 if (ret)
101 return ret;
102
103 ret = regmap_set_bits(regmap, ADP5585_GENERAL_CFG, ADP5585_OSC_EN);
104 if (ret)
105 return ret;
106
107 return regmap_set_bits(regmap, ADP5585_PWM_CFG, ADP5585_PWM_EN);
108 }
109
pwm_adp5585_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)110 static int pwm_adp5585_get_state(struct pwm_chip *chip,
111 struct pwm_device *pwm,
112 struct pwm_state *state)
113 {
114 struct regmap *regmap = pwmchip_get_drvdata(chip);
115 unsigned int on, off;
116 unsigned int val;
117 __le16 on_off;
118 int ret;
119
120 ret = regmap_bulk_read(regmap, ADP5585_PWM_OFFT_LOW, &on_off, 2);
121 if (ret)
122 return ret;
123 off = le16_to_cpu(on_off);
124
125 ret = regmap_bulk_read(regmap, ADP5585_PWM_ONT_LOW, &on_off, 2);
126 if (ret)
127 return ret;
128 on = le16_to_cpu(on_off);
129
130 state->duty_cycle = on * (NSEC_PER_SEC / ADP5585_PWM_OSC_FREQ_HZ);
131 state->period = (on + off) * (NSEC_PER_SEC / ADP5585_PWM_OSC_FREQ_HZ);
132
133 state->polarity = PWM_POLARITY_NORMAL;
134
135 regmap_read(regmap, ADP5585_PWM_CFG, &val);
136 state->enabled = !!(val & ADP5585_PWM_EN);
137
138 return 0;
139 }
140
141 static const struct pwm_ops adp5585_pwm_ops = {
142 .request = pwm_adp5585_request,
143 .free = pwm_adp5585_free,
144 .apply = pwm_adp5585_apply,
145 .get_state = pwm_adp5585_get_state,
146 };
147
adp5585_pwm_probe(struct platform_device * pdev)148 static int adp5585_pwm_probe(struct platform_device *pdev)
149 {
150 struct device *dev = &pdev->dev;
151 struct adp5585_dev *adp5585 = dev_get_drvdata(dev->parent);
152 struct pwm_chip *chip;
153 int ret;
154
155 chip = devm_pwmchip_alloc(dev, ADP5585_PWM_CHAN_NUM, 0);
156 if (IS_ERR(chip))
157 return PTR_ERR(chip);
158
159 device_set_of_node_from_dev(dev, dev->parent);
160
161 pwmchip_set_drvdata(chip, adp5585->regmap);
162 chip->ops = &adp5585_pwm_ops;
163
164 ret = devm_pwmchip_add(dev, chip);
165 if (ret)
166 return dev_err_probe(dev, ret, "failed to add PWM chip\n");
167
168 return 0;
169 }
170
171 static const struct platform_device_id adp5585_pwm_id_table[] = {
172 { "adp5585-pwm" },
173 { /* Sentinel */ }
174 };
175 MODULE_DEVICE_TABLE(platform, adp5585_pwm_id_table);
176
177 static struct platform_driver adp5585_pwm_driver = {
178 .driver = {
179 .name = "adp5585-pwm",
180 },
181 .probe = adp5585_pwm_probe,
182 .id_table = adp5585_pwm_id_table,
183 };
184 module_platform_driver(adp5585_pwm_driver);
185
186 MODULE_AUTHOR("Xiaoning Wang <xiaoning.wang@nxp.com>");
187 MODULE_DESCRIPTION("ADP5585 PWM Driver");
188 MODULE_LICENSE("GPL");
189