1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
4 *
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/irqchip/chained_irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_pci.h>
22 #include <linux/pci.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/resource.h>
27 #include <linux/types.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/regmap.h>
30 #include <linux/gpio/consumer.h>
31
32 #include "../../pci.h"
33 #include "pcie-designware.h"
34
35 /* PCIe controller wrapper DRA7XX configuration registers */
36
37 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
38 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
39 #define ERR_SYS BIT(0)
40 #define ERR_FATAL BIT(1)
41 #define ERR_NONFATAL BIT(2)
42 #define ERR_COR BIT(3)
43 #define ERR_AXI BIT(4)
44 #define ERR_ECRC BIT(5)
45 #define PME_TURN_OFF BIT(8)
46 #define PME_TO_ACK BIT(9)
47 #define PM_PME BIT(10)
48 #define LINK_REQ_RST BIT(11)
49 #define LINK_UP_EVT BIT(12)
50 #define CFG_BME_EVT BIT(13)
51 #define CFG_MSE_EVT BIT(14)
52 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
53 ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
54 LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
55
56 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
57 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
58 #define INTA BIT(0)
59 #define INTB BIT(1)
60 #define INTC BIT(2)
61 #define INTD BIT(3)
62 #define MSI BIT(4)
63 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
64
65 #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
66 #define DEVICE_TYPE_EP 0x0
67 #define DEVICE_TYPE_LEG_EP 0x1
68 #define DEVICE_TYPE_RC 0x4
69
70 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
71 #define LTSSM_EN 0x1
72
73 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
74 #define LINK_UP BIT(16)
75 #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
76
77 #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
78 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
79
80 #define PCIECTRL_TI_CONF_MSI_XMT 0x012c
81 #define MSI_REQ_GRANT BIT(0)
82 #define MSI_VECTOR_SHIFT 7
83
84 #define PCIE_1LANE_2LANE_SELECTION BIT(13)
85 #define PCIE_B1C0_MODE_SEL BIT(2)
86 #define PCIE_B0_B1_TSYNCEN BIT(0)
87
88 struct dra7xx_pcie {
89 struct dw_pcie *pci;
90 void __iomem *base; /* DT ti_conf */
91 int phy_count; /* DT phy-names count */
92 struct phy **phy;
93 struct irq_domain *irq_domain;
94 struct clk *clk;
95 enum dw_pcie_device_mode mode;
96 };
97
98 struct dra7xx_pcie_of_data {
99 enum dw_pcie_device_mode mode;
100 u32 b1co_mode_sel_mask;
101 };
102
103 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
104
dra7xx_pcie_readl(struct dra7xx_pcie * pcie,u32 offset)105 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
106 {
107 return readl(pcie->base + offset);
108 }
109
dra7xx_pcie_writel(struct dra7xx_pcie * pcie,u32 offset,u32 value)110 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
111 u32 value)
112 {
113 writel(value, pcie->base + offset);
114 }
115
dra7xx_pcie_cpu_addr_fixup(struct dw_pcie * pci,u64 cpu_addr)116 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
117 {
118 return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR;
119 }
120
dra7xx_pcie_link_up(struct dw_pcie * pci)121 static int dra7xx_pcie_link_up(struct dw_pcie *pci)
122 {
123 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
124 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
125
126 return !!(reg & LINK_UP);
127 }
128
dra7xx_pcie_stop_link(struct dw_pcie * pci)129 static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
130 {
131 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
132 u32 reg;
133
134 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
135 reg &= ~LTSSM_EN;
136 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
137 }
138
dra7xx_pcie_establish_link(struct dw_pcie * pci)139 static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
140 {
141 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
142 struct device *dev = pci->dev;
143 u32 reg;
144
145 if (dw_pcie_link_up(pci)) {
146 dev_err(dev, "link is already up\n");
147 return 0;
148 }
149
150 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
151 reg |= LTSSM_EN;
152 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
153
154 return 0;
155 }
156
dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie * dra7xx)157 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
158 {
159 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
160 LEG_EP_INTERRUPTS | MSI);
161
162 dra7xx_pcie_writel(dra7xx,
163 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
164 MSI | LEG_EP_INTERRUPTS);
165 }
166
dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie * dra7xx)167 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
168 {
169 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
170 INTERRUPTS);
171 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
172 INTERRUPTS);
173 }
174
dra7xx_pcie_enable_interrupts(struct dra7xx_pcie * dra7xx)175 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
176 {
177 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
178 dra7xx_pcie_enable_msi_interrupts(dra7xx);
179 }
180
dra7xx_pcie_host_init(struct dw_pcie_rp * pp)181 static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp)
182 {
183 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
184 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
185
186 dra7xx_pcie_enable_interrupts(dra7xx);
187
188 return 0;
189 }
190
dra7xx_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)191 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
192 irq_hw_number_t hwirq)
193 {
194 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
195 irq_set_chip_data(irq, domain->host_data);
196
197 return 0;
198 }
199
200 static const struct irq_domain_ops intx_domain_ops = {
201 .map = dra7xx_pcie_intx_map,
202 .xlate = pci_irqd_intx_xlate,
203 };
204
dra7xx_pcie_handle_msi(struct dw_pcie_rp * pp,int index)205 static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index)
206 {
207 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
208 unsigned long val;
209 int pos;
210
211 val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
212 (index * MSI_REG_CTRL_BLOCK_SIZE));
213 if (!val)
214 return 0;
215
216 pos = find_first_bit(&val, MAX_MSI_IRQS_PER_CTRL);
217 while (pos != MAX_MSI_IRQS_PER_CTRL) {
218 generic_handle_domain_irq(pp->irq_domain,
219 (index * MAX_MSI_IRQS_PER_CTRL) + pos);
220 pos++;
221 pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
222 }
223
224 return 1;
225 }
226
dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp * pp)227 static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp)
228 {
229 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
230 int ret, i, count, num_ctrls;
231
232 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
233
234 /**
235 * Need to make sure all MSI status bits read 0 before exiting.
236 * Else, new MSI IRQs are not registered by the wrapper. Have an
237 * upperbound for the loop and exit the IRQ in case of IRQ flood
238 * to avoid locking up system in interrupt context.
239 */
240 count = 0;
241 do {
242 ret = 0;
243
244 for (i = 0; i < num_ctrls; i++)
245 ret |= dra7xx_pcie_handle_msi(pp, i);
246 count++;
247 } while (ret && count <= 1000);
248
249 if (count > 1000)
250 dev_warn_ratelimited(pci->dev,
251 "Too many MSI IRQs to handle\n");
252 }
253
dra7xx_pcie_msi_irq_handler(struct irq_desc * desc)254 static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
255 {
256 struct irq_chip *chip = irq_desc_get_chip(desc);
257 struct dra7xx_pcie *dra7xx;
258 struct dw_pcie_rp *pp;
259 struct dw_pcie *pci;
260 unsigned long reg;
261 u32 bit;
262
263 chained_irq_enter(chip, desc);
264
265 pp = irq_desc_get_handler_data(desc);
266 pci = to_dw_pcie_from_pp(pp);
267 dra7xx = to_dra7xx_pcie(pci);
268
269 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
270 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
271
272 switch (reg) {
273 case MSI:
274 dra7xx_pcie_handle_msi_irq(pp);
275 break;
276 case INTA:
277 case INTB:
278 case INTC:
279 case INTD:
280 for_each_set_bit(bit, ®, PCI_NUM_INTX)
281 generic_handle_domain_irq(dra7xx->irq_domain, bit);
282 break;
283 }
284
285 chained_irq_exit(chip, desc);
286 }
287
dra7xx_pcie_irq_handler(int irq,void * arg)288 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
289 {
290 struct dra7xx_pcie *dra7xx = arg;
291 struct dw_pcie *pci = dra7xx->pci;
292 struct device *dev = pci->dev;
293 struct dw_pcie_ep *ep = &pci->ep;
294 u32 reg;
295
296 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
297
298 if (reg & ERR_SYS)
299 dev_dbg(dev, "System Error\n");
300
301 if (reg & ERR_FATAL)
302 dev_dbg(dev, "Fatal Error\n");
303
304 if (reg & ERR_NONFATAL)
305 dev_dbg(dev, "Non Fatal Error\n");
306
307 if (reg & ERR_COR)
308 dev_dbg(dev, "Correctable Error\n");
309
310 if (reg & ERR_AXI)
311 dev_dbg(dev, "AXI tag lookup fatal Error\n");
312
313 if (reg & ERR_ECRC)
314 dev_dbg(dev, "ECRC Error\n");
315
316 if (reg & PME_TURN_OFF)
317 dev_dbg(dev,
318 "Power Management Event Turn-Off message received\n");
319
320 if (reg & PME_TO_ACK)
321 dev_dbg(dev,
322 "Power Management Turn-Off Ack message received\n");
323
324 if (reg & PM_PME)
325 dev_dbg(dev, "PM Power Management Event message received\n");
326
327 if (reg & LINK_REQ_RST)
328 dev_dbg(dev, "Link Request Reset\n");
329
330 if (reg & LINK_UP_EVT) {
331 if (dra7xx->mode == DW_PCIE_EP_TYPE)
332 dw_pcie_ep_linkup(ep);
333 dev_dbg(dev, "Link-up state change\n");
334 }
335
336 if (reg & CFG_BME_EVT)
337 dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
338
339 if (reg & CFG_MSE_EVT)
340 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
341
342 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
343
344 return IRQ_HANDLED;
345 }
346
dra7xx_pcie_init_irq_domain(struct dw_pcie_rp * pp)347 static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp)
348 {
349 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
350 struct device *dev = pci->dev;
351 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
352 struct device_node *node = dev->of_node;
353 struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
354
355 if (!pcie_intc_node) {
356 dev_err(dev, "No PCIe Intc node found\n");
357 return -ENODEV;
358 }
359
360 irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler,
361 pp);
362 dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
363 &intx_domain_ops, pp);
364 of_node_put(pcie_intc_node);
365 if (!dra7xx->irq_domain) {
366 dev_err(dev, "Failed to get a INTx IRQ domain\n");
367 return -ENODEV;
368 }
369
370 return 0;
371 }
372
373 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
374 .init = dra7xx_pcie_host_init,
375 };
376
dra7xx_pcie_ep_init(struct dw_pcie_ep * ep)377 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
378 {
379 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
380 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
381 enum pci_barno bar;
382
383 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
384 dw_pcie_ep_reset_bar(pci, bar);
385
386 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
387 }
388
dra7xx_pcie_raise_intx_irq(struct dra7xx_pcie * dra7xx)389 static void dra7xx_pcie_raise_intx_irq(struct dra7xx_pcie *dra7xx)
390 {
391 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
392 mdelay(1);
393 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
394 }
395
dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie * dra7xx,u8 interrupt_num)396 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
397 u8 interrupt_num)
398 {
399 u32 reg;
400
401 reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
402 reg |= MSI_REQ_GRANT;
403 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
404 }
405
dra7xx_pcie_raise_irq(struct dw_pcie_ep * ep,u8 func_no,unsigned int type,u16 interrupt_num)406 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
407 unsigned int type, u16 interrupt_num)
408 {
409 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
410 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
411
412 switch (type) {
413 case PCI_IRQ_INTX:
414 dra7xx_pcie_raise_intx_irq(dra7xx);
415 break;
416 case PCI_IRQ_MSI:
417 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
418 break;
419 default:
420 dev_err(pci->dev, "UNKNOWN IRQ type\n");
421 }
422
423 return 0;
424 }
425
426 static const struct pci_epc_features dra7xx_pcie_epc_features = {
427 .linkup_notifier = true,
428 .msi_capable = true,
429 .msix_capable = false,
430 };
431
432 static const struct pci_epc_features*
dra7xx_pcie_get_features(struct dw_pcie_ep * ep)433 dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
434 {
435 return &dra7xx_pcie_epc_features;
436 }
437
438 static const struct dw_pcie_ep_ops pcie_ep_ops = {
439 .init = dra7xx_pcie_ep_init,
440 .raise_irq = dra7xx_pcie_raise_irq,
441 .get_features = dra7xx_pcie_get_features,
442 };
443
dra7xx_add_pcie_ep(struct dra7xx_pcie * dra7xx,struct platform_device * pdev)444 static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
445 struct platform_device *pdev)
446 {
447 int ret;
448 struct dw_pcie_ep *ep;
449 struct device *dev = &pdev->dev;
450 struct dw_pcie *pci = dra7xx->pci;
451
452 ep = &pci->ep;
453 ep->ops = &pcie_ep_ops;
454
455 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");
456 if (IS_ERR(pci->dbi_base))
457 return PTR_ERR(pci->dbi_base);
458
459 pci->dbi_base2 =
460 devm_platform_ioremap_resource_byname(pdev, "ep_dbics2");
461 if (IS_ERR(pci->dbi_base2))
462 return PTR_ERR(pci->dbi_base2);
463
464 ret = dw_pcie_ep_init(ep);
465 if (ret) {
466 dev_err(dev, "failed to initialize endpoint\n");
467 return ret;
468 }
469
470 ret = dw_pcie_ep_init_registers(ep);
471 if (ret) {
472 dev_err(dev, "Failed to initialize DWC endpoint registers\n");
473 dw_pcie_ep_deinit(ep);
474 return ret;
475 }
476
477 pci_epc_init_notify(ep->epc);
478
479 return 0;
480 }
481
dra7xx_add_pcie_port(struct dra7xx_pcie * dra7xx,struct platform_device * pdev)482 static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
483 struct platform_device *pdev)
484 {
485 int ret;
486 struct dw_pcie *pci = dra7xx->pci;
487 struct dw_pcie_rp *pp = &pci->pp;
488 struct device *dev = pci->dev;
489
490 pp->irq = platform_get_irq(pdev, 1);
491 if (pp->irq < 0)
492 return pp->irq;
493
494 /* MSI IRQ is muxed */
495 pp->msi_irq[0] = -ENODEV;
496
497 ret = dra7xx_pcie_init_irq_domain(pp);
498 if (ret < 0)
499 return ret;
500
501 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");
502 if (IS_ERR(pci->dbi_base))
503 return PTR_ERR(pci->dbi_base);
504
505 pp->ops = &dra7xx_pcie_host_ops;
506
507 ret = dw_pcie_host_init(pp);
508 if (ret) {
509 dev_err(dev, "failed to initialize host\n");
510 return ret;
511 }
512
513 return 0;
514 }
515
516 static const struct dw_pcie_ops dw_pcie_ops = {
517 .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
518 .start_link = dra7xx_pcie_establish_link,
519 .stop_link = dra7xx_pcie_stop_link,
520 .link_up = dra7xx_pcie_link_up,
521 };
522
dra7xx_pcie_disable_phy(struct dra7xx_pcie * dra7xx)523 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
524 {
525 int phy_count = dra7xx->phy_count;
526
527 while (phy_count--) {
528 phy_power_off(dra7xx->phy[phy_count]);
529 phy_exit(dra7xx->phy[phy_count]);
530 }
531 }
532
dra7xx_pcie_enable_phy(struct dra7xx_pcie * dra7xx)533 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
534 {
535 int phy_count = dra7xx->phy_count;
536 int ret;
537 int i;
538
539 for (i = 0; i < phy_count; i++) {
540 ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
541 if (ret < 0)
542 goto err_phy;
543
544 ret = phy_init(dra7xx->phy[i]);
545 if (ret < 0)
546 goto err_phy;
547
548 ret = phy_power_on(dra7xx->phy[i]);
549 if (ret < 0) {
550 phy_exit(dra7xx->phy[i]);
551 goto err_phy;
552 }
553 }
554
555 return 0;
556
557 err_phy:
558 while (--i >= 0) {
559 phy_power_off(dra7xx->phy[i]);
560 phy_exit(dra7xx->phy[i]);
561 }
562
563 return ret;
564 }
565
566 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
567 .mode = DW_PCIE_RC_TYPE,
568 };
569
570 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
571 .mode = DW_PCIE_EP_TYPE,
572 };
573
574 static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
575 .b1co_mode_sel_mask = BIT(2),
576 .mode = DW_PCIE_RC_TYPE,
577 };
578
579 static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
580 .b1co_mode_sel_mask = GENMASK(3, 2),
581 .mode = DW_PCIE_RC_TYPE,
582 };
583
584 static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
585 .b1co_mode_sel_mask = BIT(2),
586 .mode = DW_PCIE_EP_TYPE,
587 };
588
589 static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
590 .b1co_mode_sel_mask = GENMASK(3, 2),
591 .mode = DW_PCIE_EP_TYPE,
592 };
593
594 static const struct of_device_id of_dra7xx_pcie_match[] = {
595 {
596 .compatible = "ti,dra7-pcie",
597 .data = &dra7xx_pcie_rc_of_data,
598 },
599 {
600 .compatible = "ti,dra7-pcie-ep",
601 .data = &dra7xx_pcie_ep_of_data,
602 },
603 {
604 .compatible = "ti,dra746-pcie-rc",
605 .data = &dra746_pcie_rc_of_data,
606 },
607 {
608 .compatible = "ti,dra726-pcie-rc",
609 .data = &dra726_pcie_rc_of_data,
610 },
611 {
612 .compatible = "ti,dra746-pcie-ep",
613 .data = &dra746_pcie_ep_of_data,
614 },
615 {
616 .compatible = "ti,dra726-pcie-ep",
617 .data = &dra726_pcie_ep_of_data,
618 },
619 {},
620 };
621 MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match);
622
623 /*
624 * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
625 * @dra7xx: the dra7xx device where the workaround should be applied
626 *
627 * Access to the PCIe slave port that are not 32-bit aligned will result
628 * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
629 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
630 * 0x3.
631 *
632 * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
633 */
dra7xx_pcie_unaligned_memaccess(struct device * dev)634 static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
635 {
636 int ret;
637 struct device_node *np = dev->of_node;
638 struct of_phandle_args args;
639 struct regmap *regmap;
640
641 regmap = syscon_regmap_lookup_by_phandle(np,
642 "ti,syscon-unaligned-access");
643 if (IS_ERR(regmap)) {
644 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
645 return -EINVAL;
646 }
647
648 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
649 2, 0, &args);
650 if (ret) {
651 dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
652 return ret;
653 }
654
655 ret = regmap_update_bits(regmap, args.args[0], args.args[1],
656 args.args[1]);
657 if (ret)
658 dev_err(dev, "failed to enable unaligned access\n");
659
660 of_node_put(args.np);
661
662 return ret;
663 }
664
dra7xx_pcie_configure_two_lane(struct device * dev,u32 b1co_mode_sel_mask)665 static int dra7xx_pcie_configure_two_lane(struct device *dev,
666 u32 b1co_mode_sel_mask)
667 {
668 struct device_node *np = dev->of_node;
669 struct regmap *pcie_syscon;
670 unsigned int pcie_reg;
671 u32 mask;
672 u32 val;
673
674 pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
675 if (IS_ERR(pcie_syscon)) {
676 dev_err(dev, "unable to get ti,syscon-lane-sel\n");
677 return -EINVAL;
678 }
679
680 if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
681 &pcie_reg)) {
682 dev_err(dev, "couldn't get lane selection reg offset\n");
683 return -EINVAL;
684 }
685
686 mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
687 val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
688 regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
689
690 return 0;
691 }
692
dra7xx_pcie_probe(struct platform_device * pdev)693 static int dra7xx_pcie_probe(struct platform_device *pdev)
694 {
695 u32 reg;
696 int ret;
697 int irq;
698 int i;
699 int phy_count;
700 struct phy **phy;
701 struct device_link **link;
702 void __iomem *base;
703 struct dw_pcie *pci;
704 struct dra7xx_pcie *dra7xx;
705 struct device *dev = &pdev->dev;
706 struct device_node *np = dev->of_node;
707 char name[10];
708 struct gpio_desc *reset;
709 const struct dra7xx_pcie_of_data *data;
710 enum dw_pcie_device_mode mode;
711 u32 b1co_mode_sel_mask;
712
713 data = of_device_get_match_data(dev);
714 if (!data)
715 return -EINVAL;
716
717 mode = (enum dw_pcie_device_mode)data->mode;
718 b1co_mode_sel_mask = data->b1co_mode_sel_mask;
719
720 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
721 if (!dra7xx)
722 return -ENOMEM;
723
724 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
725 if (!pci)
726 return -ENOMEM;
727
728 pci->dev = dev;
729 pci->ops = &dw_pcie_ops;
730
731 irq = platform_get_irq(pdev, 0);
732 if (irq < 0)
733 return irq;
734
735 base = devm_platform_ioremap_resource_byname(pdev, "ti_conf");
736 if (IS_ERR(base))
737 return PTR_ERR(base);
738
739 phy_count = of_property_count_strings(np, "phy-names");
740 if (phy_count < 0) {
741 dev_err(dev, "unable to find the strings\n");
742 return phy_count;
743 }
744
745 phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);
746 if (!phy)
747 return -ENOMEM;
748
749 link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
750 if (!link)
751 return -ENOMEM;
752
753 dra7xx->clk = devm_clk_get_optional(dev, NULL);
754 if (IS_ERR(dra7xx->clk))
755 return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
756 "clock request failed");
757
758 ret = clk_prepare_enable(dra7xx->clk);
759 if (ret)
760 return ret;
761
762 for (i = 0; i < phy_count; i++) {
763 snprintf(name, sizeof(name), "pcie-phy%d", i);
764 phy[i] = devm_phy_get(dev, name);
765 if (IS_ERR(phy[i]))
766 return PTR_ERR(phy[i]);
767
768 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
769 if (!link[i]) {
770 ret = -EINVAL;
771 goto err_link;
772 }
773 }
774
775 dra7xx->base = base;
776 dra7xx->phy = phy;
777 dra7xx->pci = pci;
778 dra7xx->phy_count = phy_count;
779
780 if (phy_count == 2) {
781 ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
782 if (ret < 0)
783 dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
784 }
785
786 ret = dra7xx_pcie_enable_phy(dra7xx);
787 if (ret) {
788 dev_err(dev, "failed to enable phy\n");
789 return ret;
790 }
791
792 platform_set_drvdata(pdev, dra7xx);
793
794 pm_runtime_enable(dev);
795 ret = pm_runtime_get_sync(dev);
796 if (ret < 0) {
797 dev_err(dev, "pm_runtime_get_sync failed\n");
798 goto err_get_sync;
799 }
800
801 reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
802 if (IS_ERR(reset)) {
803 ret = PTR_ERR(reset);
804 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
805 goto err_gpio;
806 }
807
808 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
809 reg &= ~LTSSM_EN;
810 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
811
812 switch (mode) {
813 case DW_PCIE_RC_TYPE:
814 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
815 ret = -ENODEV;
816 goto err_gpio;
817 }
818
819 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
820 DEVICE_TYPE_RC);
821
822 ret = dra7xx_pcie_unaligned_memaccess(dev);
823 if (ret)
824 dev_err(dev, "WA for Errata i870 not applied\n");
825
826 ret = dra7xx_add_pcie_port(dra7xx, pdev);
827 if (ret < 0)
828 goto err_gpio;
829 break;
830 case DW_PCIE_EP_TYPE:
831 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
832 ret = -ENODEV;
833 goto err_gpio;
834 }
835
836 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
837 DEVICE_TYPE_EP);
838
839 ret = dra7xx_pcie_unaligned_memaccess(dev);
840 if (ret)
841 goto err_gpio;
842
843 ret = dra7xx_add_pcie_ep(dra7xx, pdev);
844 if (ret < 0)
845 goto err_gpio;
846 break;
847 default:
848 dev_err(dev, "INVALID device type %d\n", mode);
849 }
850 dra7xx->mode = mode;
851
852 ret = devm_request_threaded_irq(dev, irq, NULL, dra7xx_pcie_irq_handler,
853 IRQF_SHARED | IRQF_ONESHOT,
854 "dra7xx-pcie-main", dra7xx);
855 if (ret) {
856 dev_err(dev, "failed to request irq\n");
857 goto err_deinit;
858 }
859
860 return 0;
861
862 err_deinit:
863 if (dra7xx->mode == DW_PCIE_RC_TYPE)
864 dw_pcie_host_deinit(&dra7xx->pci->pp);
865 else
866 dw_pcie_ep_deinit(&dra7xx->pci->ep);
867
868 err_gpio:
869 err_get_sync:
870 pm_runtime_put(dev);
871 pm_runtime_disable(dev);
872 dra7xx_pcie_disable_phy(dra7xx);
873
874 err_link:
875 while (--i >= 0)
876 device_link_del(link[i]);
877
878 return ret;
879 }
880
dra7xx_pcie_suspend(struct device * dev)881 static int dra7xx_pcie_suspend(struct device *dev)
882 {
883 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
884 struct dw_pcie *pci = dra7xx->pci;
885 u32 val;
886
887 if (dra7xx->mode != DW_PCIE_RC_TYPE)
888 return 0;
889
890 /* clear MSE */
891 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
892 val &= ~PCI_COMMAND_MEMORY;
893 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
894
895 return 0;
896 }
897
dra7xx_pcie_resume(struct device * dev)898 static int dra7xx_pcie_resume(struct device *dev)
899 {
900 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
901 struct dw_pcie *pci = dra7xx->pci;
902 u32 val;
903
904 if (dra7xx->mode != DW_PCIE_RC_TYPE)
905 return 0;
906
907 /* set MSE */
908 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
909 val |= PCI_COMMAND_MEMORY;
910 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
911
912 return 0;
913 }
914
dra7xx_pcie_suspend_noirq(struct device * dev)915 static int dra7xx_pcie_suspend_noirq(struct device *dev)
916 {
917 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
918
919 dra7xx_pcie_disable_phy(dra7xx);
920
921 return 0;
922 }
923
dra7xx_pcie_resume_noirq(struct device * dev)924 static int dra7xx_pcie_resume_noirq(struct device *dev)
925 {
926 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
927 int ret;
928
929 ret = dra7xx_pcie_enable_phy(dra7xx);
930 if (ret) {
931 dev_err(dev, "failed to enable phy\n");
932 return ret;
933 }
934
935 return 0;
936 }
937
dra7xx_pcie_shutdown(struct platform_device * pdev)938 static void dra7xx_pcie_shutdown(struct platform_device *pdev)
939 {
940 struct device *dev = &pdev->dev;
941 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
942 int ret;
943
944 dra7xx_pcie_stop_link(dra7xx->pci);
945
946 ret = pm_runtime_put_sync(dev);
947 if (ret < 0)
948 dev_dbg(dev, "pm_runtime_put_sync failed\n");
949
950 pm_runtime_disable(dev);
951 dra7xx_pcie_disable_phy(dra7xx);
952
953 clk_disable_unprepare(dra7xx->clk);
954 }
955
956 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
957 SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
958 NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
959 dra7xx_pcie_resume_noirq)
960 };
961
962 static struct platform_driver dra7xx_pcie_driver = {
963 .probe = dra7xx_pcie_probe,
964 .driver = {
965 .name = "dra7-pcie",
966 .of_match_table = of_dra7xx_pcie_match,
967 .suppress_bind_attrs = true,
968 .pm = &dra7xx_pcie_pm_ops,
969 },
970 .shutdown = dra7xx_pcie_shutdown,
971 };
972 module_platform_driver(dra7xx_pcie_driver);
973
974 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
975 MODULE_DESCRIPTION("PCIe controller driver for TI DRA7xx SoCs");
976 MODULE_LICENSE("GPL v2");
977