1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * A V4L2 driver for Galaxycore GC2145 camera.
4 * Copyright (C) 2023, STMicroelectronics SA
5 *
6 * Inspired by the imx219.c driver
7 *
8 * Datasheet v1.0 available at http://files.pine64.org/doc/datasheet/PinebookPro/GC2145%20CSP%20DataSheet%20release%20V1.0_20131201.pdf
9 */
10
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/units.h>
19
20 #include <media/mipi-csi2.h>
21 #include <media/v4l2-cci.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-event.h>
25 #include <media/v4l2-fwnode.h>
26 #include <media/v4l2-mediabus.h>
27
28 /* Chip ID */
29 #define GC2145_CHIP_ID 0x2145
30
31 /* Page 0 */
32 #define GC2145_REG_EXPOSURE CCI_REG16(0x03)
33 #define GC2145_REG_HBLANK CCI_REG16(0x05)
34 #define GC2145_REG_VBLANK CCI_REG16(0x07)
35 #define GC2145_REG_ROW_START CCI_REG16(0x09)
36 #define GC2145_REG_COL_START CCI_REG16(0x0b)
37 #define GC2145_REG_WIN_HEIGHT CCI_REG16(0x0d)
38 #define GC2145_REG_WIN_WIDTH CCI_REG16(0x0f)
39 #define GC2145_REG_ANALOG_MODE1 CCI_REG8(0x17)
40 #define GC2145_REG_OUTPUT_FMT CCI_REG8(0x84)
41 #define GC2145_REG_SYNC_MODE CCI_REG8(0x86)
42 #define GC2145_SYNC_MODE_COL_SWITCH BIT(4)
43 #define GC2145_SYNC_MODE_ROW_SWITCH BIT(5)
44 #define GC2145_REG_BYPASS_MODE CCI_REG8(0x89)
45 #define GC2145_BYPASS_MODE_SWITCH BIT(5)
46 #define GC2145_REG_DEBUG_MODE2 CCI_REG8(0x8c)
47 #define GC2145_REG_DEBUG_MODE3 CCI_REG8(0x8d)
48 #define GC2145_REG_CROP_ENABLE CCI_REG8(0x90)
49 #define GC2145_REG_CROP_Y CCI_REG16(0x91)
50 #define GC2145_REG_CROP_X CCI_REG16(0x93)
51 #define GC2145_REG_CROP_HEIGHT CCI_REG16(0x95)
52 #define GC2145_REG_CROP_WIDTH CCI_REG16(0x97)
53 #define GC2145_REG_GLOBAL_GAIN CCI_REG8(0xb0)
54 #define GC2145_REG_CHIP_ID CCI_REG16(0xf0)
55 #define GC2145_REG_PAD_IO CCI_REG8(0xf2)
56 #define GC2145_REG_PAGE_SELECT CCI_REG8(0xfe)
57 /* Page 3 */
58 #define GC2145_REG_DPHY_ANALOG_MODE1 CCI_REG8(0x01)
59 #define GC2145_DPHY_MODE_PHY_CLK_EN BIT(0)
60 #define GC2145_DPHY_MODE_PHY_LANE0_EN BIT(1)
61 #define GC2145_DPHY_MODE_PHY_LANE1_EN BIT(2)
62 #define GC2145_DPHY_MODE_PHY_CLK_LANE_P2S_SEL BIT(7)
63 #define GC2145_REG_DPHY_ANALOG_MODE2 CCI_REG8(0x02)
64 #define GC2145_DPHY_CLK_DIFF(a) ((a) & 0x07)
65 #define GC2145_DPHY_LANE0_DIFF(a) (((a) & 0x07) << 4)
66 #define GC2145_REG_DPHY_ANALOG_MODE3 CCI_REG8(0x03)
67 #define GC2145_DPHY_LANE1_DIFF(a) ((a) & 0x07)
68 #define GC2145_DPHY_CLK_DELAY BIT(4)
69 #define GC2145_DPHY_LANE0_DELAY BIT(5)
70 #define GC2145_DPHY_LANE1_DELAY BIT(6)
71 #define GC2145_REG_FIFO_FULL_LVL CCI_REG16_LE(0x04)
72 #define GC2145_REG_FIFO_MODE CCI_REG8(0x06)
73 #define GC2145_FIFO_MODE_READ_GATE BIT(3)
74 #define GC2145_FIFO_MODE_MIPI_CLK_MODULE BIT(7)
75 #define GC2145_REG_BUF_CSI2_MODE CCI_REG8(0x10)
76 #define GC2145_CSI2_MODE_DOUBLE BIT(0)
77 #define GC2145_CSI2_MODE_RAW8 BIT(2)
78 #define GC2145_CSI2_MODE_MIPI_EN BIT(4)
79 #define GC2145_CSI2_MODE_EN BIT(7)
80 #define GC2145_REG_MIPI_DT CCI_REG8(0x11)
81 #define GC2145_REG_LWC CCI_REG16_LE(0x12)
82 #define GC2145_REG_DPHY_MODE CCI_REG8(0x15)
83 #define GC2145_DPHY_MODE_TRIGGER_PROG BIT(4)
84 #define GC2145_REG_FIFO_GATE_MODE CCI_REG8(0x17)
85 #define GC2145_REG_T_LPX CCI_REG8(0x21)
86 #define GC2145_REG_T_CLK_HS_PREPARE CCI_REG8(0x22)
87 #define GC2145_REG_T_CLK_ZERO CCI_REG8(0x23)
88 #define GC2145_REG_T_CLK_PRE CCI_REG8(0x24)
89 #define GC2145_REG_T_CLK_POST CCI_REG8(0x25)
90 #define GC2145_REG_T_CLK_TRAIL CCI_REG8(0x26)
91 #define GC2145_REG_T_HS_EXIT CCI_REG8(0x27)
92 #define GC2145_REG_T_WAKEUP CCI_REG8(0x28)
93 #define GC2145_REG_T_HS_PREPARE CCI_REG8(0x29)
94 #define GC2145_REG_T_HS_ZERO CCI_REG8(0x2a)
95 #define GC2145_REG_T_HS_TRAIL CCI_REG8(0x2b)
96
97 /* External clock frequency is 24.0MHz */
98 #define GC2145_XCLK_FREQ (24 * HZ_PER_MHZ)
99
100 #define GC2145_NATIVE_WIDTH 1616U
101 #define GC2145_NATIVE_HEIGHT 1232U
102
103 /**
104 * struct gc2145_mode - GC2145 mode description
105 * @width: frame width (in pixels)
106 * @height: frame height (in pixels)
107 * @reg_seq: registers config sequence to enter into the mode
108 * @reg_seq_size: size of the sequence
109 * @pixel_rate: pixel rate associated with the mode
110 * @crop: window area captured
111 * @hblank: default horizontal blanking
112 * @vblank: default vertical blanking
113 * @link_freq_index: index within the link frequency menu
114 */
115 struct gc2145_mode {
116 unsigned int width;
117 unsigned int height;
118 const struct cci_reg_sequence *reg_seq;
119 size_t reg_seq_size;
120 unsigned long pixel_rate;
121 struct v4l2_rect crop;
122 unsigned int hblank;
123 unsigned int vblank;
124 unsigned int link_freq_index;
125 };
126
127 #define GC2145_DEFAULT_EXPOSURE 0x04e2
128 #define GC2145_DEFAULT_GLOBAL_GAIN 0x55
129 static const struct cci_reg_sequence gc2145_common_regs[] = {
130 {GC2145_REG_PAGE_SELECT, 0x00},
131 /* SH Delay */
132 {CCI_REG8(0x12), 0x2e},
133 /* Flip */
134 {GC2145_REG_ANALOG_MODE1, 0x14},
135 /* Analog Conf */
136 {CCI_REG8(0x18), 0x22}, {CCI_REG8(0x19), 0x0e}, {CCI_REG8(0x1a), 0x01},
137 {CCI_REG8(0x1b), 0x4b}, {CCI_REG8(0x1c), 0x07}, {CCI_REG8(0x1d), 0x10},
138 {CCI_REG8(0x1e), 0x88}, {CCI_REG8(0x1f), 0x78}, {CCI_REG8(0x20), 0x03},
139 {CCI_REG8(0x21), 0x40}, {CCI_REG8(0x22), 0xa0}, {CCI_REG8(0x24), 0x16},
140 {CCI_REG8(0x25), 0x01}, {CCI_REG8(0x26), 0x10}, {CCI_REG8(0x2d), 0x60},
141 {CCI_REG8(0x30), 0x01}, {CCI_REG8(0x31), 0x90}, {CCI_REG8(0x33), 0x06},
142 {CCI_REG8(0x34), 0x01},
143 /* ISP related */
144 {CCI_REG8(0x80), 0x7f}, {CCI_REG8(0x81), 0x26}, {CCI_REG8(0x82), 0xfa},
145 {CCI_REG8(0x83), 0x00}, {CCI_REG8(0x84), 0x02}, {CCI_REG8(0x86), 0x02},
146 {CCI_REG8(0x88), 0x03},
147 {GC2145_REG_BYPASS_MODE, 0x03},
148 {CCI_REG8(0x85), 0x08}, {CCI_REG8(0x8a), 0x00}, {CCI_REG8(0x8b), 0x00},
149 {GC2145_REG_GLOBAL_GAIN, GC2145_DEFAULT_GLOBAL_GAIN},
150 {CCI_REG8(0xc3), 0x00}, {CCI_REG8(0xc4), 0x80}, {CCI_REG8(0xc5), 0x90},
151 {CCI_REG8(0xc6), 0x3b}, {CCI_REG8(0xc7), 0x46},
152 /* BLK */
153 {GC2145_REG_PAGE_SELECT, 0x00},
154 {CCI_REG8(0x40), 0x42}, {CCI_REG8(0x41), 0x00}, {CCI_REG8(0x43), 0x5b},
155 {CCI_REG8(0x5e), 0x00}, {CCI_REG8(0x5f), 0x00}, {CCI_REG8(0x60), 0x00},
156 {CCI_REG8(0x61), 0x00}, {CCI_REG8(0x62), 0x00}, {CCI_REG8(0x63), 0x00},
157 {CCI_REG8(0x64), 0x00}, {CCI_REG8(0x65), 0x00}, {CCI_REG8(0x66), 0x20},
158 {CCI_REG8(0x67), 0x20}, {CCI_REG8(0x68), 0x20}, {CCI_REG8(0x69), 0x20},
159 {CCI_REG8(0x76), 0x00}, {CCI_REG8(0x6a), 0x08}, {CCI_REG8(0x6b), 0x08},
160 {CCI_REG8(0x6c), 0x08}, {CCI_REG8(0x6d), 0x08}, {CCI_REG8(0x6e), 0x08},
161 {CCI_REG8(0x6f), 0x08}, {CCI_REG8(0x70), 0x08}, {CCI_REG8(0x71), 0x08},
162 {CCI_REG8(0x76), 0x00}, {CCI_REG8(0x72), 0xf0}, {CCI_REG8(0x7e), 0x3c},
163 {CCI_REG8(0x7f), 0x00},
164 {GC2145_REG_PAGE_SELECT, 0x02},
165 {CCI_REG8(0x48), 0x15}, {CCI_REG8(0x49), 0x00}, {CCI_REG8(0x4b), 0x0b},
166 /* AEC */
167 {GC2145_REG_PAGE_SELECT, 0x00},
168 {GC2145_REG_EXPOSURE, GC2145_DEFAULT_EXPOSURE},
169 {GC2145_REG_PAGE_SELECT, 0x01},
170 {CCI_REG8(0x01), 0x04}, {CCI_REG8(0x02), 0xc0}, {CCI_REG8(0x03), 0x04},
171 {CCI_REG8(0x04), 0x90}, {CCI_REG8(0x05), 0x30}, {CCI_REG8(0x06), 0x90},
172 {CCI_REG8(0x07), 0x30}, {CCI_REG8(0x08), 0x80}, {CCI_REG8(0x09), 0x00},
173 {CCI_REG8(0x0a), 0x82}, {CCI_REG8(0x0b), 0x11}, {CCI_REG8(0x0c), 0x10},
174 {CCI_REG8(0x11), 0x10}, {CCI_REG8(0x13), 0x7b}, {CCI_REG8(0x17), 0x00},
175 {CCI_REG8(0x1c), 0x11}, {CCI_REG8(0x1e), 0x61}, {CCI_REG8(0x1f), 0x35},
176 {CCI_REG8(0x20), 0x40}, {CCI_REG8(0x22), 0x40}, {CCI_REG8(0x23), 0x20},
177 {GC2145_REG_PAGE_SELECT, 0x02},
178 {CCI_REG8(0x0f), 0x04},
179 {GC2145_REG_PAGE_SELECT, 0x01},
180 {CCI_REG8(0x12), 0x35}, {CCI_REG8(0x15), 0xb0}, {CCI_REG8(0x10), 0x31},
181 {CCI_REG8(0x3e), 0x28}, {CCI_REG8(0x3f), 0xb0}, {CCI_REG8(0x40), 0x90},
182 {CCI_REG8(0x41), 0x0f},
183 /* INTPEE */
184 {GC2145_REG_PAGE_SELECT, 0x02},
185 {CCI_REG8(0x90), 0x6c}, {CCI_REG8(0x91), 0x03}, {CCI_REG8(0x92), 0xcb},
186 {CCI_REG8(0x94), 0x33}, {CCI_REG8(0x95), 0x84}, {CCI_REG8(0x97), 0x65},
187 {CCI_REG8(0xa2), 0x11},
188 /* DNDD */
189 {GC2145_REG_PAGE_SELECT, 0x02},
190 {CCI_REG8(0x80), 0xc1}, {CCI_REG8(0x81), 0x08}, {CCI_REG8(0x82), 0x05},
191 {CCI_REG8(0x83), 0x08}, {CCI_REG8(0x84), 0x0a}, {CCI_REG8(0x86), 0xf0},
192 {CCI_REG8(0x87), 0x50}, {CCI_REG8(0x88), 0x15}, {CCI_REG8(0x89), 0xb0},
193 {CCI_REG8(0x8a), 0x30}, {CCI_REG8(0x8b), 0x10},
194 /* ASDE */
195 {GC2145_REG_PAGE_SELECT, 0x01},
196 {CCI_REG8(0x21), 0x04},
197 {GC2145_REG_PAGE_SELECT, 0x02},
198 {CCI_REG8(0xa3), 0x50}, {CCI_REG8(0xa4), 0x20}, {CCI_REG8(0xa5), 0x40},
199 {CCI_REG8(0xa6), 0x80}, {CCI_REG8(0xab), 0x40}, {CCI_REG8(0xae), 0x0c},
200 {CCI_REG8(0xb3), 0x46}, {CCI_REG8(0xb4), 0x64}, {CCI_REG8(0xb6), 0x38},
201 {CCI_REG8(0xb7), 0x01}, {CCI_REG8(0xb9), 0x2b}, {CCI_REG8(0x3c), 0x04},
202 {CCI_REG8(0x3d), 0x15}, {CCI_REG8(0x4b), 0x06}, {CCI_REG8(0x4c), 0x20},
203 /* Gamma */
204 {GC2145_REG_PAGE_SELECT, 0x02},
205 {CCI_REG8(0x10), 0x09}, {CCI_REG8(0x11), 0x0d}, {CCI_REG8(0x12), 0x13},
206 {CCI_REG8(0x13), 0x19}, {CCI_REG8(0x14), 0x27}, {CCI_REG8(0x15), 0x37},
207 {CCI_REG8(0x16), 0x45}, {CCI_REG8(0x17), 0x53}, {CCI_REG8(0x18), 0x69},
208 {CCI_REG8(0x19), 0x7d}, {CCI_REG8(0x1a), 0x8f}, {CCI_REG8(0x1b), 0x9d},
209 {CCI_REG8(0x1c), 0xa9}, {CCI_REG8(0x1d), 0xbd}, {CCI_REG8(0x1e), 0xcd},
210 {CCI_REG8(0x1f), 0xd9}, {CCI_REG8(0x20), 0xe3}, {CCI_REG8(0x21), 0xea},
211 {CCI_REG8(0x22), 0xef}, {CCI_REG8(0x23), 0xf5}, {CCI_REG8(0x24), 0xf9},
212 {CCI_REG8(0x25), 0xff},
213 {GC2145_REG_PAGE_SELECT, 0x00},
214 {CCI_REG8(0xc6), 0x20}, {CCI_REG8(0xc7), 0x2b},
215 /* Gamma 2 */
216 {GC2145_REG_PAGE_SELECT, 0x02},
217 {CCI_REG8(0x26), 0x0f}, {CCI_REG8(0x27), 0x14}, {CCI_REG8(0x28), 0x19},
218 {CCI_REG8(0x29), 0x1e}, {CCI_REG8(0x2a), 0x27}, {CCI_REG8(0x2b), 0x33},
219 {CCI_REG8(0x2c), 0x3b}, {CCI_REG8(0x2d), 0x45}, {CCI_REG8(0x2e), 0x59},
220 {CCI_REG8(0x2f), 0x69}, {CCI_REG8(0x30), 0x7c}, {CCI_REG8(0x31), 0x89},
221 {CCI_REG8(0x32), 0x98}, {CCI_REG8(0x33), 0xae}, {CCI_REG8(0x34), 0xc0},
222 {CCI_REG8(0x35), 0xcf}, {CCI_REG8(0x36), 0xda}, {CCI_REG8(0x37), 0xe2},
223 {CCI_REG8(0x38), 0xe9}, {CCI_REG8(0x39), 0xf3}, {CCI_REG8(0x3a), 0xf9},
224 {CCI_REG8(0x3b), 0xff},
225 /* YCP */
226 {GC2145_REG_PAGE_SELECT, 0x02},
227 {CCI_REG8(0xd1), 0x32}, {CCI_REG8(0xd2), 0x32}, {CCI_REG8(0xd3), 0x40},
228 {CCI_REG8(0xd6), 0xf0}, {CCI_REG8(0xd7), 0x10}, {CCI_REG8(0xd8), 0xda},
229 {CCI_REG8(0xdd), 0x14}, {CCI_REG8(0xde), 0x86}, {CCI_REG8(0xed), 0x80},
230 {CCI_REG8(0xee), 0x00}, {CCI_REG8(0xef), 0x3f}, {CCI_REG8(0xd8), 0xd8},
231 /* ABS */
232 {GC2145_REG_PAGE_SELECT, 0x01},
233 {CCI_REG8(0x9f), 0x40},
234 /* LSC */
235 {GC2145_REG_PAGE_SELECT, 0x01},
236 {CCI_REG8(0xc2), 0x14}, {CCI_REG8(0xc3), 0x0d}, {CCI_REG8(0xc4), 0x0c},
237 {CCI_REG8(0xc8), 0x15}, {CCI_REG8(0xc9), 0x0d}, {CCI_REG8(0xca), 0x0a},
238 {CCI_REG8(0xbc), 0x24}, {CCI_REG8(0xbd), 0x10}, {CCI_REG8(0xbe), 0x0b},
239 {CCI_REG8(0xb6), 0x25}, {CCI_REG8(0xb7), 0x16}, {CCI_REG8(0xb8), 0x15},
240 {CCI_REG8(0xc5), 0x00}, {CCI_REG8(0xc6), 0x00}, {CCI_REG8(0xc7), 0x00},
241 {CCI_REG8(0xcb), 0x00}, {CCI_REG8(0xcc), 0x00}, {CCI_REG8(0xcd), 0x00},
242 {CCI_REG8(0xbf), 0x07}, {CCI_REG8(0xc0), 0x00}, {CCI_REG8(0xc1), 0x00},
243 {CCI_REG8(0xb9), 0x00}, {CCI_REG8(0xba), 0x00}, {CCI_REG8(0xbb), 0x00},
244 {CCI_REG8(0xaa), 0x01}, {CCI_REG8(0xab), 0x01}, {CCI_REG8(0xac), 0x00},
245 {CCI_REG8(0xad), 0x05}, {CCI_REG8(0xae), 0x06}, {CCI_REG8(0xaf), 0x0e},
246 {CCI_REG8(0xb0), 0x0b}, {CCI_REG8(0xb1), 0x07}, {CCI_REG8(0xb2), 0x06},
247 {CCI_REG8(0xb3), 0x17}, {CCI_REG8(0xb4), 0x0e}, {CCI_REG8(0xb5), 0x0e},
248 {CCI_REG8(0xd0), 0x09}, {CCI_REG8(0xd1), 0x00}, {CCI_REG8(0xd2), 0x00},
249 {CCI_REG8(0xd6), 0x08}, {CCI_REG8(0xd7), 0x00}, {CCI_REG8(0xd8), 0x00},
250 {CCI_REG8(0xd9), 0x00}, {CCI_REG8(0xda), 0x00}, {CCI_REG8(0xdb), 0x00},
251 {CCI_REG8(0xd3), 0x0a}, {CCI_REG8(0xd4), 0x00}, {CCI_REG8(0xd5), 0x00},
252 {CCI_REG8(0xa4), 0x00}, {CCI_REG8(0xa5), 0x00}, {CCI_REG8(0xa6), 0x77},
253 {CCI_REG8(0xa7), 0x77}, {CCI_REG8(0xa8), 0x77}, {CCI_REG8(0xa9), 0x77},
254 {CCI_REG8(0xa1), 0x80}, {CCI_REG8(0xa2), 0x80},
255 {GC2145_REG_PAGE_SELECT, 0x01},
256 {CCI_REG8(0xdf), 0x0d}, {CCI_REG8(0xdc), 0x25}, {CCI_REG8(0xdd), 0x30},
257 {CCI_REG8(0xe0), 0x77}, {CCI_REG8(0xe1), 0x80}, {CCI_REG8(0xe2), 0x77},
258 {CCI_REG8(0xe3), 0x90}, {CCI_REG8(0xe6), 0x90}, {CCI_REG8(0xe7), 0xa0},
259 {CCI_REG8(0xe8), 0x90}, {CCI_REG8(0xe9), 0xa0},
260 /* AWB */
261 /* measure window */
262 {GC2145_REG_PAGE_SELECT, 0x00},
263 {CCI_REG8(0xec), 0x06}, {CCI_REG8(0xed), 0x04}, {CCI_REG8(0xee), 0x60},
264 {CCI_REG8(0xef), 0x90}, {CCI_REG8(0xb6), 0x01},
265 {GC2145_REG_PAGE_SELECT, 0x01},
266 {CCI_REG8(0x4f), 0x00}, {CCI_REG8(0x4f), 0x00}, {CCI_REG8(0x4b), 0x01},
267 {CCI_REG8(0x4f), 0x00},
268 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x71}, {CCI_REG8(0x4e), 0x01},
269 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x91}, {CCI_REG8(0x4e), 0x01},
270 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x70}, {CCI_REG8(0x4e), 0x01},
271 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x90}, {CCI_REG8(0x4e), 0x02},
272 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xb0}, {CCI_REG8(0x4e), 0x02},
273 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8f}, {CCI_REG8(0x4e), 0x02},
274 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6f}, {CCI_REG8(0x4e), 0x02},
275 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xaf}, {CCI_REG8(0x4e), 0x02},
276 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xd0}, {CCI_REG8(0x4e), 0x02},
277 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xf0}, {CCI_REG8(0x4e), 0x02},
278 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcf}, {CCI_REG8(0x4e), 0x02},
279 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xef}, {CCI_REG8(0x4e), 0x02},
280 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6e}, {CCI_REG8(0x4e), 0x03},
281 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8e}, {CCI_REG8(0x4e), 0x03},
282 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xae}, {CCI_REG8(0x4e), 0x03},
283 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xce}, {CCI_REG8(0x4e), 0x03},
284 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4d}, {CCI_REG8(0x4e), 0x03},
285 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6d}, {CCI_REG8(0x4e), 0x03},
286 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8d}, {CCI_REG8(0x4e), 0x03},
287 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xad}, {CCI_REG8(0x4e), 0x03},
288 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcd}, {CCI_REG8(0x4e), 0x03},
289 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4c}, {CCI_REG8(0x4e), 0x03},
290 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6c}, {CCI_REG8(0x4e), 0x03},
291 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8c}, {CCI_REG8(0x4e), 0x03},
292 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xac}, {CCI_REG8(0x4e), 0x03},
293 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcc}, {CCI_REG8(0x4e), 0x03},
294 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcb}, {CCI_REG8(0x4e), 0x03},
295 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4b}, {CCI_REG8(0x4e), 0x03},
296 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6b}, {CCI_REG8(0x4e), 0x03},
297 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8b}, {CCI_REG8(0x4e), 0x03},
298 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xab}, {CCI_REG8(0x4e), 0x03},
299 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x04},
300 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xaa}, {CCI_REG8(0x4e), 0x04},
301 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x04},
302 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x04},
303 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xc9}, {CCI_REG8(0x4e), 0x04},
304 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x04},
305 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x89}, {CCI_REG8(0x4e), 0x04},
306 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xa9}, {CCI_REG8(0x4e), 0x04},
307 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x0b}, {CCI_REG8(0x4e), 0x05},
308 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x0a}, {CCI_REG8(0x4e), 0x05},
309 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xeb}, {CCI_REG8(0x4e), 0x05},
310 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xea}, {CCI_REG8(0x4e), 0x05},
311 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x09}, {CCI_REG8(0x4e), 0x05},
312 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x29}, {CCI_REG8(0x4e), 0x05},
313 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x2a}, {CCI_REG8(0x4e), 0x05},
314 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x4a}, {CCI_REG8(0x4e), 0x05},
315 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x06},
316 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x49}, {CCI_REG8(0x4e), 0x06},
317 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x69}, {CCI_REG8(0x4e), 0x06},
318 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x89}, {CCI_REG8(0x4e), 0x06},
319 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xa9}, {CCI_REG8(0x4e), 0x06},
320 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x48}, {CCI_REG8(0x4e), 0x06},
321 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x68}, {CCI_REG8(0x4e), 0x06},
322 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x69}, {CCI_REG8(0x4e), 0x06},
323 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x07},
324 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc9}, {CCI_REG8(0x4e), 0x07},
325 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe9}, {CCI_REG8(0x4e), 0x07},
326 {CCI_REG8(0x4c), 0x03}, {CCI_REG8(0x4d), 0x09}, {CCI_REG8(0x4e), 0x07},
327 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc8}, {CCI_REG8(0x4e), 0x07},
328 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe8}, {CCI_REG8(0x4e), 0x07},
329 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xa7}, {CCI_REG8(0x4e), 0x07},
330 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc7}, {CCI_REG8(0x4e), 0x07},
331 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe7}, {CCI_REG8(0x4e), 0x07},
332 {CCI_REG8(0x4c), 0x03}, {CCI_REG8(0x4d), 0x07}, {CCI_REG8(0x4e), 0x07},
333 {CCI_REG8(0x4f), 0x01},
334 {CCI_REG8(0x50), 0x80}, {CCI_REG8(0x51), 0xa8}, {CCI_REG8(0x52), 0x47},
335 {CCI_REG8(0x53), 0x38}, {CCI_REG8(0x54), 0xc7}, {CCI_REG8(0x56), 0x0e},
336 {CCI_REG8(0x58), 0x08}, {CCI_REG8(0x5b), 0x00}, {CCI_REG8(0x5c), 0x74},
337 {CCI_REG8(0x5d), 0x8b}, {CCI_REG8(0x61), 0xdb}, {CCI_REG8(0x62), 0xb8},
338 {CCI_REG8(0x63), 0x86}, {CCI_REG8(0x64), 0xc0}, {CCI_REG8(0x65), 0x04},
339 {CCI_REG8(0x67), 0xa8}, {CCI_REG8(0x68), 0xb0}, {CCI_REG8(0x69), 0x00},
340 {CCI_REG8(0x6a), 0xa8}, {CCI_REG8(0x6b), 0xb0}, {CCI_REG8(0x6c), 0xaf},
341 {CCI_REG8(0x6d), 0x8b}, {CCI_REG8(0x6e), 0x50}, {CCI_REG8(0x6f), 0x18},
342 {CCI_REG8(0x73), 0xf0}, {CCI_REG8(0x70), 0x0d}, {CCI_REG8(0x71), 0x60},
343 {CCI_REG8(0x72), 0x80}, {CCI_REG8(0x74), 0x01}, {CCI_REG8(0x75), 0x01},
344 {CCI_REG8(0x7f), 0x0c}, {CCI_REG8(0x76), 0x70}, {CCI_REG8(0x77), 0x58},
345 {CCI_REG8(0x78), 0xa0}, {CCI_REG8(0x79), 0x5e}, {CCI_REG8(0x7a), 0x54},
346 {CCI_REG8(0x7b), 0x58},
347 /* CC */
348 {GC2145_REG_PAGE_SELECT, 0x02},
349 {CCI_REG8(0xc0), 0x01}, {CCI_REG8(0xc1), 0x44}, {CCI_REG8(0xc2), 0xfd},
350 {CCI_REG8(0xc3), 0x04}, {CCI_REG8(0xc4), 0xf0}, {CCI_REG8(0xc5), 0x48},
351 {CCI_REG8(0xc6), 0xfd}, {CCI_REG8(0xc7), 0x46}, {CCI_REG8(0xc8), 0xfd},
352 {CCI_REG8(0xc9), 0x02}, {CCI_REG8(0xca), 0xe0}, {CCI_REG8(0xcb), 0x45},
353 {CCI_REG8(0xcc), 0xec}, {CCI_REG8(0xcd), 0x48}, {CCI_REG8(0xce), 0xf0},
354 {CCI_REG8(0xcf), 0xf0}, {CCI_REG8(0xe3), 0x0c}, {CCI_REG8(0xe4), 0x4b},
355 {CCI_REG8(0xe5), 0xe0},
356 /* ABS */
357 {GC2145_REG_PAGE_SELECT, 0x01},
358 {CCI_REG8(0x9f), 0x40},
359 /* Dark sun */
360 {GC2145_REG_PAGE_SELECT, 0x02},
361 {CCI_REG8(0x40), 0xbf}, {CCI_REG8(0x46), 0xcf},
362 };
363
364 #define GC2145_640_480_PIXELRATE 30000000
365 #define GC2145_640_480_LINKFREQ 120000000
366 #define GC2145_640_480_HBLANK 0x0130
367 #define GC2145_640_480_VBLANK 0x000c
368 static const struct cci_reg_sequence gc2145_mode_640_480_regs[] = {
369 {GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0},
370 {GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06},
371 {CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x86},
372 {CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e},
373 /* Disable PAD IO */
374 {GC2145_REG_PAD_IO, 0x00},
375 {GC2145_REG_PAGE_SELECT, 0x00},
376 /* Row/Col start - 0/0 */
377 {GC2145_REG_ROW_START, 0x0000},
378 {GC2145_REG_COL_START, 0x0000},
379 /* Window size 1216/1618 */
380 {GC2145_REG_WIN_HEIGHT, 0x04c0},
381 {GC2145_REG_WIN_WIDTH, 0x0652},
382 /* Scalar more */
383 {CCI_REG8(0xfd), 0x01}, {CCI_REG8(0xfa), 0x00},
384 /* Crop 640-480@0-0 */
385 {GC2145_REG_CROP_ENABLE, 0x01},
386 {GC2145_REG_CROP_Y, 0x0000},
387 {GC2145_REG_CROP_X, 0x0000},
388 {GC2145_REG_CROP_HEIGHT, 0x01e0},
389 {GC2145_REG_CROP_WIDTH, 0x0280},
390 /* Subsampling configuration */
391 {CCI_REG8(0x99), 0x55}, {CCI_REG8(0x9a), 0x06}, {CCI_REG8(0x9b), 0x01},
392 {CCI_REG8(0x9c), 0x23}, {CCI_REG8(0x9d), 0x00}, {CCI_REG8(0x9e), 0x00},
393 {CCI_REG8(0x9f), 0x01}, {CCI_REG8(0xa0), 0x23}, {CCI_REG8(0xa1), 0x00},
394 {CCI_REG8(0xa2), 0x00},
395 {GC2145_REG_PAGE_SELECT, 0x01},
396 /* AEC anti-flicker */
397 {CCI_REG16(0x25), 0x0175},
398 /* AEC exposure level 1-5 */
399 {CCI_REG16(0x27), 0x045f}, {CCI_REG16(0x29), 0x045f},
400 {CCI_REG16(0x2b), 0x045f}, {CCI_REG16(0x2d), 0x045f},
401 };
402
403 #define GC2145_1280_720_PIXELRATE 48000000
404 #define GC2145_1280_720_LINKFREQ 192000000
405 #define GC2145_1280_720_HBLANK 0x0156
406 #define GC2145_1280_720_VBLANK 0x0011
407 static const struct cci_reg_sequence gc2145_mode_1280_720_regs[] = {
408 {GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0},
409 {GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06},
410 {CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x83},
411 {CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e},
412 /* Disable PAD IO */
413 {GC2145_REG_PAD_IO, 0x00},
414 {GC2145_REG_PAGE_SELECT, 0x00},
415 /* Row/Col start - 240/160 */
416 {GC2145_REG_ROW_START, 0x00f0},
417 {GC2145_REG_COL_START, 0x00a0},
418 /* Window size 736/1296 */
419 {GC2145_REG_WIN_HEIGHT, 0x02e0},
420 {GC2145_REG_WIN_WIDTH, 0x0510},
421 /* Crop 1280-720@0-0 */
422 {GC2145_REG_CROP_ENABLE, 0x01},
423 {GC2145_REG_CROP_Y, 0x0000},
424 {GC2145_REG_CROP_X, 0x0000},
425 {GC2145_REG_CROP_HEIGHT, 0x02d0},
426 {GC2145_REG_CROP_WIDTH, 0x0500},
427 {GC2145_REG_PAGE_SELECT, 0x01},
428 /* AEC anti-flicker */
429 {CCI_REG16(0x25), 0x00e6},
430 /* AEC exposure level 1-5 */
431 {CCI_REG16(0x27), 0x02b2}, {CCI_REG16(0x29), 0x02b2},
432 {CCI_REG16(0x2b), 0x02b2}, {CCI_REG16(0x2d), 0x02b2},
433 };
434
435 #define GC2145_1600_1200_PIXELRATE 60000000
436 #define GC2145_1600_1200_LINKFREQ 240000000
437 #define GC2145_1600_1200_HBLANK 0x0156
438 #define GC2145_1600_1200_VBLANK 0x0010
439 static const struct cci_reg_sequence gc2145_mode_1600_1200_regs[] = {
440 {GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0},
441 {GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06},
442 {CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x84},
443 {CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e},
444 /* Disable PAD IO */
445 {GC2145_REG_PAD_IO, 0x00},
446 {GC2145_REG_PAGE_SELECT, 0x00},
447 /* Row/Col start - 0/0 */
448 {GC2145_REG_ROW_START, 0x0000},
449 {GC2145_REG_COL_START, 0x0000},
450 /* Window size: 1216/1618 */
451 {GC2145_REG_WIN_HEIGHT, 0x04c0},
452 {GC2145_REG_WIN_WIDTH, 0x0652},
453 /* Crop 1600-1200@0-0 */
454 {GC2145_REG_CROP_ENABLE, 0x01},
455 {GC2145_REG_CROP_Y, 0x0000},
456 {GC2145_REG_CROP_X, 0x0000},
457 {GC2145_REG_CROP_HEIGHT, 0x04b0},
458 {GC2145_REG_CROP_WIDTH, 0x0640},
459 {GC2145_REG_PAGE_SELECT, 0x01},
460 /* AEC anti-flicker */
461 {CCI_REG16(0x25), 0x00fa},
462 /* AEC exposure level 1-5 */
463 {CCI_REG16(0x27), 0x04e2}, {CCI_REG16(0x29), 0x04e2},
464 {CCI_REG16(0x2b), 0x04e2}, {CCI_REG16(0x2d), 0x04e2},
465 };
466
467 static const s64 gc2145_link_freq_menu[] = {
468 GC2145_640_480_LINKFREQ,
469 GC2145_1280_720_LINKFREQ,
470 GC2145_1600_1200_LINKFREQ,
471 };
472
473 /* Regulators supplies */
474 static const char * const gc2145_supply_name[] = {
475 "iovdd", /* Digital I/O (1.7-3V) suppply */
476 "avdd", /* Analog (2.7-3V) supply */
477 "dvdd", /* Digital Core (1.7-1.9V) supply */
478 };
479
480 #define GC2145_NUM_SUPPLIES ARRAY_SIZE(gc2145_supply_name)
481
482 /* Mode configs */
483 #define GC2145_MODE_640X480 0
484 #define GC2145_MODE_1280X720 1
485 #define GC2145_MODE_1600X1200 2
486 static const struct gc2145_mode supported_modes[] = {
487 {
488 /* 640x480 30fps mode */
489 .width = 640,
490 .height = 480,
491 .reg_seq = gc2145_mode_640_480_regs,
492 .reg_seq_size = ARRAY_SIZE(gc2145_mode_640_480_regs),
493 .pixel_rate = GC2145_640_480_PIXELRATE,
494 .crop = {
495 .top = 0,
496 .left = 0,
497 .width = 640,
498 .height = 480,
499 },
500 .hblank = GC2145_640_480_HBLANK,
501 .vblank = GC2145_640_480_VBLANK,
502 .link_freq_index = GC2145_MODE_640X480,
503 },
504 {
505 /* 1280x720 30fps mode */
506 .width = 1280,
507 .height = 720,
508 .reg_seq = gc2145_mode_1280_720_regs,
509 .reg_seq_size = ARRAY_SIZE(gc2145_mode_1280_720_regs),
510 .pixel_rate = GC2145_1280_720_PIXELRATE,
511 .crop = {
512 .top = 160,
513 .left = 240,
514 .width = 1280,
515 .height = 720,
516 },
517 .hblank = GC2145_1280_720_HBLANK,
518 .vblank = GC2145_1280_720_VBLANK,
519 .link_freq_index = GC2145_MODE_1280X720,
520 },
521 {
522 /* 1600x1200 20fps mode */
523 .width = 1600,
524 .height = 1200,
525 .reg_seq = gc2145_mode_1600_1200_regs,
526 .reg_seq_size = ARRAY_SIZE(gc2145_mode_1600_1200_regs),
527 .pixel_rate = GC2145_1600_1200_PIXELRATE,
528 .crop = {
529 .top = 0,
530 .left = 0,
531 .width = 1600,
532 .height = 1200,
533 },
534 .hblank = GC2145_1600_1200_HBLANK,
535 .vblank = GC2145_1600_1200_VBLANK,
536 .link_freq_index = GC2145_MODE_1600X1200,
537 },
538 };
539
540 /**
541 * struct gc2145_format - GC2145 pixel format description
542 * @code: media bus (MBUS) associated code
543 * @colorspace: V4L2 colorspace
544 * @datatype: MIPI CSI2 data type
545 * @output_fmt: GC2145 output format
546 * @switch_bit: GC2145 first/second switch
547 * @row_col_switch: GC2145 switch row and/or column
548 */
549 struct gc2145_format {
550 unsigned int code;
551 unsigned int colorspace;
552 unsigned char datatype;
553 unsigned char output_fmt;
554 bool switch_bit;
555 unsigned char row_col_switch;
556 };
557
558 /* All supported formats */
559 static const struct gc2145_format supported_formats[] = {
560 {
561 .code = MEDIA_BUS_FMT_UYVY8_1X16,
562 .colorspace = V4L2_COLORSPACE_SRGB,
563 .datatype = MIPI_CSI2_DT_YUV422_8B,
564 .output_fmt = 0x00,
565 },
566 {
567 .code = MEDIA_BUS_FMT_VYUY8_1X16,
568 .colorspace = V4L2_COLORSPACE_SRGB,
569 .datatype = MIPI_CSI2_DT_YUV422_8B,
570 .output_fmt = 0x01,
571 },
572 {
573 .code = MEDIA_BUS_FMT_YUYV8_1X16,
574 .colorspace = V4L2_COLORSPACE_SRGB,
575 .datatype = MIPI_CSI2_DT_YUV422_8B,
576 .output_fmt = 0x02,
577 },
578 {
579 .code = MEDIA_BUS_FMT_YVYU8_1X16,
580 .colorspace = V4L2_COLORSPACE_SRGB,
581 .datatype = MIPI_CSI2_DT_YUV422_8B,
582 .output_fmt = 0x03,
583 },
584 {
585 .code = MEDIA_BUS_FMT_RGB565_1X16,
586 .colorspace = V4L2_COLORSPACE_SRGB,
587 .datatype = MIPI_CSI2_DT_RGB565,
588 .output_fmt = 0x06,
589 .switch_bit = true,
590 },
591 {
592 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
593 .colorspace = V4L2_COLORSPACE_RAW,
594 .datatype = MIPI_CSI2_DT_RAW8,
595 .output_fmt = 0x17,
596 .row_col_switch = GC2145_SYNC_MODE_COL_SWITCH,
597 },
598 {
599 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
600 .colorspace = V4L2_COLORSPACE_RAW,
601 .datatype = MIPI_CSI2_DT_RAW8,
602 .output_fmt = 0x17,
603 .row_col_switch = GC2145_SYNC_MODE_COL_SWITCH | GC2145_SYNC_MODE_ROW_SWITCH,
604 },
605 {
606 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
607 .colorspace = V4L2_COLORSPACE_RAW,
608 .datatype = MIPI_CSI2_DT_RAW8,
609 .output_fmt = 0x17,
610 .row_col_switch = 0,
611 },
612 {
613 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
614 .colorspace = V4L2_COLORSPACE_RAW,
615 .datatype = MIPI_CSI2_DT_RAW8,
616 .output_fmt = 0x17,
617 .row_col_switch = GC2145_SYNC_MODE_ROW_SWITCH,
618 },
619 };
620
621 struct gc2145_ctrls {
622 struct v4l2_ctrl_handler handler;
623 struct v4l2_ctrl *pixel_rate;
624 struct v4l2_ctrl *link_freq;
625 struct v4l2_ctrl *test_pattern;
626 struct v4l2_ctrl *hflip;
627 struct v4l2_ctrl *vflip;
628 struct v4l2_ctrl *hblank;
629 struct v4l2_ctrl *vblank;
630 };
631
632 struct gc2145 {
633 struct v4l2_subdev sd;
634 struct media_pad pad;
635
636 struct regmap *regmap;
637 struct clk *xclk;
638
639 struct gpio_desc *reset_gpio;
640 struct gpio_desc *powerdown_gpio;
641 struct regulator_bulk_data supplies[GC2145_NUM_SUPPLIES];
642
643 /* V4L2 controls */
644 struct gc2145_ctrls ctrls;
645
646 /* Current mode */
647 const struct gc2145_mode *mode;
648 };
649
to_gc2145(struct v4l2_subdev * _sd)650 static inline struct gc2145 *to_gc2145(struct v4l2_subdev *_sd)
651 {
652 return container_of(_sd, struct gc2145, sd);
653 }
654
gc2145_ctrl_to_sd(struct v4l2_ctrl * ctrl)655 static inline struct v4l2_subdev *gc2145_ctrl_to_sd(struct v4l2_ctrl *ctrl)
656 {
657 return &container_of(ctrl->handler, struct gc2145,
658 ctrls.handler)->sd;
659 }
660
661 static const struct gc2145_format *
gc2145_get_format_code(struct gc2145 * gc2145,u32 code)662 gc2145_get_format_code(struct gc2145 *gc2145, u32 code)
663 {
664 unsigned int i;
665
666 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
667 if (supported_formats[i].code == code)
668 break;
669 }
670
671 if (i >= ARRAY_SIZE(supported_formats))
672 i = 0;
673
674 return &supported_formats[i];
675 }
676
gc2145_update_pad_format(struct gc2145 * gc2145,const struct gc2145_mode * mode,struct v4l2_mbus_framefmt * fmt,u32 code,u32 colorspace)677 static void gc2145_update_pad_format(struct gc2145 *gc2145,
678 const struct gc2145_mode *mode,
679 struct v4l2_mbus_framefmt *fmt, u32 code,
680 u32 colorspace)
681 {
682 fmt->code = code;
683 fmt->width = mode->width;
684 fmt->height = mode->height;
685 fmt->field = V4L2_FIELD_NONE;
686 fmt->colorspace = V4L2_COLORSPACE_SRGB;
687 fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
688 fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
689 fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
690 }
691
gc2145_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)692 static int gc2145_init_state(struct v4l2_subdev *sd,
693 struct v4l2_subdev_state *state)
694 {
695 struct gc2145 *gc2145 = to_gc2145(sd);
696 struct v4l2_mbus_framefmt *format;
697 struct v4l2_rect *crop;
698
699 /* Initialize pad format */
700 format = v4l2_subdev_state_get_format(state, 0);
701 gc2145_update_pad_format(gc2145, &supported_modes[0], format,
702 MEDIA_BUS_FMT_RGB565_1X16,
703 V4L2_COLORSPACE_SRGB);
704
705 /* Initialize crop rectangle. */
706 crop = v4l2_subdev_state_get_crop(state, 0);
707 *crop = supported_modes[0].crop;
708
709 return 0;
710 }
711
gc2145_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)712 static int gc2145_get_selection(struct v4l2_subdev *sd,
713 struct v4l2_subdev_state *sd_state,
714 struct v4l2_subdev_selection *sel)
715 {
716 switch (sel->target) {
717 case V4L2_SEL_TGT_CROP:
718 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);
719 return 0;
720
721 case V4L2_SEL_TGT_NATIVE_SIZE:
722 sel->r.top = 0;
723 sel->r.left = 0;
724 sel->r.width = GC2145_NATIVE_WIDTH;
725 sel->r.height = GC2145_NATIVE_HEIGHT;
726
727 return 0;
728
729 case V4L2_SEL_TGT_CROP_DEFAULT:
730 case V4L2_SEL_TGT_CROP_BOUNDS:
731 sel->r.top = 0;
732 sel->r.left = 0;
733 sel->r.width = 1600;
734 sel->r.height = 1200;
735
736 return 0;
737 }
738
739 return -EINVAL;
740 }
741
gc2145_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)742 static int gc2145_enum_mbus_code(struct v4l2_subdev *sd,
743 struct v4l2_subdev_state *sd_state,
744 struct v4l2_subdev_mbus_code_enum *code)
745 {
746 if (code->index >= ARRAY_SIZE(supported_formats))
747 return -EINVAL;
748
749 code->code = supported_formats[code->index].code;
750 return 0;
751 }
752
gc2145_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)753 static int gc2145_enum_frame_size(struct v4l2_subdev *sd,
754 struct v4l2_subdev_state *sd_state,
755 struct v4l2_subdev_frame_size_enum *fse)
756 {
757 struct gc2145 *gc2145 = to_gc2145(sd);
758 const struct gc2145_format *gc2145_format;
759 u32 code;
760
761 if (fse->index >= ARRAY_SIZE(supported_modes))
762 return -EINVAL;
763
764 gc2145_format = gc2145_get_format_code(gc2145, fse->code);
765 code = gc2145_format->code;
766 if (fse->code != code)
767 return -EINVAL;
768
769 fse->min_width = supported_modes[fse->index].width;
770 fse->max_width = fse->min_width;
771 fse->min_height = supported_modes[fse->index].height;
772 fse->max_height = fse->min_height;
773
774 return 0;
775 }
776
gc2145_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)777 static int gc2145_set_pad_format(struct v4l2_subdev *sd,
778 struct v4l2_subdev_state *sd_state,
779 struct v4l2_subdev_format *fmt)
780 {
781 struct gc2145 *gc2145 = to_gc2145(sd);
782 const struct gc2145_mode *mode;
783 const struct gc2145_format *gc2145_fmt;
784 struct v4l2_mbus_framefmt *framefmt;
785 struct gc2145_ctrls *ctrls = &gc2145->ctrls;
786 struct v4l2_rect *crop;
787
788 gc2145_fmt = gc2145_get_format_code(gc2145, fmt->format.code);
789 mode = v4l2_find_nearest_size(supported_modes,
790 ARRAY_SIZE(supported_modes),
791 width, height,
792 fmt->format.width, fmt->format.height);
793
794 /* In RAW mode, VGA is not possible so use 720p instead */
795 if (gc2145_fmt->colorspace == V4L2_COLORSPACE_RAW &&
796 mode == &supported_modes[GC2145_MODE_640X480])
797 mode = &supported_modes[GC2145_MODE_1280X720];
798
799 gc2145_update_pad_format(gc2145, mode, &fmt->format, gc2145_fmt->code,
800 gc2145_fmt->colorspace);
801 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
802 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
803 gc2145->mode = mode;
804 /* Update pixel_rate based on the mode */
805 __v4l2_ctrl_s_ctrl_int64(ctrls->pixel_rate, mode->pixel_rate);
806 /* Update link_freq based on the mode */
807 __v4l2_ctrl_s_ctrl(ctrls->link_freq, mode->link_freq_index);
808 /* Update hblank/vblank based on the mode */
809 __v4l2_ctrl_s_ctrl(ctrls->hblank, mode->hblank);
810 __v4l2_ctrl_s_ctrl(ctrls->vblank, mode->vblank);
811 }
812 *framefmt = fmt->format;
813 crop = v4l2_subdev_state_get_crop(sd_state, fmt->pad);
814 *crop = mode->crop;
815
816 return 0;
817 }
818
819 static const struct cci_reg_sequence gc2145_common_mipi_regs[] = {
820 {GC2145_REG_PAGE_SELECT, 0x03},
821 {GC2145_REG_DPHY_ANALOG_MODE1, GC2145_DPHY_MODE_PHY_CLK_EN |
822 GC2145_DPHY_MODE_PHY_LANE0_EN |
823 GC2145_DPHY_MODE_PHY_LANE1_EN |
824 GC2145_DPHY_MODE_PHY_CLK_LANE_P2S_SEL},
825 {GC2145_REG_DPHY_ANALOG_MODE2, GC2145_DPHY_CLK_DIFF(2) |
826 GC2145_DPHY_LANE0_DIFF(2)},
827 {GC2145_REG_DPHY_ANALOG_MODE3, GC2145_DPHY_LANE1_DIFF(0) |
828 GC2145_DPHY_CLK_DELAY},
829 {GC2145_REG_FIFO_MODE, GC2145_FIFO_MODE_READ_GATE |
830 GC2145_FIFO_MODE_MIPI_CLK_MODULE},
831 {GC2145_REG_DPHY_MODE, GC2145_DPHY_MODE_TRIGGER_PROG},
832 /* Clock & Data lanes timing */
833 {GC2145_REG_T_LPX, 0x10},
834 {GC2145_REG_T_CLK_HS_PREPARE, 0x04}, {GC2145_REG_T_CLK_ZERO, 0x10},
835 {GC2145_REG_T_CLK_PRE, 0x10}, {GC2145_REG_T_CLK_POST, 0x10},
836 {GC2145_REG_T_CLK_TRAIL, 0x05},
837 {GC2145_REG_T_HS_PREPARE, 0x03}, {GC2145_REG_T_HS_ZERO, 0x0a},
838 {GC2145_REG_T_HS_TRAIL, 0x06},
839 };
840
gc2145_config_mipi_mode(struct gc2145 * gc2145,const struct gc2145_format * gc2145_format)841 static int gc2145_config_mipi_mode(struct gc2145 *gc2145,
842 const struct gc2145_format *gc2145_format)
843 {
844 u16 lwc, fifo_full_lvl;
845 int ret = 0;
846
847 /* Common MIPI settings */
848 cci_multi_reg_write(gc2145->regmap, gc2145_common_mipi_regs,
849 ARRAY_SIZE(gc2145_common_mipi_regs), &ret);
850
851 /*
852 * Adjust the MIPI buffer settings.
853 * For YUV/RGB, LWC = image width * 2
854 * For RAW8, LWC = image width
855 * For RAW10, LWC = image width * 1.25
856 */
857 if (gc2145_format->colorspace != V4L2_COLORSPACE_RAW)
858 lwc = gc2145->mode->width * 2;
859 else
860 lwc = gc2145->mode->width;
861
862 cci_write(gc2145->regmap, GC2145_REG_LWC, lwc, &ret);
863
864 /*
865 * Adjust the MIPI FIFO Full Level
866 * 640x480 RGB: 0x0190
867 * 1280x720 / 1600x1200 (aka no scaler) non RAW: 0x0001
868 * 1600x1200 RAW: 0x0190
869 */
870 if (gc2145_format->colorspace != V4L2_COLORSPACE_RAW) {
871 if (gc2145->mode->width == 1280 || gc2145->mode->width == 1600)
872 fifo_full_lvl = 0x0001;
873 else
874 fifo_full_lvl = 0x0190;
875 } else {
876 fifo_full_lvl = 0x0190;
877 }
878
879 cci_write(gc2145->regmap, GC2145_REG_FIFO_FULL_LVL,
880 fifo_full_lvl, &ret);
881
882 /*
883 * Set the FIFO gate mode / MIPI wdiv set:
884 * 0xf1 in case of RAW mode and 0xf0 otherwise
885 */
886 cci_write(gc2145->regmap, GC2145_REG_FIFO_GATE_MODE,
887 gc2145_format->colorspace == V4L2_COLORSPACE_RAW ?
888 0xf1 : 0xf0, &ret);
889
890 /* Set the MIPI data type */
891 cci_write(gc2145->regmap, GC2145_REG_MIPI_DT,
892 gc2145_format->datatype, &ret);
893
894 /* Configure mode and enable CSI */
895 cci_write(gc2145->regmap, GC2145_REG_BUF_CSI2_MODE,
896 GC2145_CSI2_MODE_RAW8 | GC2145_CSI2_MODE_DOUBLE |
897 GC2145_CSI2_MODE_EN | GC2145_CSI2_MODE_MIPI_EN, &ret);
898
899 return ret;
900 }
901
gc2145_start_streaming(struct gc2145 * gc2145,struct v4l2_subdev_state * state)902 static int gc2145_start_streaming(struct gc2145 *gc2145,
903 struct v4l2_subdev_state *state)
904 {
905 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd);
906 const struct gc2145_format *gc2145_format;
907 struct v4l2_mbus_framefmt *fmt;
908 int ret;
909
910 ret = pm_runtime_resume_and_get(&client->dev);
911 if (ret < 0)
912 return ret;
913
914 /* Apply default values of current mode */
915 cci_multi_reg_write(gc2145->regmap, gc2145->mode->reg_seq,
916 gc2145->mode->reg_seq_size, &ret);
917 cci_multi_reg_write(gc2145->regmap, gc2145_common_regs,
918 ARRAY_SIZE(gc2145_common_regs), &ret);
919 if (ret) {
920 dev_err(&client->dev, "%s failed to write regs\n", __func__);
921 goto err_rpm_put;
922 }
923
924 fmt = v4l2_subdev_state_get_format(state, 0);
925 gc2145_format = gc2145_get_format_code(gc2145, fmt->code);
926
927 /* Set the output format */
928 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x00, &ret);
929
930 cci_write(gc2145->regmap, GC2145_REG_OUTPUT_FMT,
931 gc2145_format->output_fmt, &ret);
932 cci_update_bits(gc2145->regmap, GC2145_REG_BYPASS_MODE,
933 GC2145_BYPASS_MODE_SWITCH,
934 gc2145_format->switch_bit ? GC2145_BYPASS_MODE_SWITCH
935 : 0, &ret);
936 cci_update_bits(gc2145->regmap, GC2145_REG_SYNC_MODE,
937 GC2145_SYNC_MODE_COL_SWITCH |
938 GC2145_SYNC_MODE_ROW_SWITCH,
939 gc2145_format->row_col_switch, &ret);
940 if (ret) {
941 dev_err(&client->dev, "%s failed to write regs\n", __func__);
942 goto err_rpm_put;
943 }
944
945 /* Apply customized values from user */
946 ret = __v4l2_ctrl_handler_setup(&gc2145->ctrls.handler);
947 if (ret) {
948 dev_err(&client->dev, "%s failed to apply ctrls\n", __func__);
949 goto err_rpm_put;
950 }
951
952 /* Perform MIPI specific configuration */
953 ret = gc2145_config_mipi_mode(gc2145, gc2145_format);
954 if (ret) {
955 dev_err(&client->dev, "%s failed to write mipi conf\n",
956 __func__);
957 goto err_rpm_put;
958 }
959
960 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x00, &ret);
961
962 return 0;
963
964 err_rpm_put:
965 pm_runtime_mark_last_busy(&client->dev);
966 pm_runtime_put_autosuspend(&client->dev);
967 return ret;
968 }
969
gc2145_stop_streaming(struct gc2145 * gc2145)970 static void gc2145_stop_streaming(struct gc2145 *gc2145)
971 {
972 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd);
973 int ret = 0;
974
975 /* Disable lanes & mipi streaming */
976 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x03, &ret);
977 cci_update_bits(gc2145->regmap, GC2145_REG_BUF_CSI2_MODE,
978 GC2145_CSI2_MODE_EN | GC2145_CSI2_MODE_MIPI_EN, 0,
979 &ret);
980 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x00, &ret);
981 if (ret)
982 dev_err(&client->dev, "%s failed to write regs\n", __func__);
983
984 pm_runtime_mark_last_busy(&client->dev);
985 pm_runtime_put_autosuspend(&client->dev);
986 }
987
gc2145_set_stream(struct v4l2_subdev * sd,int enable)988 static int gc2145_set_stream(struct v4l2_subdev *sd, int enable)
989 {
990 struct gc2145 *gc2145 = to_gc2145(sd);
991 struct v4l2_subdev_state *state;
992 int ret = 0;
993
994 state = v4l2_subdev_lock_and_get_active_state(sd);
995
996 if (enable)
997 ret = gc2145_start_streaming(gc2145, state);
998 else
999 gc2145_stop_streaming(gc2145);
1000
1001 v4l2_subdev_unlock_state(state);
1002
1003 return ret;
1004 }
1005
1006 /* Power/clock management functions */
gc2145_power_on(struct device * dev)1007 static int gc2145_power_on(struct device *dev)
1008 {
1009 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1010 struct gc2145 *gc2145 = to_gc2145(sd);
1011 int ret;
1012
1013 ret = regulator_bulk_enable(GC2145_NUM_SUPPLIES, gc2145->supplies);
1014 if (ret) {
1015 dev_err(dev, "failed to enable regulators\n");
1016 return ret;
1017 }
1018
1019 ret = clk_prepare_enable(gc2145->xclk);
1020 if (ret) {
1021 dev_err(dev, "failed to enable clock\n");
1022 goto reg_off;
1023 }
1024
1025 gpiod_set_value_cansleep(gc2145->powerdown_gpio, 0);
1026 gpiod_set_value_cansleep(gc2145->reset_gpio, 0);
1027
1028 /*
1029 * Datasheet doesn't mention timing between PWDN/RESETB control and
1030 * i2c access however, experimentation shows that a rather big delay is
1031 * needed.
1032 */
1033 msleep(41);
1034
1035 return 0;
1036
1037 reg_off:
1038 regulator_bulk_disable(GC2145_NUM_SUPPLIES, gc2145->supplies);
1039
1040 return ret;
1041 }
1042
gc2145_power_off(struct device * dev)1043 static int gc2145_power_off(struct device *dev)
1044 {
1045 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1046 struct gc2145 *gc2145 = to_gc2145(sd);
1047
1048 gpiod_set_value_cansleep(gc2145->powerdown_gpio, 1);
1049 gpiod_set_value_cansleep(gc2145->reset_gpio, 1);
1050 clk_disable_unprepare(gc2145->xclk);
1051 regulator_bulk_disable(GC2145_NUM_SUPPLIES, gc2145->supplies);
1052
1053 return 0;
1054 }
1055
gc2145_get_regulators(struct gc2145 * gc2145)1056 static int gc2145_get_regulators(struct gc2145 *gc2145)
1057 {
1058 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd);
1059 unsigned int i;
1060
1061 for (i = 0; i < GC2145_NUM_SUPPLIES; i++)
1062 gc2145->supplies[i].supply = gc2145_supply_name[i];
1063
1064 return devm_regulator_bulk_get(&client->dev, GC2145_NUM_SUPPLIES,
1065 gc2145->supplies);
1066 }
1067
1068 /* Verify chip ID */
gc2145_identify_module(struct gc2145 * gc2145)1069 static int gc2145_identify_module(struct gc2145 *gc2145)
1070 {
1071 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd);
1072 int ret;
1073 u64 chip_id;
1074
1075 ret = cci_read(gc2145->regmap, GC2145_REG_CHIP_ID, &chip_id, NULL);
1076 if (ret) {
1077 dev_err(&client->dev, "failed to read chip id (%d)\n", ret);
1078 return ret;
1079 }
1080
1081 if (chip_id != GC2145_CHIP_ID) {
1082 dev_err(&client->dev, "chip id mismatch: %x!=%llx\n",
1083 GC2145_CHIP_ID, chip_id);
1084 return -EIO;
1085 }
1086
1087 return 0;
1088 }
1089
1090 static const char * const test_pattern_menu[] = {
1091 "Disabled",
1092 "Colored patterns",
1093 "Uniform white",
1094 "Uniform yellow",
1095 "Uniform cyan",
1096 "Uniform green",
1097 "Uniform magenta",
1098 "Uniform red",
1099 "Uniform black",
1100 };
1101
1102 #define GC2145_TEST_PATTERN_ENABLE BIT(0)
1103 #define GC2145_TEST_PATTERN_UXGA BIT(3)
1104
1105 #define GC2145_TEST_UNIFORM BIT(3)
1106 #define GC2145_TEST_WHITE (4 << 4)
1107 #define GC2145_TEST_YELLOW (8 << 4)
1108 #define GC2145_TEST_CYAN (9 << 4)
1109 #define GC2145_TEST_GREEN (6 << 4)
1110 #define GC2145_TEST_MAGENTA (10 << 4)
1111 #define GC2145_TEST_RED (5 << 4)
1112 #define GC2145_TEST_BLACK (0)
1113
1114 static const u8 test_pattern_val[] = {
1115 0,
1116 GC2145_TEST_PATTERN_ENABLE,
1117 GC2145_TEST_UNIFORM | GC2145_TEST_WHITE,
1118 GC2145_TEST_UNIFORM | GC2145_TEST_YELLOW,
1119 GC2145_TEST_UNIFORM | GC2145_TEST_CYAN,
1120 GC2145_TEST_UNIFORM | GC2145_TEST_GREEN,
1121 GC2145_TEST_UNIFORM | GC2145_TEST_MAGENTA,
1122 GC2145_TEST_UNIFORM | GC2145_TEST_RED,
1123 GC2145_TEST_UNIFORM | GC2145_TEST_BLACK,
1124 };
1125
1126 static const struct v4l2_subdev_core_ops gc2145_core_ops = {
1127 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1128 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1129 };
1130
1131 static const struct v4l2_subdev_video_ops gc2145_video_ops = {
1132 .s_stream = gc2145_set_stream,
1133 };
1134
1135 static const struct v4l2_subdev_pad_ops gc2145_pad_ops = {
1136 .enum_mbus_code = gc2145_enum_mbus_code,
1137 .get_fmt = v4l2_subdev_get_fmt,
1138 .set_fmt = gc2145_set_pad_format,
1139 .get_selection = gc2145_get_selection,
1140 .enum_frame_size = gc2145_enum_frame_size,
1141 };
1142
1143 static const struct v4l2_subdev_ops gc2145_subdev_ops = {
1144 .core = &gc2145_core_ops,
1145 .video = &gc2145_video_ops,
1146 .pad = &gc2145_pad_ops,
1147 };
1148
1149 static const struct v4l2_subdev_internal_ops gc2145_subdev_internal_ops = {
1150 .init_state = gc2145_init_state,
1151 };
1152
gc2145_set_ctrl_test_pattern(struct gc2145 * gc2145,int value)1153 static int gc2145_set_ctrl_test_pattern(struct gc2145 *gc2145, int value)
1154 {
1155 int ret = 0;
1156
1157 if (!value) {
1158 /* Disable test pattern */
1159 cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE2, 0, &ret);
1160 return cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE3, 0,
1161 &ret);
1162 }
1163
1164 /* Enable test pattern, colored or uniform */
1165 cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE2,
1166 GC2145_TEST_PATTERN_ENABLE | GC2145_TEST_PATTERN_UXGA, &ret);
1167
1168 if (!(test_pattern_val[value] & GC2145_TEST_UNIFORM))
1169 return cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE3, 0,
1170 &ret);
1171
1172 /* Uniform */
1173 return cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE3,
1174 test_pattern_val[value], &ret);
1175 }
1176
gc2145_s_ctrl(struct v4l2_ctrl * ctrl)1177 static int gc2145_s_ctrl(struct v4l2_ctrl *ctrl)
1178 {
1179 struct v4l2_subdev *sd = gc2145_ctrl_to_sd(ctrl);
1180 struct i2c_client *client = v4l2_get_subdevdata(sd);
1181 struct gc2145 *gc2145 = to_gc2145(sd);
1182 int ret;
1183
1184 if (pm_runtime_get_if_in_use(&client->dev) == 0)
1185 return 0;
1186
1187 switch (ctrl->id) {
1188 case V4L2_CID_HBLANK:
1189 ret = cci_write(gc2145->regmap, GC2145_REG_HBLANK, ctrl->val,
1190 NULL);
1191 break;
1192 case V4L2_CID_VBLANK:
1193 ret = cci_write(gc2145->regmap, GC2145_REG_VBLANK, ctrl->val,
1194 NULL);
1195 break;
1196 case V4L2_CID_TEST_PATTERN:
1197 ret = gc2145_set_ctrl_test_pattern(gc2145, ctrl->val);
1198 break;
1199 case V4L2_CID_HFLIP:
1200 ret = cci_update_bits(gc2145->regmap, GC2145_REG_ANALOG_MODE1,
1201 BIT(0), (ctrl->val ? BIT(0) : 0), NULL);
1202 break;
1203 case V4L2_CID_VFLIP:
1204 ret = cci_update_bits(gc2145->regmap, GC2145_REG_ANALOG_MODE1,
1205 BIT(1), (ctrl->val ? BIT(1) : 0), NULL);
1206 break;
1207 default:
1208 ret = -EINVAL;
1209 break;
1210 }
1211
1212 pm_runtime_mark_last_busy(&client->dev);
1213 pm_runtime_put_autosuspend(&client->dev);
1214
1215 return ret;
1216 }
1217
1218 static const struct v4l2_ctrl_ops gc2145_ctrl_ops = {
1219 .s_ctrl = gc2145_s_ctrl,
1220 };
1221
1222 /* Initialize control handlers */
gc2145_init_controls(struct gc2145 * gc2145)1223 static int gc2145_init_controls(struct gc2145 *gc2145)
1224 {
1225 struct i2c_client *client = v4l2_get_subdevdata(&gc2145->sd);
1226 const struct v4l2_ctrl_ops *ops = &gc2145_ctrl_ops;
1227 struct gc2145_ctrls *ctrls = &gc2145->ctrls;
1228 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1229 struct v4l2_fwnode_device_properties props;
1230 int ret;
1231
1232 ret = v4l2_ctrl_handler_init(hdl, 12);
1233 if (ret)
1234 return ret;
1235
1236 ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
1237 GC2145_640_480_PIXELRATE,
1238 GC2145_1600_1200_PIXELRATE, 1,
1239 supported_modes[0].pixel_rate);
1240
1241 ctrls->link_freq = v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_LINK_FREQ,
1242 ARRAY_SIZE(gc2145_link_freq_menu) - 1,
1243 0, gc2145_link_freq_menu);
1244 if (ctrls->link_freq)
1245 ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1246
1247 ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
1248 0, 0xfff, 1, GC2145_640_480_HBLANK);
1249
1250 ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
1251 0, 0x1fff, 1, GC2145_640_480_VBLANK);
1252
1253 ctrls->test_pattern =
1254 v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
1255 ARRAY_SIZE(test_pattern_menu) - 1,
1256 0, 0, test_pattern_menu);
1257 ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP,
1258 0, 1, 1, 0);
1259 ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP,
1260 0, 1, 1, 0);
1261
1262 if (hdl->error) {
1263 ret = hdl->error;
1264 dev_err(&client->dev, "control init failed (%d)\n", ret);
1265 goto error;
1266 }
1267
1268 ret = v4l2_fwnode_device_parse(&client->dev, &props);
1269 if (ret)
1270 goto error;
1271
1272 ret = v4l2_ctrl_new_fwnode_properties(hdl, &gc2145_ctrl_ops,
1273 &props);
1274 if (ret)
1275 goto error;
1276
1277 gc2145->sd.ctrl_handler = hdl;
1278
1279 return 0;
1280
1281 error:
1282 v4l2_ctrl_handler_free(hdl);
1283
1284 return ret;
1285 }
1286
gc2145_check_hwcfg(struct device * dev)1287 static int gc2145_check_hwcfg(struct device *dev)
1288 {
1289 struct fwnode_handle *endpoint;
1290 struct v4l2_fwnode_endpoint ep_cfg = {
1291 .bus_type = V4L2_MBUS_CSI2_DPHY
1292 };
1293 int ret;
1294
1295 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1296 if (!endpoint) {
1297 dev_err(dev, "endpoint node not found\n");
1298 return -EINVAL;
1299 }
1300
1301 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg);
1302 fwnode_handle_put(endpoint);
1303 if (ret)
1304 return ret;
1305
1306 /* Check the number of MIPI CSI2 data lanes */
1307 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2) {
1308 dev_err(dev, "only 2 data lanes are currently supported\n");
1309 ret = -EINVAL;
1310 goto out;
1311 }
1312
1313 /* Check the link frequency set in device tree */
1314 if (!ep_cfg.nr_of_link_frequencies) {
1315 dev_err(dev, "link-frequency property not found in DT\n");
1316 ret = -EINVAL;
1317 goto out;
1318 }
1319
1320 if (ep_cfg.nr_of_link_frequencies != 3 ||
1321 ep_cfg.link_frequencies[0] != GC2145_640_480_LINKFREQ ||
1322 ep_cfg.link_frequencies[1] != GC2145_1280_720_LINKFREQ ||
1323 ep_cfg.link_frequencies[2] != GC2145_1600_1200_LINKFREQ) {
1324 dev_err(dev, "Invalid link-frequencies provided\n");
1325 ret = -EINVAL;
1326 }
1327
1328 out:
1329 v4l2_fwnode_endpoint_free(&ep_cfg);
1330
1331 return ret;
1332 }
1333
gc2145_probe(struct i2c_client * client)1334 static int gc2145_probe(struct i2c_client *client)
1335 {
1336 struct device *dev = &client->dev;
1337 unsigned int xclk_freq;
1338 struct gc2145 *gc2145;
1339 int ret;
1340
1341 gc2145 = devm_kzalloc(&client->dev, sizeof(*gc2145), GFP_KERNEL);
1342 if (!gc2145)
1343 return -ENOMEM;
1344
1345 v4l2_i2c_subdev_init(&gc2145->sd, client, &gc2145_subdev_ops);
1346 gc2145->sd.internal_ops = &gc2145_subdev_internal_ops;
1347
1348 /* Check the hardware configuration in device tree */
1349 if (gc2145_check_hwcfg(dev))
1350 return -EINVAL;
1351
1352 /* Get system clock (xclk) */
1353 gc2145->xclk = devm_clk_get(dev, NULL);
1354 if (IS_ERR(gc2145->xclk))
1355 return dev_err_probe(dev, PTR_ERR(gc2145->xclk),
1356 "failed to get xclk\n");
1357
1358 xclk_freq = clk_get_rate(gc2145->xclk);
1359 if (xclk_freq != GC2145_XCLK_FREQ) {
1360 dev_err(dev, "xclk frequency not supported: %d Hz\n",
1361 xclk_freq);
1362 return -EINVAL;
1363 }
1364
1365 ret = gc2145_get_regulators(gc2145);
1366 if (ret)
1367 return dev_err_probe(dev, ret,
1368 "failed to get regulators\n");
1369
1370 /* Request optional reset pin */
1371 gc2145->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1372 GPIOD_OUT_HIGH);
1373 if (IS_ERR(gc2145->reset_gpio))
1374 return dev_err_probe(dev, PTR_ERR(gc2145->reset_gpio),
1375 "failed to get reset_gpio\n");
1376
1377 /* Request optional powerdown pin */
1378 gc2145->powerdown_gpio = devm_gpiod_get_optional(dev, "powerdown",
1379 GPIOD_OUT_HIGH);
1380 if (IS_ERR(gc2145->powerdown_gpio))
1381 return dev_err_probe(dev, PTR_ERR(gc2145->powerdown_gpio),
1382 "failed to get powerdown_gpio\n");
1383
1384 /* Initialise the regmap for further cci access */
1385 gc2145->regmap = devm_cci_regmap_init_i2c(client, 8);
1386 if (IS_ERR(gc2145->regmap))
1387 return dev_err_probe(dev, PTR_ERR(gc2145->regmap),
1388 "failed to get cci regmap\n");
1389
1390 /*
1391 * The sensor must be powered for gc2145_identify_module()
1392 * to be able to read the CHIP_ID register
1393 */
1394 ret = gc2145_power_on(dev);
1395 if (ret)
1396 return ret;
1397
1398 ret = gc2145_identify_module(gc2145);
1399 if (ret)
1400 goto error_power_off;
1401
1402 /* Set default mode */
1403 gc2145->mode = &supported_modes[0];
1404
1405 ret = gc2145_init_controls(gc2145);
1406 if (ret)
1407 goto error_power_off;
1408
1409 /* Initialize subdev */
1410 gc2145->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1411 V4L2_SUBDEV_FL_HAS_EVENTS;
1412 gc2145->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1413
1414 /* Initialize source pad */
1415 gc2145->pad.flags = MEDIA_PAD_FL_SOURCE;
1416
1417 ret = media_entity_pads_init(&gc2145->sd.entity, 1, &gc2145->pad);
1418 if (ret) {
1419 dev_err(dev, "failed to init entity pads: %d\n", ret);
1420 goto error_handler_free;
1421 }
1422
1423 gc2145->sd.state_lock = gc2145->ctrls.handler.lock;
1424 ret = v4l2_subdev_init_finalize(&gc2145->sd);
1425 if (ret < 0) {
1426 dev_err(dev, "subdev init error: %d\n", ret);
1427 goto error_media_entity;
1428 }
1429
1430 /* Enable runtime PM and turn off the device */
1431 pm_runtime_set_active(dev);
1432 pm_runtime_get_noresume(&client->dev);
1433 pm_runtime_enable(dev);
1434
1435 pm_runtime_set_autosuspend_delay(&client->dev, 1000);
1436 pm_runtime_use_autosuspend(&client->dev);
1437 pm_runtime_put_autosuspend(&client->dev);
1438
1439 ret = v4l2_async_register_subdev_sensor(&gc2145->sd);
1440 if (ret < 0) {
1441 dev_err(dev, "failed to register sensor sub-device: %d\n", ret);
1442 goto error_subdev_cleanup;
1443 }
1444
1445 return 0;
1446
1447 error_subdev_cleanup:
1448 v4l2_subdev_cleanup(&gc2145->sd);
1449 pm_runtime_disable(&client->dev);
1450 pm_runtime_set_suspended(&client->dev);
1451
1452 error_media_entity:
1453 media_entity_cleanup(&gc2145->sd.entity);
1454
1455 error_handler_free:
1456 v4l2_ctrl_handler_free(&gc2145->ctrls.handler);
1457
1458 error_power_off:
1459 gc2145_power_off(dev);
1460
1461 return ret;
1462 }
1463
gc2145_remove(struct i2c_client * client)1464 static void gc2145_remove(struct i2c_client *client)
1465 {
1466 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1467 struct gc2145 *gc2145 = to_gc2145(sd);
1468
1469 v4l2_subdev_cleanup(sd);
1470 v4l2_async_unregister_subdev(sd);
1471 media_entity_cleanup(&sd->entity);
1472 v4l2_ctrl_handler_free(&gc2145->ctrls.handler);
1473
1474 pm_runtime_disable(&client->dev);
1475 if (!pm_runtime_status_suspended(&client->dev))
1476 gc2145_power_off(&client->dev);
1477 pm_runtime_set_suspended(&client->dev);
1478 }
1479
1480 static const struct of_device_id gc2145_dt_ids[] = {
1481 { .compatible = "galaxycore,gc2145" },
1482 { /* sentinel */ }
1483 };
1484 MODULE_DEVICE_TABLE(of, gc2145_dt_ids);
1485
1486 static const struct dev_pm_ops gc2145_pm_ops = {
1487 RUNTIME_PM_OPS(gc2145_power_off, gc2145_power_on, NULL)
1488 };
1489
1490 static struct i2c_driver gc2145_i2c_driver = {
1491 .driver = {
1492 .name = "gc2145",
1493 .of_match_table = gc2145_dt_ids,
1494 .pm = pm_ptr(&gc2145_pm_ops),
1495 },
1496 .probe = gc2145_probe,
1497 .remove = gc2145_remove,
1498 };
1499
1500 module_i2c_driver(gc2145_i2c_driver);
1501
1502 MODULE_AUTHOR("Alain Volmat <alain.volmat@foss.st.com>");
1503 MODULE_DESCRIPTION("GalaxyCore GC2145 sensor driver");
1504 MODULE_LICENSE("GPL");
1505