1 // SPDX-License-Identifier: GPL-2.0-or-later
2 #include <linux/of_irq.h>
3 #include "i2c-viai2c-common.h"
4
viai2c_wait_bus_not_busy(struct viai2c * i2c)5 int viai2c_wait_bus_not_busy(struct viai2c *i2c)
6 {
7 unsigned long timeout;
8
9 timeout = jiffies + VIAI2C_TIMEOUT;
10 while (!(readw(i2c->base + VIAI2C_REG_CSR) & VIAI2C_CSR_READY_MASK)) {
11 if (time_after(jiffies, timeout)) {
12 dev_warn(i2c->dev, "timeout waiting for bus ready\n");
13 return -EBUSY;
14 }
15 msleep(20);
16 }
17
18 return 0;
19 }
20 EXPORT_SYMBOL_GPL(viai2c_wait_bus_not_busy);
21
viai2c_write(struct viai2c * i2c,struct i2c_msg * pmsg,int last)22 static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last)
23 {
24 u16 val, tcr_val = i2c->tcr;
25
26 i2c->last = last;
27
28 if (pmsg->len == 0) {
29 /*
30 * We still need to run through the while (..) once, so
31 * start at -1 and break out early from the loop
32 */
33 i2c->xfered_len = -1;
34 writew(0, i2c->base + VIAI2C_REG_CDR);
35 } else {
36 writew(pmsg->buf[0] & 0xFF, i2c->base + VIAI2C_REG_CDR);
37 }
38
39 if (i2c->platform == VIAI2C_PLAT_WMT && !(pmsg->flags & I2C_M_NOSTART)) {
40 val = readw(i2c->base + VIAI2C_REG_CR);
41 val &= ~VIAI2C_CR_TX_END;
42 val |= VIAI2C_CR_CPU_RDY;
43 writew(val, i2c->base + VIAI2C_REG_CR);
44 }
45
46 reinit_completion(&i2c->complete);
47
48 tcr_val |= pmsg->addr & VIAI2C_TCR_ADDR_MASK;
49
50 writew(tcr_val, i2c->base + VIAI2C_REG_TCR);
51
52 if (i2c->platform == VIAI2C_PLAT_WMT && pmsg->flags & I2C_M_NOSTART) {
53 val = readw(i2c->base + VIAI2C_REG_CR);
54 val |= VIAI2C_CR_CPU_RDY;
55 writew(val, i2c->base + VIAI2C_REG_CR);
56 }
57
58 if (!wait_for_completion_timeout(&i2c->complete, VIAI2C_TIMEOUT))
59 return -ETIMEDOUT;
60
61 return i2c->ret;
62 }
63
viai2c_read(struct viai2c * i2c,struct i2c_msg * pmsg,bool first)64 static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg, bool first)
65 {
66 u16 val, tcr_val = i2c->tcr;
67
68 val = readw(i2c->base + VIAI2C_REG_CR);
69 val &= ~(VIAI2C_CR_TX_END | VIAI2C_CR_RX_END);
70
71 if (i2c->platform == VIAI2C_PLAT_WMT && !(pmsg->flags & I2C_M_NOSTART))
72 val |= VIAI2C_CR_CPU_RDY;
73
74 if (pmsg->len == 1)
75 val |= VIAI2C_CR_RX_END;
76
77 writew(val, i2c->base + VIAI2C_REG_CR);
78
79 reinit_completion(&i2c->complete);
80
81 tcr_val |= VIAI2C_TCR_READ | (pmsg->addr & VIAI2C_TCR_ADDR_MASK);
82
83 writew(tcr_val, i2c->base + VIAI2C_REG_TCR);
84
85 if ((i2c->platform == VIAI2C_PLAT_WMT && (pmsg->flags & I2C_M_NOSTART)) ||
86 (i2c->platform == VIAI2C_PLAT_ZHAOXIN && !first)) {
87 val = readw(i2c->base + VIAI2C_REG_CR);
88 val |= VIAI2C_CR_CPU_RDY;
89 writew(val, i2c->base + VIAI2C_REG_CR);
90 }
91
92 if (!wait_for_completion_timeout(&i2c->complete, VIAI2C_TIMEOUT))
93 return -ETIMEDOUT;
94
95 return i2c->ret;
96 }
97
viai2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)98 int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
99 {
100 struct i2c_msg *pmsg;
101 int i;
102 int ret = 0;
103 struct viai2c *i2c = i2c_get_adapdata(adap);
104
105 i2c->mode = VIAI2C_BYTE_MODE;
106 for (i = 0; ret >= 0 && i < num; i++) {
107 pmsg = &msgs[i];
108 if (i2c->platform == VIAI2C_PLAT_WMT && !(pmsg->flags & I2C_M_NOSTART)) {
109 ret = viai2c_wait_bus_not_busy(i2c);
110 if (ret < 0)
111 return ret;
112 }
113
114 i2c->msg = pmsg;
115 i2c->xfered_len = 0;
116
117 if (pmsg->flags & I2C_M_RD)
118 ret = viai2c_read(i2c, pmsg, i == 0);
119 else
120 ret = viai2c_write(i2c, pmsg, (i + 1) == num);
121 }
122
123 return (ret < 0) ? ret : i;
124 }
125 EXPORT_SYMBOL_GPL(viai2c_xfer);
126
127 /*
128 * Main process of the byte mode xfer
129 *
130 * Return value indicates whether the transfer is complete
131 * 1: all the data has been successfully transferred
132 * 0: there is still data that needs to be transferred
133 * -EIO: error occurred
134 */
viai2c_irq_xfer(struct viai2c * i2c)135 int viai2c_irq_xfer(struct viai2c *i2c)
136 {
137 u16 val;
138 struct i2c_msg *msg = i2c->msg;
139 u8 read = msg->flags & I2C_M_RD;
140 void __iomem *base = i2c->base;
141
142 if (read) {
143 msg->buf[i2c->xfered_len] = readw(base + VIAI2C_REG_CDR) >> 8;
144
145 val = readw(base + VIAI2C_REG_CR) | VIAI2C_CR_CPU_RDY;
146 if (i2c->xfered_len == msg->len - 2)
147 val |= VIAI2C_CR_RX_END;
148 writew(val, base + VIAI2C_REG_CR);
149 } else {
150 val = readw(base + VIAI2C_REG_CSR);
151 if (val & VIAI2C_CSR_RCV_NOT_ACK)
152 return -EIO;
153
154 /* I2C_SMBUS_QUICK */
155 if (msg->len == 0) {
156 val = VIAI2C_CR_TX_END | VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE;
157 writew(val, base + VIAI2C_REG_CR);
158 return 1;
159 }
160
161 if ((i2c->xfered_len + 1) == msg->len) {
162 if (i2c->platform == VIAI2C_PLAT_WMT && !i2c->last)
163 writew(VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR);
164 else if (i2c->platform == VIAI2C_PLAT_ZHAOXIN && i2c->last)
165 writeb(VIAI2C_CR_TX_END, base + VIAI2C_REG_CR);
166 } else {
167 writew(msg->buf[i2c->xfered_len + 1] & 0xFF, base + VIAI2C_REG_CDR);
168 writew(VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR);
169 }
170 }
171
172 i2c->xfered_len++;
173
174 return i2c->xfered_len == msg->len;
175 }
176 EXPORT_SYMBOL_GPL(viai2c_irq_xfer);
177
viai2c_init(struct platform_device * pdev,struct viai2c ** pi2c,int plat)178 int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat)
179 {
180 struct viai2c *i2c;
181
182 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
183 if (!i2c)
184 return -ENOMEM;
185
186 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
187 if (IS_ERR(i2c->base))
188 return PTR_ERR(i2c->base);
189
190 i2c->platform = plat;
191
192 i2c->dev = &pdev->dev;
193 init_completion(&i2c->complete);
194 platform_set_drvdata(pdev, i2c);
195
196 *pi2c = i2c;
197 return 0;
198 }
199 EXPORT_SYMBOL_GPL(viai2c_init);
200
201 MODULE_DESCRIPTION("Via/Wondermedia/Zhaoxin I2C controller core");
202 MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
203 MODULE_LICENSE("GPL");
204