1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3     i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus
4     - Based on i2c-piix4.c
5     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
6     Philip Edelbrock <phil@netroedge.com>
7     - Intel SCH support
8     Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com>
9 
10 */
11 
12 /*
13    Supports:
14 	Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L)
15    Note: we assume there can only be one device, with one SMBus interface.
16 */
17 
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/stddef.h>
23 #include <linux/ioport.h>
24 #include <linux/i2c.h>
25 #include <linux/io.h>
26 
27 /* SCH SMBus address offsets */
28 #define SMBHSTCNT	(0 + sch_smba)
29 #define SMBHSTSTS	(1 + sch_smba)
30 #define SMBHSTCLK	(2 + sch_smba)
31 #define SMBHSTADD	(4 + sch_smba) /* TSA */
32 #define SMBHSTCMD	(5 + sch_smba)
33 #define SMBHSTDAT0	(6 + sch_smba)
34 #define SMBHSTDAT1	(7 + sch_smba)
35 #define SMBBLKDAT	(0x20 + sch_smba)
36 
37 /* Other settings */
38 #define MAX_RETRIES	5000
39 
40 /* I2C constants */
41 #define SCH_QUICK		0x00
42 #define SCH_BYTE		0x01
43 #define SCH_BYTE_DATA		0x02
44 #define SCH_WORD_DATA		0x03
45 #define SCH_BLOCK_DATA		0x05
46 
47 static unsigned short sch_smba;
48 static struct i2c_adapter sch_adapter;
49 static int backbone_speed = 33000; /* backbone speed in kHz */
50 module_param(backbone_speed, int, S_IRUSR | S_IWUSR);
51 MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
52 
53 /*
54  * Start the i2c transaction -- the i2c_access will prepare the transaction
55  * and this function will execute it.
56  * return 0 for success and others for failure.
57  */
sch_transaction(void)58 static int sch_transaction(void)
59 {
60 	int temp;
61 	int result = 0;
62 	int retries = 0;
63 
64 	dev_dbg(&sch_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
65 		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
66 		inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
67 		inb(SMBHSTDAT1));
68 
69 	/* Make sure the SMBus host is ready to start transmitting */
70 	temp = inb(SMBHSTSTS) & 0x0f;
71 	if (temp) {
72 		/* Can not be busy since we checked it in sch_access */
73 		if (temp & 0x01) {
74 			dev_dbg(&sch_adapter.dev, "Completion (%02x). "
75 				"Clear...\n", temp);
76 		}
77 		if (temp & 0x06) {
78 			dev_dbg(&sch_adapter.dev, "SMBus error (%02x). "
79 				"Resetting...\n", temp);
80 		}
81 		outb(temp, SMBHSTSTS);
82 		temp = inb(SMBHSTSTS) & 0x0f;
83 		if (temp) {
84 			dev_err(&sch_adapter.dev,
85 				"SMBus is not ready: (%02x)\n", temp);
86 			return -EAGAIN;
87 		}
88 	}
89 
90 	/* start the transaction by setting bit 4 */
91 	outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT);
92 
93 	do {
94 		usleep_range(100, 200);
95 		temp = inb(SMBHSTSTS) & 0x0f;
96 	} while ((temp & 0x08) && (retries++ < MAX_RETRIES));
97 
98 	/* If the SMBus is still busy, we give up */
99 	if (retries > MAX_RETRIES) {
100 		dev_err(&sch_adapter.dev, "SMBus Timeout!\n");
101 		result = -ETIMEDOUT;
102 	} else if (temp & 0x04) {
103 		result = -EIO;
104 		dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be "
105 			"locked until next hard reset. (sorry!)\n");
106 		/* Clock stops and target is stuck in mid-transmission */
107 	} else if (temp & 0x02) {
108 		result = -EIO;
109 		dev_err(&sch_adapter.dev, "Error: no response!\n");
110 	} else if (temp & 0x01) {
111 		dev_dbg(&sch_adapter.dev, "Post complete!\n");
112 		outb(temp, SMBHSTSTS);
113 		temp = inb(SMBHSTSTS) & 0x07;
114 		if (temp & 0x06) {
115 			/* Completion clear failed */
116 			dev_dbg(&sch_adapter.dev, "Failed reset at end of "
117 				"transaction (%02x), Bus error!\n", temp);
118 		}
119 	} else {
120 		result = -ENXIO;
121 		dev_dbg(&sch_adapter.dev, "No such address.\n");
122 	}
123 	dev_dbg(&sch_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
124 		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
125 		inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
126 		inb(SMBHSTDAT1));
127 	return result;
128 }
129 
130 /*
131  * This is the main access entry for i2c-sch access
132  * adap is i2c_adapter pointer, addr is the i2c device bus address, read_write
133  * (0 for read and 1 for write), size is i2c transaction type and data is the
134  * union of transaction for data to be transferred or data read from bus.
135  * return 0 for success and others for failure.
136  */
sch_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)137 static s32 sch_access(struct i2c_adapter *adap, u16 addr,
138 		 unsigned short flags, char read_write,
139 		 u8 command, int size, union i2c_smbus_data *data)
140 {
141 	int i, len, temp, rc;
142 
143 	/* Make sure the SMBus host is not busy */
144 	temp = inb(SMBHSTSTS) & 0x0f;
145 	if (temp & 0x08) {
146 		dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
147 		return -EAGAIN;
148 	}
149 	temp = inw(SMBHSTCLK);
150 	if (!temp) {
151 		/*
152 		 * We can't determine if we have 33 or 25 MHz clock for
153 		 * SMBus, so expect 33 MHz and calculate a bus clock of
154 		 * 100 kHz. If we actually run at 25 MHz the bus will be
155 		 * run ~75 kHz instead which should do no harm.
156 		 */
157 		dev_notice(&sch_adapter.dev,
158 			"Clock divider uninitialized. Setting defaults\n");
159 		outw(backbone_speed / (4 * 100), SMBHSTCLK);
160 	}
161 
162 	dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
163 		(read_write)?"READ":"WRITE");
164 	switch (size) {
165 	case I2C_SMBUS_QUICK:
166 		outb((addr << 1) | read_write, SMBHSTADD);
167 		size = SCH_QUICK;
168 		break;
169 	case I2C_SMBUS_BYTE:
170 		outb((addr << 1) | read_write, SMBHSTADD);
171 		if (read_write == I2C_SMBUS_WRITE)
172 			outb(command, SMBHSTCMD);
173 		size = SCH_BYTE;
174 		break;
175 	case I2C_SMBUS_BYTE_DATA:
176 		outb((addr << 1) | read_write, SMBHSTADD);
177 		outb(command, SMBHSTCMD);
178 		if (read_write == I2C_SMBUS_WRITE)
179 			outb(data->byte, SMBHSTDAT0);
180 		size = SCH_BYTE_DATA;
181 		break;
182 	case I2C_SMBUS_WORD_DATA:
183 		outb((addr << 1) | read_write, SMBHSTADD);
184 		outb(command, SMBHSTCMD);
185 		if (read_write == I2C_SMBUS_WRITE) {
186 			outb(data->word & 0xff, SMBHSTDAT0);
187 			outb((data->word & 0xff00) >> 8, SMBHSTDAT1);
188 		}
189 		size = SCH_WORD_DATA;
190 		break;
191 	case I2C_SMBUS_BLOCK_DATA:
192 		outb((addr << 1) | read_write, SMBHSTADD);
193 		outb(command, SMBHSTCMD);
194 		if (read_write == I2C_SMBUS_WRITE) {
195 			len = data->block[0];
196 			if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
197 				return -EINVAL;
198 			outb(len, SMBHSTDAT0);
199 			for (i = 1; i <= len; i++)
200 				outb(data->block[i], SMBBLKDAT+i-1);
201 		}
202 		size = SCH_BLOCK_DATA;
203 		break;
204 	default:
205 		dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
206 		return -EOPNOTSUPP;
207 	}
208 	dev_dbg(&sch_adapter.dev, "write size %d to 0x%04x\n", size, SMBHSTCNT);
209 	outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT);
210 
211 	rc = sch_transaction();
212 	if (rc)	/* Error in transaction */
213 		return rc;
214 
215 	if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK))
216 		return 0;
217 
218 	switch (size) {
219 	case SCH_BYTE:
220 	case SCH_BYTE_DATA:
221 		data->byte = inb(SMBHSTDAT0);
222 		break;
223 	case SCH_WORD_DATA:
224 		data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8);
225 		break;
226 	case SCH_BLOCK_DATA:
227 		data->block[0] = inb(SMBHSTDAT0);
228 		if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
229 			return -EPROTO;
230 		for (i = 1; i <= data->block[0]; i++)
231 			data->block[i] = inb(SMBBLKDAT+i-1);
232 		break;
233 	}
234 	return 0;
235 }
236 
sch_func(struct i2c_adapter * adapter)237 static u32 sch_func(struct i2c_adapter *adapter)
238 {
239 	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
240 	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
241 	    I2C_FUNC_SMBUS_BLOCK_DATA;
242 }
243 
244 static const struct i2c_algorithm smbus_algorithm = {
245 	.smbus_xfer	= sch_access,
246 	.functionality	= sch_func,
247 };
248 
249 static struct i2c_adapter sch_adapter = {
250 	.owner		= THIS_MODULE,
251 	.class		= I2C_CLASS_HWMON,
252 	.algo		= &smbus_algorithm,
253 };
254 
smbus_sch_probe(struct platform_device * dev)255 static int smbus_sch_probe(struct platform_device *dev)
256 {
257 	struct resource *res;
258 	int retval;
259 
260 	res = platform_get_resource(dev, IORESOURCE_IO, 0);
261 	if (!res)
262 		return -EBUSY;
263 
264 	if (!devm_request_region(&dev->dev, res->start, resource_size(res),
265 				 dev->name)) {
266 		dev_err(&dev->dev, "SMBus region 0x%x already in use!\n",
267 			sch_smba);
268 		return -EBUSY;
269 	}
270 
271 	sch_smba = res->start;
272 
273 	dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba);
274 
275 	/* set up the sysfs linkage to our parent device */
276 	sch_adapter.dev.parent = &dev->dev;
277 
278 	snprintf(sch_adapter.name, sizeof(sch_adapter.name),
279 		"SMBus SCH adapter at %04x", sch_smba);
280 
281 	retval = i2c_add_adapter(&sch_adapter);
282 	if (retval)
283 		sch_smba = 0;
284 
285 	return retval;
286 }
287 
smbus_sch_remove(struct platform_device * pdev)288 static void smbus_sch_remove(struct platform_device *pdev)
289 {
290 	if (sch_smba) {
291 		i2c_del_adapter(&sch_adapter);
292 		sch_smba = 0;
293 	}
294 }
295 
296 static struct platform_driver smbus_sch_driver = {
297 	.driver = {
298 		.name = "isch_smbus",
299 	},
300 	.probe		= smbus_sch_probe,
301 	.remove_new	= smbus_sch_remove,
302 };
303 
304 module_platform_driver(smbus_sch_driver);
305 
306 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
307 MODULE_DESCRIPTION("Intel SCH SMBus driver");
308 MODULE_LICENSE("GPL");
309 MODULE_ALIAS("platform:isch_smbus");
310