1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Linaro Ltd
4 * Author: Sumit Semwal <sumit.semwal@linaro.org>
5 *
6 * This driver is for the DSI interface to panels using the NT36672A display driver IC
7 * from Novatek.
8 * Currently supported are the Tianma FHD+ panels found in some Xiaomi phones, including
9 * some variants of the Poco F1 phone.
10 *
11 * Panels using the Novatek NT37762A IC should add appropriate configuration per-panel and
12 * use this driver.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19
20 #include <linux/gpio/consumer.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <drm/drm_device.h>
25 #include <drm/drm_mipi_dsi.h>
26 #include <drm/drm_modes.h>
27 #include <drm/drm_panel.h>
28
29 #include <video/mipi_display.h>
30
31 struct nt36672a_panel_cmd {
32 const char data[2];
33 };
34
35 static const char * const nt36672a_regulator_names[] = {
36 "vddio",
37 "vddpos",
38 "vddneg",
39 };
40
41 static unsigned long const nt36672a_regulator_enable_loads[] = {
42 62000,
43 100000,
44 100000
45 };
46
47 struct nt36672a_panel_desc {
48 const struct drm_display_mode *display_mode;
49 const char *panel_name;
50
51 unsigned int width_mm;
52 unsigned int height_mm;
53
54 unsigned long mode_flags;
55 enum mipi_dsi_pixel_format format;
56 unsigned int lanes;
57
58 unsigned int num_on_cmds_1;
59 const struct nt36672a_panel_cmd *on_cmds_1;
60 unsigned int num_on_cmds_2;
61 const struct nt36672a_panel_cmd *on_cmds_2;
62
63 unsigned int num_off_cmds;
64 const struct nt36672a_panel_cmd *off_cmds;
65 };
66
67 struct nt36672a_panel {
68 struct drm_panel base;
69 struct mipi_dsi_device *link;
70 const struct nt36672a_panel_desc *desc;
71
72 struct regulator_bulk_data supplies[ARRAY_SIZE(nt36672a_regulator_names)];
73
74 struct gpio_desc *reset_gpio;
75 };
76
to_nt36672a_panel(struct drm_panel * panel)77 static inline struct nt36672a_panel *to_nt36672a_panel(struct drm_panel *panel)
78 {
79 return container_of(panel, struct nt36672a_panel, base);
80 }
81
nt36672a_send_cmds(struct drm_panel * panel,const struct nt36672a_panel_cmd * cmds,int num)82 static int nt36672a_send_cmds(struct drm_panel *panel, const struct nt36672a_panel_cmd *cmds,
83 int num)
84 {
85 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
86 unsigned int i;
87 int err;
88
89 for (i = 0; i < num; i++) {
90 const struct nt36672a_panel_cmd *cmd = &cmds[i];
91
92 err = mipi_dsi_dcs_write(pinfo->link, cmd->data[0], cmd->data + 1, 1);
93
94 if (err < 0)
95 return err;
96 }
97
98 return 0;
99 }
100
nt36672a_panel_power_off(struct drm_panel * panel)101 static int nt36672a_panel_power_off(struct drm_panel *panel)
102 {
103 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
104 int ret = 0;
105
106 gpiod_set_value(pinfo->reset_gpio, 1);
107
108 ret = regulator_bulk_disable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies);
109 if (ret)
110 dev_err(panel->dev, "regulator_bulk_disable failed %d\n", ret);
111
112 return ret;
113 }
114
nt36672a_panel_unprepare(struct drm_panel * panel)115 static int nt36672a_panel_unprepare(struct drm_panel *panel)
116 {
117 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
118 int ret;
119
120 /* send off cmds */
121 ret = nt36672a_send_cmds(panel, pinfo->desc->off_cmds,
122 pinfo->desc->num_off_cmds);
123
124 if (ret < 0)
125 dev_err(panel->dev, "failed to send DCS off cmds: %d\n", ret);
126
127 ret = mipi_dsi_dcs_set_display_off(pinfo->link);
128 if (ret < 0)
129 dev_err(panel->dev, "set_display_off cmd failed ret = %d\n", ret);
130
131 /* 120ms delay required here as per DCS spec */
132 msleep(120);
133
134 ret = mipi_dsi_dcs_enter_sleep_mode(pinfo->link);
135 if (ret < 0)
136 dev_err(panel->dev, "enter_sleep cmd failed ret = %d\n", ret);
137
138 /* 0x3C = 60ms delay */
139 msleep(60);
140
141 ret = nt36672a_panel_power_off(panel);
142 if (ret < 0)
143 dev_err(panel->dev, "power_off failed ret = %d\n", ret);
144
145 return ret;
146 }
147
nt36672a_panel_power_on(struct nt36672a_panel * pinfo)148 static int nt36672a_panel_power_on(struct nt36672a_panel *pinfo)
149 {
150 int ret;
151
152 ret = regulator_bulk_enable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies);
153 if (ret < 0)
154 return ret;
155
156 /*
157 * As per downstream kernel, Reset sequence of Tianma FHD panel requires the panel to
158 * be out of reset for 10ms, followed by being held in reset for 10ms. But for Android
159 * AOSP, we needed to bump it upto 200ms otherwise we get white screen sometimes.
160 * FIXME: Try to reduce this 200ms to a lesser value.
161 */
162 gpiod_set_value(pinfo->reset_gpio, 1);
163 msleep(200);
164 gpiod_set_value(pinfo->reset_gpio, 0);
165 msleep(200);
166
167 return 0;
168 }
169
nt36672a_panel_prepare(struct drm_panel * panel)170 static int nt36672a_panel_prepare(struct drm_panel *panel)
171 {
172 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
173 int err;
174
175 err = nt36672a_panel_power_on(pinfo);
176 if (err < 0)
177 goto poweroff;
178
179 /* send first part of init cmds */
180 err = nt36672a_send_cmds(panel, pinfo->desc->on_cmds_1,
181 pinfo->desc->num_on_cmds_1);
182
183 if (err < 0) {
184 dev_err(panel->dev, "failed to send DCS Init 1st Code: %d\n", err);
185 goto poweroff;
186 }
187
188 err = mipi_dsi_dcs_exit_sleep_mode(pinfo->link);
189 if (err < 0) {
190 dev_err(panel->dev, "failed to exit sleep mode: %d\n", err);
191 goto poweroff;
192 }
193
194 /* 0x46 = 70 ms delay */
195 msleep(70);
196
197 err = mipi_dsi_dcs_set_display_on(pinfo->link);
198 if (err < 0) {
199 dev_err(panel->dev, "failed to Set Display ON: %d\n", err);
200 goto poweroff;
201 }
202
203 /* Send rest of the init cmds */
204 err = nt36672a_send_cmds(panel, pinfo->desc->on_cmds_2,
205 pinfo->desc->num_on_cmds_2);
206
207 if (err < 0) {
208 dev_err(panel->dev, "failed to send DCS Init 2nd Code: %d\n", err);
209 goto poweroff;
210 }
211
212 msleep(120);
213
214 return 0;
215
216 poweroff:
217 gpiod_set_value(pinfo->reset_gpio, 0);
218 return err;
219 }
220
nt36672a_panel_get_modes(struct drm_panel * panel,struct drm_connector * connector)221 static int nt36672a_panel_get_modes(struct drm_panel *panel,
222 struct drm_connector *connector)
223 {
224 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
225 const struct drm_display_mode *m = pinfo->desc->display_mode;
226 struct drm_display_mode *mode;
227
228 mode = drm_mode_duplicate(connector->dev, m);
229 if (!mode) {
230 dev_err(panel->dev, "failed to add mode %ux%u@%u\n", m->hdisplay,
231 m->vdisplay, drm_mode_vrefresh(m));
232 return -ENOMEM;
233 }
234
235 connector->display_info.width_mm = pinfo->desc->width_mm;
236 connector->display_info.height_mm = pinfo->desc->height_mm;
237
238 drm_mode_set_name(mode);
239 drm_mode_probed_add(connector, mode);
240
241 return 1;
242 }
243
244 static const struct drm_panel_funcs panel_funcs = {
245 .unprepare = nt36672a_panel_unprepare,
246 .prepare = nt36672a_panel_prepare,
247 .get_modes = nt36672a_panel_get_modes,
248 };
249
250 static const struct nt36672a_panel_cmd tianma_fhd_video_on_cmds_1[] = {
251 /* skin enhancement mode */
252 { .data = {0xFF, 0x22} },
253 { .data = {0x00, 0x40} },
254 { .data = {0x01, 0xC0} },
255 { .data = {0x02, 0x40} },
256 { .data = {0x03, 0x40} },
257 { .data = {0x04, 0x40} },
258 { .data = {0x05, 0x40} },
259 { .data = {0x06, 0x40} },
260 { .data = {0x07, 0x40} },
261 { .data = {0x08, 0x40} },
262 { .data = {0x09, 0x40} },
263 { .data = {0x0A, 0x40} },
264 { .data = {0x0B, 0x40} },
265 { .data = {0x0C, 0x40} },
266 { .data = {0x0D, 0x40} },
267 { .data = {0x0E, 0x40} },
268 { .data = {0x0F, 0x40} },
269 { .data = {0x10, 0x40} },
270 { .data = {0x11, 0x50} },
271 { .data = {0x12, 0x60} },
272 { .data = {0x13, 0x70} },
273 { .data = {0x14, 0x58} },
274 { .data = {0x15, 0x68} },
275 { .data = {0x16, 0x78} },
276 { .data = {0x17, 0x77} },
277 { .data = {0x18, 0x39} },
278 { .data = {0x19, 0x2D} },
279 { .data = {0x1A, 0x2E} },
280 { .data = {0x1B, 0x32} },
281 { .data = {0x1C, 0x37} },
282 { .data = {0x1D, 0x3A} },
283 { .data = {0x1E, 0x40} },
284 { .data = {0x1F, 0x40} },
285 { .data = {0x20, 0x40} },
286 { .data = {0x21, 0x40} },
287 { .data = {0x22, 0x40} },
288 { .data = {0x23, 0x40} },
289 { .data = {0x24, 0x40} },
290 { .data = {0x25, 0x40} },
291 { .data = {0x26, 0x40} },
292 { .data = {0x27, 0x40} },
293 { .data = {0x28, 0x40} },
294 { .data = {0x2D, 0x00} },
295 { .data = {0x2F, 0x40} },
296 { .data = {0x30, 0x40} },
297 { .data = {0x31, 0x40} },
298 { .data = {0x32, 0x40} },
299 { .data = {0x33, 0x40} },
300 { .data = {0x34, 0x40} },
301 { .data = {0x35, 0x40} },
302 { .data = {0x36, 0x40} },
303 { .data = {0x37, 0x40} },
304 { .data = {0x38, 0x40} },
305 { .data = {0x39, 0x40} },
306 { .data = {0x3A, 0x40} },
307 { .data = {0x3B, 0x40} },
308 { .data = {0x3D, 0x40} },
309 { .data = {0x3F, 0x40} },
310 { .data = {0x40, 0x40} },
311 { .data = {0x41, 0x40} },
312 { .data = {0x42, 0x40} },
313 { .data = {0x43, 0x40} },
314 { .data = {0x44, 0x40} },
315 { .data = {0x45, 0x40} },
316 { .data = {0x46, 0x40} },
317 { .data = {0x47, 0x40} },
318 { .data = {0x48, 0x40} },
319 { .data = {0x49, 0x40} },
320 { .data = {0x4A, 0x40} },
321 { .data = {0x4B, 0x40} },
322 { .data = {0x4C, 0x40} },
323 { .data = {0x4D, 0x40} },
324 { .data = {0x4E, 0x40} },
325 { .data = {0x4F, 0x40} },
326 { .data = {0x50, 0x40} },
327 { .data = {0x51, 0x40} },
328 { .data = {0x52, 0x40} },
329 { .data = {0x53, 0x01} },
330 { .data = {0x54, 0x01} },
331 { .data = {0x55, 0xFE} },
332 { .data = {0x56, 0x77} },
333 { .data = {0x58, 0xCD} },
334 { .data = {0x59, 0xD0} },
335 { .data = {0x5A, 0xD0} },
336 { .data = {0x5B, 0x50} },
337 { .data = {0x5C, 0x50} },
338 { .data = {0x5D, 0x50} },
339 { .data = {0x5E, 0x50} },
340 { .data = {0x5F, 0x50} },
341 { .data = {0x60, 0x50} },
342 { .data = {0x61, 0x50} },
343 { .data = {0x62, 0x50} },
344 { .data = {0x63, 0x50} },
345 { .data = {0x64, 0x50} },
346 { .data = {0x65, 0x50} },
347 { .data = {0x66, 0x50} },
348 { .data = {0x67, 0x50} },
349 { .data = {0x68, 0x50} },
350 { .data = {0x69, 0x50} },
351 { .data = {0x6A, 0x50} },
352 { .data = {0x6B, 0x50} },
353 { .data = {0x6C, 0x50} },
354 { .data = {0x6D, 0x50} },
355 { .data = {0x6E, 0x50} },
356 { .data = {0x6F, 0x50} },
357 { .data = {0x70, 0x07} },
358 { .data = {0x71, 0x00} },
359 { .data = {0x72, 0x00} },
360 { .data = {0x73, 0x00} },
361 { .data = {0x74, 0x06} },
362 { .data = {0x75, 0x0C} },
363 { .data = {0x76, 0x03} },
364 { .data = {0x77, 0x09} },
365 { .data = {0x78, 0x0F} },
366 { .data = {0x79, 0x68} },
367 { .data = {0x7A, 0x88} },
368 { .data = {0x7C, 0x80} },
369 { .data = {0x7D, 0x80} },
370 { .data = {0x7E, 0x80} },
371 { .data = {0x7F, 0x00} },
372 { .data = {0x80, 0x00} },
373 { .data = {0x81, 0x00} },
374 { .data = {0x83, 0x01} },
375 { .data = {0x84, 0x00} },
376 { .data = {0x85, 0x80} },
377 { .data = {0x86, 0x80} },
378 { .data = {0x87, 0x80} },
379 { .data = {0x88, 0x40} },
380 { .data = {0x89, 0x91} },
381 { .data = {0x8A, 0x98} },
382 { .data = {0x8B, 0x80} },
383 { .data = {0x8C, 0x80} },
384 { .data = {0x8D, 0x80} },
385 { .data = {0x8E, 0x80} },
386 { .data = {0x8F, 0x80} },
387 { .data = {0x90, 0x80} },
388 { .data = {0x91, 0x80} },
389 { .data = {0x92, 0x80} },
390 { .data = {0x93, 0x80} },
391 { .data = {0x94, 0x80} },
392 { .data = {0x95, 0x80} },
393 { .data = {0x96, 0x80} },
394 { .data = {0x97, 0x80} },
395 { .data = {0x98, 0x80} },
396 { .data = {0x99, 0x80} },
397 { .data = {0x9A, 0x80} },
398 { .data = {0x9B, 0x80} },
399 { .data = {0x9C, 0x80} },
400 { .data = {0x9D, 0x80} },
401 { .data = {0x9E, 0x80} },
402 { .data = {0x9F, 0x80} },
403 { .data = {0xA0, 0x8A} },
404 { .data = {0xA2, 0x80} },
405 { .data = {0xA6, 0x80} },
406 { .data = {0xA7, 0x80} },
407 { .data = {0xA9, 0x80} },
408 { .data = {0xAA, 0x80} },
409 { .data = {0xAB, 0x80} },
410 { .data = {0xAC, 0x80} },
411 { .data = {0xAD, 0x80} },
412 { .data = {0xAE, 0x80} },
413 { .data = {0xAF, 0x80} },
414 { .data = {0xB7, 0x76} },
415 { .data = {0xB8, 0x76} },
416 { .data = {0xB9, 0x05} },
417 { .data = {0xBA, 0x0D} },
418 { .data = {0xBB, 0x14} },
419 { .data = {0xBC, 0x0F} },
420 { .data = {0xBD, 0x18} },
421 { .data = {0xBE, 0x1F} },
422 { .data = {0xBF, 0x05} },
423 { .data = {0xC0, 0x0D} },
424 { .data = {0xC1, 0x14} },
425 { .data = {0xC2, 0x03} },
426 { .data = {0xC3, 0x07} },
427 { .data = {0xC4, 0x0A} },
428 { .data = {0xC5, 0xA0} },
429 { .data = {0xC6, 0x55} },
430 { .data = {0xC7, 0xFF} },
431 { .data = {0xC8, 0x39} },
432 { .data = {0xC9, 0x44} },
433 { .data = {0xCA, 0x12} },
434 { .data = {0xCD, 0x80} },
435 { .data = {0xDB, 0x80} },
436 { .data = {0xDC, 0x80} },
437 { .data = {0xDD, 0x80} },
438 { .data = {0xE0, 0x80} },
439 { .data = {0xE1, 0x80} },
440 { .data = {0xE2, 0x80} },
441 { .data = {0xE3, 0x80} },
442 { .data = {0xE4, 0x80} },
443 { .data = {0xE5, 0x40} },
444 { .data = {0xE6, 0x40} },
445 { .data = {0xE7, 0x40} },
446 { .data = {0xE8, 0x40} },
447 { .data = {0xE9, 0x40} },
448 { .data = {0xEA, 0x40} },
449 { .data = {0xEB, 0x40} },
450 { .data = {0xEC, 0x40} },
451 { .data = {0xED, 0x40} },
452 { .data = {0xEE, 0x40} },
453 { .data = {0xEF, 0x40} },
454 { .data = {0xF0, 0x40} },
455 { .data = {0xF1, 0x40} },
456 { .data = {0xF2, 0x40} },
457 { .data = {0xF3, 0x40} },
458 { .data = {0xF4, 0x40} },
459 { .data = {0xF5, 0x40} },
460 { .data = {0xF6, 0x40} },
461 { .data = {0xFB, 0x1} },
462 { .data = {0xFF, 0x23} },
463 { .data = {0xFB, 0x01} },
464 /* dimming enable */
465 { .data = {0x01, 0x84} },
466 { .data = {0x05, 0x2D} },
467 { .data = {0x06, 0x00} },
468 /* resolution 1080*2246 */
469 { .data = {0x11, 0x01} },
470 { .data = {0x12, 0x7B} },
471 { .data = {0x15, 0x6F} },
472 { .data = {0x16, 0x0B} },
473 /* UI mode */
474 { .data = {0x29, 0x0A} },
475 { .data = {0x30, 0xFF} },
476 { .data = {0x31, 0xFF} },
477 { .data = {0x32, 0xFF} },
478 { .data = {0x33, 0xFF} },
479 { .data = {0x34, 0xFF} },
480 { .data = {0x35, 0xFF} },
481 { .data = {0x36, 0xFF} },
482 { .data = {0x37, 0xFF} },
483 { .data = {0x38, 0xFC} },
484 { .data = {0x39, 0xF8} },
485 { .data = {0x3A, 0xF4} },
486 { .data = {0x3B, 0xF1} },
487 { .data = {0x3D, 0xEE} },
488 { .data = {0x3F, 0xEB} },
489 { .data = {0x40, 0xE8} },
490 { .data = {0x41, 0xE5} },
491 /* STILL mode */
492 { .data = {0x2A, 0x13} },
493 { .data = {0x45, 0xFF} },
494 { .data = {0x46, 0xFF} },
495 { .data = {0x47, 0xFF} },
496 { .data = {0x48, 0xFF} },
497 { .data = {0x49, 0xFF} },
498 { .data = {0x4A, 0xFF} },
499 { .data = {0x4B, 0xFF} },
500 { .data = {0x4C, 0xFF} },
501 { .data = {0x4D, 0xED} },
502 { .data = {0x4E, 0xD5} },
503 { .data = {0x4F, 0xBF} },
504 { .data = {0x50, 0xA6} },
505 { .data = {0x51, 0x96} },
506 { .data = {0x52, 0x86} },
507 { .data = {0x53, 0x76} },
508 { .data = {0x54, 0x66} },
509 /* MOVING mode */
510 { .data = {0x2B, 0x0E} },
511 { .data = {0x58, 0xFF} },
512 { .data = {0x59, 0xFF} },
513 { .data = {0x5A, 0xFF} },
514 { .data = {0x5B, 0xFF} },
515 { .data = {0x5C, 0xFF} },
516 { .data = {0x5D, 0xFF} },
517 { .data = {0x5E, 0xFF} },
518 { .data = {0x5F, 0xFF} },
519 { .data = {0x60, 0xF6} },
520 { .data = {0x61, 0xEA} },
521 { .data = {0x62, 0xE1} },
522 { .data = {0x63, 0xD8} },
523 { .data = {0x64, 0xCE} },
524 { .data = {0x65, 0xC3} },
525 { .data = {0x66, 0xBA} },
526 { .data = {0x67, 0xB3} },
527 { .data = {0xFF, 0x25} },
528 { .data = {0xFB, 0x01} },
529 { .data = {0x05, 0x04} },
530 { .data = {0xFF, 0x26} },
531 { .data = {0xFB, 0x01} },
532 { .data = {0x1C, 0xAF} },
533 { .data = {0xFF, 0x10} },
534 { .data = {0xFB, 0x01} },
535 { .data = {0x51, 0xFF} },
536 { .data = {0x53, 0x24} },
537 { .data = {0x55, 0x00} },
538 };
539
540 static const struct nt36672a_panel_cmd tianma_fhd_video_on_cmds_2[] = {
541 { .data = {0xFF, 0x24} },
542 { .data = {0xFB, 0x01} },
543 { .data = {0xC3, 0x01} },
544 { .data = {0xC4, 0x54} },
545 { .data = {0xFF, 0x10} },
546 };
547
548 static const struct nt36672a_panel_cmd tianma_fhd_video_off_cmds[] = {
549 { .data = {0xFF, 0x24} },
550 { .data = {0xFB, 0x01} },
551 { .data = {0xC3, 0x01} },
552 { .data = {0xFF, 0x10} },
553 };
554
555 static const struct drm_display_mode tianma_fhd_video_panel_default_mode = {
556 .clock = 161331,
557
558 .hdisplay = 1080,
559 .hsync_start = 1080 + 40,
560 .hsync_end = 1080 + 40 + 20,
561 .htotal = 1080 + 40 + 20 + 44,
562
563 .vdisplay = 2246,
564 .vsync_start = 2246 + 15,
565 .vsync_end = 2246 + 15 + 2,
566 .vtotal = 2246 + 15 + 2 + 8,
567
568 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
569 };
570
571 static const struct nt36672a_panel_desc tianma_fhd_video_panel_desc = {
572 .display_mode = &tianma_fhd_video_panel_default_mode,
573
574 .width_mm = 68,
575 .height_mm = 136,
576
577 .mode_flags = MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO
578 | MIPI_DSI_MODE_VIDEO_HSE
579 | MIPI_DSI_CLOCK_NON_CONTINUOUS
580 | MIPI_DSI_MODE_VIDEO_BURST,
581 .format = MIPI_DSI_FMT_RGB888,
582 .lanes = 4,
583 .on_cmds_1 = tianma_fhd_video_on_cmds_1,
584 .num_on_cmds_1 = ARRAY_SIZE(tianma_fhd_video_on_cmds_1),
585 .on_cmds_2 = tianma_fhd_video_on_cmds_2,
586 .num_on_cmds_2 = ARRAY_SIZE(tianma_fhd_video_on_cmds_2),
587 .off_cmds = tianma_fhd_video_off_cmds,
588 .num_off_cmds = ARRAY_SIZE(tianma_fhd_video_off_cmds),
589 };
590
nt36672a_panel_add(struct nt36672a_panel * pinfo)591 static int nt36672a_panel_add(struct nt36672a_panel *pinfo)
592 {
593 struct device *dev = &pinfo->link->dev;
594 int i, ret;
595
596 for (i = 0; i < ARRAY_SIZE(pinfo->supplies); i++) {
597 pinfo->supplies[i].supply = nt36672a_regulator_names[i];
598 pinfo->supplies[i].init_load_uA = nt36672a_regulator_enable_loads[i];
599 }
600
601 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pinfo->supplies),
602 pinfo->supplies);
603 if (ret < 0)
604 return dev_err_probe(dev, ret, "failed to get regulators\n");
605
606 pinfo->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
607 if (IS_ERR(pinfo->reset_gpio))
608 return dev_err_probe(dev, PTR_ERR(pinfo->reset_gpio),
609 "failed to get reset gpio from DT\n");
610
611 drm_panel_init(&pinfo->base, dev, &panel_funcs, DRM_MODE_CONNECTOR_DSI);
612
613 ret = drm_panel_of_backlight(&pinfo->base);
614 if (ret)
615 return dev_err_probe(dev, ret, "Failed to get backlight\n");
616
617 drm_panel_add(&pinfo->base);
618
619 return 0;
620 }
621
nt36672a_panel_probe(struct mipi_dsi_device * dsi)622 static int nt36672a_panel_probe(struct mipi_dsi_device *dsi)
623 {
624 struct nt36672a_panel *pinfo;
625 const struct nt36672a_panel_desc *desc;
626 int err;
627
628 pinfo = devm_kzalloc(&dsi->dev, sizeof(*pinfo), GFP_KERNEL);
629 if (!pinfo)
630 return -ENOMEM;
631
632 desc = of_device_get_match_data(&dsi->dev);
633 dsi->mode_flags = desc->mode_flags;
634 dsi->format = desc->format;
635 dsi->lanes = desc->lanes;
636 pinfo->desc = desc;
637 pinfo->link = dsi;
638
639 mipi_dsi_set_drvdata(dsi, pinfo);
640
641 err = nt36672a_panel_add(pinfo);
642 if (err < 0)
643 return err;
644
645 err = mipi_dsi_attach(dsi);
646 if (err < 0) {
647 drm_panel_remove(&pinfo->base);
648 return err;
649 }
650
651 return 0;
652 }
653
nt36672a_panel_remove(struct mipi_dsi_device * dsi)654 static void nt36672a_panel_remove(struct mipi_dsi_device *dsi)
655 {
656 struct nt36672a_panel *pinfo = mipi_dsi_get_drvdata(dsi);
657 int err;
658
659 err = mipi_dsi_detach(dsi);
660 if (err < 0)
661 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
662
663 drm_panel_remove(&pinfo->base);
664 }
665
666 static const struct of_device_id tianma_fhd_video_of_match[] = {
667 { .compatible = "tianma,fhd-video", .data = &tianma_fhd_video_panel_desc },
668 { },
669 };
670 MODULE_DEVICE_TABLE(of, tianma_fhd_video_of_match);
671
672 static struct mipi_dsi_driver nt36672a_panel_driver = {
673 .driver = {
674 .name = "panel-tianma-nt36672a",
675 .of_match_table = tianma_fhd_video_of_match,
676 },
677 .probe = nt36672a_panel_probe,
678 .remove = nt36672a_panel_remove,
679 };
680 module_mipi_dsi_driver(nt36672a_panel_driver);
681
682 MODULE_AUTHOR("Sumit Semwal <sumit.semwal@linaro.org>");
683 MODULE_DESCRIPTION("NOVATEK NT36672A based MIPI-DSI LCD panel driver");
684 MODULE_LICENSE("GPL");
685